source: PlatformSupport/XBD/boards/Rice_University_WARP_FPGA_V2P70_LogicClkBoard/data/Rice_University_WARP_FPGA_V2P70_LogicClkBoard_v2_2_0.xbd

# -------------------------------------------------------------
#  Copyright (c) 2006 Rice University
#  All Rights Reserved
#  This code is covered by the Rice-WARP license
#  See http://warp.rice.edu/license/ for details
# -------------------------------------------------------------

# Define the attributes of the board that will be displayed when listing the board. 
ATTRIBUTE VENDOR = Rice University - WARP Project 
ATTRIBUTE SPEC_URL = http://warp.rice.edu/
ATTRIBUTE CONTACT_INFO_URL= http://warp.rice.edu/
ATTRIBUTE NAME = WARP Kits (FPGA/Clock/Radio Boards)
ATTRIBUTE REVISION = FPGA 1.2 / Radio 1.4 / Clock 1.1
ATTRIBUTE DESC = Rice University WARP
ATTRIBUTE LONG_DESC = 'This board utilizes a Xilinx Virtex-II Pro FPGA XC2VP70-FF1517-6C. This XBD enables: 4 LEDs, 2 Hex Displays, 1 Reset Button, 4 Push-Buttons, SystemACE CompactFlash MCU interface, UART, 2 512kx32b ZBT SRAMs, Ethernet & OneWire EEPROM. It includes support for the 4-slot radio controller and radio and analog bridges. It configures the XPS clock_generator to be driven by the clock board 40MHz logic/converter oscillator.'
# Defining hardware interfaces

# Define the first clock which is the processor clock. IOTYPE = XIL_CLOCK_V1 defines a general clock.
# port name can be named as desired but remain consistent when defining the pins in the FPGA section.
BEGIN IO_INTERFACE
    ATTRIBUTE IOTYPE = XIL_CLOCK_V1
    ATTRIBUTE INSTANCE =GCLK0
    PARAMETER CLK_FREQ = 40000000, IO_IS=clk_freq, RANGE=(40000000) # 40 MHz
    PORT GCLK6P = CONN_GCLK0_GCLK6P , IO_IS=ext_clk
    PORT RST = clkConfigInvalid
END

# Defines the reset interface.  Currently set to use first push button
BEGIN IO_INTERFACE
    ATTRIBUTE IOTYPE = XIL_RESET_V1
    ATTRIBUTE INSTANCE = rst_0
    PARAMETER RST_POLARITY =1, IO_IS=polarity, VALUE_NOTE=Active HIGH
    PORT INIT =  CONN_INIT_INIT, IO_IS=ext_rst
END

# A single GPIO core is used to interface with:
#  4 user LEDs (4-bits)
#  2 7-segment displays (14-bits)
#  4 push buttons (4-bits)
#  DIP switch (4-bits)
BEGIN IO_INTERFACE
    ATTRIBUTE IOTYPE = XIL_GPIO_V1
    ATTRIBUTE INSTANCE = USER_IO
    PARAMETER num_bits = 18, IO_IS=num_bits
    PARAMETER is_dual=1, IO_IS=is_dual          # Single channel
    PARAMETER bidir_data = 0, IO_IS=is_bidir    # No bi-directional I/O
    PARAMETER all_inputs = 1, IO_IS=all_inputs  # Channel 1 is all inputs
    PARAMETER bidir_data_2 = 1, IO_IS=is_bidir_2    # 
    PARAMETER all_inputs_2 = 0, IO_IS=all_inputs_2  # Channel 2 is all outputs

    #Channel 1 - User Inputs (buttons and switches)
    PORT SW_0 = SW_0, IO_IS = gpio_data_in[0]
    PORT SW_1 = SW_1, IO_IS = gpio_data_in[1]
    PORT SW_2 = SW_2, IO_IS = gpio_data_in[2]
    PORT SW_3 = SW_3, IO_IS = gpio_data_in[3]

    PORT PUSHU = CONN_PUSHU, IO_IS = gpio_data_in[4]
    PORT PUSHL = CONN_PUSHL, IO_IS = gpio_data_in[5]
    PORT PUSHR = CONN_PUSHR, IO_IS = gpio_data_in[6]
    PORT PUSHC = CONN_PUSHC, IO_IS = gpio_data_in[7]

    #Channel 2 - User Outputs (LEDs and hex displays)
    PORT SEG_LED0 = CONN_0_SEG1, IO_IS = gpio_data_out_2[0]
    PORT SEG_LED1 = CONN_0_SEG2, IO_IS = gpio_data_out_2[1]
    PORT SEG_LED2 = CONN_0_SEG3, IO_IS = gpio_data_out_2[2]
    PORT SEG_LED3 = CONN_0_SEG4, IO_IS = gpio_data_out_2[3]
    PORT SEG_LED4 = CONN_0_SEG5, IO_IS = gpio_data_out_2[4]
    PORT SEG_LED5 = CONN_0_SEG6, IO_IS = gpio_data_out_2[5]
    PORT SEG_LED6 = CONN_0_SEG7, IO_IS = gpio_data_out_2[6]

    PORT SEG_1_LED0 = CONN_1_SEG1, IO_IS = gpio_data_out_2[7]
    PORT SEG_1_LED1 = CONN_1_SEG2, IO_IS = gpio_data_out_2[8]
    PORT SEG_1_LED2 = CONN_1_SEG3, IO_IS = gpio_data_out_2[9]
    PORT SEG_1_LED3 = CONN_1_SEG4, IO_IS = gpio_data_out_2[10]
    PORT SEG_1_LED4 = CONN_1_SEG5, IO_IS = gpio_data_out_2[11]
    PORT SEG_1_LED5 = CONN_1_SEG6, IO_IS = gpio_data_out_2[12]
    PORT SEG_1_LED6 = CONN_1_SEG7, IO_IS = gpio_data_out_2[13]
    
    PORT LED0 = CONN_LEDs_LED0, IO_IS = gpio_data_out_2[14]
    PORT LED1 = CONN_LEDs_LED1, IO_IS = gpio_data_out_2[15]
    PORT LED2 = CONN_LEDs_LED2, IO_IS = gpio_data_out_2[16]
    PORT LED3 = CONN_LEDs_LED3, IO_IS = gpio_data_out_2[17]
END       

# This is the serial port.
BEGIN IO_INTERFACE
    ATTRIBUTE IOTYPE = XIL_UART_V1
    ATTRIBUTE INSTANCE = rs232
    PORT RXD = CONN_RXD, IO_IS=serial_in
    PORT TXD = CONN_TXD, IO_IS=serial_out
END       

# SystemACE Compact Flash microprocessor interface
BEGIN IO_INTERFACE
    ATTRIBUTE IOTYPE = XIL_SYSACE_V1
    ATTRIBUTE INSTANCE = sysace_compactflash
    PARAMETER C_MEM_WIDTH =16, IO_IS=mem_data_bus_width  
    PORT X104_5_OUT = sysace_clk, IO_IS=clk_in
    PORT X104_1_OE = sysace_clk_oe_n, IO_IS=clk_enable_n, INITIALVAL = VCC 
    PORT MPA00 = sysace_mpa_0, IO_IS = address[0] 
    PORT MPA01 = sysace_mpa_1, IO_IS = address[1] 
    PORT MPA02 = sysace_mpa_2, IO_IS = address[2] 
    PORT MPA03 = sysace_mpa_3, IO_IS = address[3] 
    PORT MPA04 = sysace_mpa_4, IO_IS = address[4] 
    PORT MPA05 = sysace_mpa_5, IO_IS = address[5] 
    PORT MPA06 = sysace_mpa_6, IO_IS = address[6] 
    PORT MPD00 = sysace_mpd_0, IO_IS = data[0]    
    PORT MPD01 = sysace_mpd_1, IO_IS = data[1]    
    PORT MPD02 = sysace_mpd_2, IO_IS = data[2]    
    PORT MPD03 = sysace_mpd_3, IO_IS = data[3]    
    PORT MPD04 = sysace_mpd_4, IO_IS = data[4]    
    PORT MPD05 = sysace_mpd_5, IO_IS = data[5]    
    PORT MPD06 = sysace_mpd_6, IO_IS = data[6]    
    PORT MPD07 = sysace_mpd_7, IO_IS = data[7]
    PORT MPD08 = sysace_mpd_8, IO_IS = data[8]
    PORT MPD09 = sysace_mpd_9, IO_IS = data[9]
    PORT MPD10 = sysace_mpd_10, IO_IS = data[10] 
    PORT MPD11 = sysace_mpd_11, IO_IS = data[11] 
    PORT MPD12 = sysace_mpd_12, IO_IS = data[12] 
    PORT MPD13 = sysace_mpd_13, IO_IS = data[13] 
    PORT MPD14 = sysace_mpd_14, IO_IS = data[14] 
    PORT MPD15 = sysace_mpd_15, IO_IS = data[15] 
    PORT MPCE  = sysace_mpce, IO_IS=chip_enable  
    PORT MPOE  = sysace_mpoe, IO_IS=output_enable
    PORT MPWE  = sysace_mpwe, IO_IS=write_enable 
    PORT MPIRQ = sysace_mpirq, IO_IS=intr_out     
END

BEGIN IO_INTERFACE
    ATTRIBUTE IOTYPE = WARP_CLKBRD_CONFIG_V1
    ATTRIBUTE INSTANCE = clk_board_config

    PORT sys_clk = clk100_osc #Off-chip clock- required for proper startup!
    PORT sys_rst = net_gnd
    PORT cfg_radio_dat_out = clk_board_radio_DO
    PORT cfg_radio_csb_out = clk_board_radio_CS
    PORT cfg_radio_en_out = clk_board_radio_EN
    PORT cfg_radio_clk_out = clk_board_radio_CLK
    PORT cfg_logic_dat_out = clk_board_logic_DO
    PORT cfg_logic_csb_out = clk_board_logic_CS
    PORT cfg_logic_en_out = clk_board_logic_EN
    PORT cfg_logic_clk_out = clk_board_logic_CLK
    PORT config_invalid = clkConfigInvalid
END

# EEPROM Serial Number and Memory interface
BEGIN IO_INTERFACE
    ATTRIBUTE IOTYPE = WARP_EEPROM_V1
    ATTRIBUTE INSTANCE = eeprom_controller
    PORT DQ0   = EEPROM_0_DQ0, INITIALVAL = VCC
#   PORT DQ0_T = 
#   PORT DQ0_O = 
#   PORT DQ0_I =

#   PORT DQ1   =
    PORT DQ1_T = DQ1_T_user_EEPROM_IO_T
    PORT DQ1_O = DQ1_O_user_EEPROM_IO_O
    PORT DQ1_I = DQ1_I_user_EEPROM_IO_I, INITIALVAL = VCC

#   PORT DQ2   =
    PORT DQ2_T = DQ2_T_user_EEPROM_IO_T
    PORT DQ2_O = DQ2_O_user_EEPROM_IO_O
    PORT DQ2_I = DQ2_I_user_EEPROM_IO_I, INITIALVAL = VCC

#   PORT DQ3   =
    PORT DQ3_T = DQ3_T_user_EEPROM_IO_T
    PORT DQ3_O = DQ3_O_user_EEPROM_IO_O
    PORT DQ3_I = DQ3_I_user_EEPROM_IO_I, INITIALVAL = VCC

#   PORT DQ4   =
    PORT DQ4_T = DQ4_T_user_EEPROM_IO_T
    PORT DQ4_O = DQ4_O_user_EEPROM_IO_O
    PORT DQ4_I = DQ4_I_user_EEPROM_IO_I, INITIALVAL = VCC

#   PORT DQ5   =
#   PORT DQ5_T =
#   PORT DQ5_O =
    PORT DQ5_I = "net_vcc"

#   PORT DQ6   =
#   PORT DQ6_T =
#   PORT DQ6_O =
    PORT DQ6_I = "net_vcc"

#   PORT DQ7   =
#   PORT DQ7_T =
#   PORT DQ7_O =
    PORT DQ7_I = "net_vcc"
END

# LTX972A Ethernet MAC (10/100)
BEGIN IO_INTERFACE
    ATTRIBUTE IOTYPE = XIL_ETHERNET_V1
    ATTRIBUTE INSTANCE = Ethernet_MAC
    PORT TXSLEW0  = phy_slew0, IO_IS=slew1,      INITIALVAL = VCC
    PORT TXSLEW1  = phy_slew1, IO_IS=slew2,      INITIALVAL = VCC
    PORT RESET    = phy_rst_n, IO_IS=PHY_RESETn, INITIALVAL = VCC
    PORT MDINT    = phy_mii_int_n, IO_IS = mii_int_n
    PORT CRS      = phy_crs,       IO_IS = ETH_CRS
    PORT COL      = phy_col,       IO_IS = ETH_COL
    PORT TXD3     = phy_tx_data_3, IO_IS = ETH_TXD[3]
    PORT TXD2     = phy_tx_data_2, IO_IS = ETH_TXD[2]
    PORT TXD1     = phy_tx_data_1, IO_IS = ETH_TXD[1]
    PORT TXD0     = phy_tx_data_0, IO_IS = ETH_TXD[0]
    PORT TX_EN    = phy_tx_en,     IO_IS = ETH_TXEN
    PORT TX_CLK   = phy_tx_clk,    IO_IS = ETH_TXC
    PORT TX_ER    = phy_tx_er,     IO_IS = ETH_TXER
    PORT RX_ER    = phy_rx_er,     IO_IS = ETH_RXER
    PORT RX_CLK   = phy_rx_clk,    IO_IS = ETH_RXC
    PORT RX_DV    = phy_dv,        IO_IS = ETH_RXDV
    PORT RXD0     = phy_rx_data_0, IO_IS = ETH_RXD[0]
    PORT RXD1     = phy_rx_data_1, IO_IS = ETH_RXD[1]
    PORT RXD2     = phy_rx_data_2, IO_IS = ETH_RXD[2]
    PORT RXD3     = phy_rx_data_3, IO_IS = ETH_RXD[3]
    PORT PHY_MDC  = phy_mii_clk,   IO_IS = ETH_MDC
    PORT PHY_MDIO = phy_mii_data,  IO_IS = ETH_MDIO
END


# Radio Controller
BEGIN IO_INTERFACE
    ATTRIBUTE IOTYPE = WARP_RADIOCONTROLLER_V1
    ATTRIBUTE INSTANCE = radio_controller_0
    ATTRIBUTE ALERT = 'This peripheral and at least one radio_bridge must be enabled to use the WARP radio interfaces.'

    #Common SPI clock and data outputs
    PORT controller_logic_clk = controller_logic_clk
    PORT spi_clk = controller_spi_clk
    PORT data_out = controller_spi_data

    #SPI radio chip selects
    PORT radio1_cs = controller_radio1_cs
    PORT radio2_cs = controller_radio2_cs
    PORT radio3_cs = controller_radio3_cs
    PORT radio4_cs = controller_radio4_cs

    #SPI DAC chip selects
    PORT dac1_cs = controller_dac1_cs
    PORT dac2_cs = controller_dac2_cs
    PORT dac3_cs = controller_dac3_cs
    PORT dac4_cs = controller_dac4_cs

    #######################
    # Slot #1 Radio Ports #
    #######################
    PORT radio1_SHDN = controller_radio1_SHDN
    PORT radio1_TxEn = controller_radio1_TxEn
    PORT radio1_RxEn = controller_radio1_RxEn
    PORT radio1_RxHP = controller_radio1_RxHP
    PORT radio1_LD = controller_radio1_LD
    PORT radio1_24PA = controller_radio1_24PA
    PORT radio1_5PA = controller_radio1_5PA
    PORT radio1_ANTSW0 = controller_radio1_ANTSW0, IO_IS = radio1_antsw[0]
    PORT radio1_ANTSW1 = controller_radio1_ANTSW1, IO_IS = radio1_antsw[1]
    PORT radio1_LED0 = controller_radio1_LED0, IO_IS = radio1_LED[0]
    PORT radio1_LED1 = controller_radio1_LED1, IO_IS = radio1_LED[1]
    PORT radio1_LED2 = controller_radio1_LED2, IO_IS = radio1_LED[2]
    PORT radio1_ADC_RX_DCS = controller_radio1_RX_ADC_DCS
    PORT radio1_ADC_RX_DFS = controller_radio1_RX_ADC_DFS
    PORT radio1_ADC_RX_OTRA = controller_radio1_RX_ADC_OTRA
    PORT radio1_ADC_RX_OTRB = controller_radio1_RX_ADC_OTRB
    PORT radio1_ADC_RX_PWDNA = controller_radio1_RX_ADC_PWDNA
    PORT radio1_ADC_RX_PWDNB = controller_radio1_RX_ADC_PWDNB
    PORT radio1_DIPSW0 = controller_radio1_DIPSW0, IO_IS = radio1_DIPSW[0]
    PORT radio1_DIPSW1 = controller_radio1_DIPSW1, IO_IS = radio1_DIPSW[1]
    PORT radio1_DIPSW2 = controller_radio1_DIPSW2, IO_IS = radio1_DIPSW[2]
    PORT radio1_DIPSW3 = controller_radio1_DIPSW3, IO_IS = radio1_DIPSW[3]
    PORT radio1_RSSI_ADC_CLAMP = controller_radio1_RSSI_ADC_CLAMP
    PORT radio1_RSSI_ADC_HIZ = controller_radio1_RSSI_ADC_HIZ
    PORT radio1_RSSI_ADC_OTR = controller_radio1_RSSI_ADC_OTR
    PORT radio1_RSSI_ADC_SLEEP = controller_radio1_RSSI_ADC_SLEEP
    PORT radio1_RSSI_ADC_D0 = controller_radio1_RSSI_ADC_D0, IO_IS = radio1_RSSI_ADC_D[0]
    PORT radio1_RSSI_ADC_D1 = controller_radio1_RSSI_ADC_D1, IO_IS = radio1_RSSI_ADC_D[1]
    PORT radio1_RSSI_ADC_D2 = controller_radio1_RSSI_ADC_D2, IO_IS = radio1_RSSI_ADC_D[2]
    PORT radio1_RSSI_ADC_D3 = controller_radio1_RSSI_ADC_D3, IO_IS = radio1_RSSI_ADC_D[3]
    PORT radio1_RSSI_ADC_D4 = controller_radio1_RSSI_ADC_D4, IO_IS = radio1_RSSI_ADC_D[4]
    PORT radio1_RSSI_ADC_D5 = controller_radio1_RSSI_ADC_D5, IO_IS = radio1_RSSI_ADC_D[5]
    PORT radio1_RSSI_ADC_D6 = controller_radio1_RSSI_ADC_D6, IO_IS = radio1_RSSI_ADC_D[6]
    PORT radio1_RSSI_ADC_D7 = controller_radio1_RSSI_ADC_D7, IO_IS = radio1_RSSI_ADC_D[7]
    PORT radio1_RSSI_ADC_D8 = controller_radio1_RSSI_ADC_D8, IO_IS = radio1_RSSI_ADC_D[8]
    PORT radio1_RSSI_ADC_D9 = controller_radio1_RSSI_ADC_D9, IO_IS = radio1_RSSI_ADC_D[9]
    PORT radio1_TX_DAC_PLL_LOCK = controller_DAC1_PLL_LOCK
    PORT radio1_TX_DAC_RESET = controller_DAC1_RESET
    PORT radio1_SHDN_external = controller_radio1_SHDN_external
    PORT radio1_TxEn_external = controller_radio1_TxEn_external
    PORT radio1_RxEn_external = controller_radio1_RxEn_external
    PORT radio1_RxHP_external = controller_radio1_RxHP_external
    PORT radio1_TxGain0 = controller_radio1_TxGain0, IO_IS = radio1_TxGain[0]
    PORT radio1_TxGain1 = controller_radio1_TxGain1, IO_IS = radio1_TxGain[1]
    PORT radio1_TxGain2 = controller_radio1_TxGain2, IO_IS = radio1_TxGain[2]
    PORT radio1_TxGain3 = controller_radio1_TxGain3, IO_IS = radio1_TxGain[3]
    PORT radio1_TxGain4 = controller_radio1_TxGain4, IO_IS = radio1_TxGain[4]
    PORT radio1_TxGain5 = controller_radio1_TxGain5, IO_IS = radio1_TxGain[5]
    PORT radio1_TxStart = controller_radio1_TxStart

    #######################
    # Slot #2 Radio Ports #
    #######################
    PORT radio2_SHDN = controller_radio2_SHDN
    PORT radio2_TxEn = controller_radio2_TxEn
    PORT radio2_RxEn = controller_radio2_RxEn
    PORT radio2_RxHP = controller_radio2_RxHP
    PORT radio2_LD = controller_radio2_LD
    PORT radio2_24PA = controller_radio2_24PA
    PORT radio2_5PA = controller_radio2_5PA
    PORT radio2_ANTSW0 = controller_radio2_ANTSW0, IO_IS = radio2_antsw[0]
    PORT radio2_ANTSW1 = controller_radio2_ANTSW1, IO_IS = radio2_antsw[1]
    PORT radio2_LED0 = controller_radio2_LED0, IO_IS = radio2_LED[0]
    PORT radio2_LED1 = controller_radio2_LED1, IO_IS = radio2_LED[1]
    PORT radio2_LED2 = controller_radio2_LED2, IO_IS = radio2_LED[2]
    PORT radio2_ADC_RX_DCS = controller_radio2_RX_ADC_DCS
    PORT radio2_ADC_RX_DFS = controller_radio2_RX_ADC_DFS
    PORT radio2_ADC_RX_OTRA = controller_radio2_RX_ADC_OTRA
    PORT radio2_ADC_RX_OTRB = controller_radio2_RX_ADC_OTRB
    PORT radio2_ADC_RX_PWDNA = controller_radio2_RX_ADC_PWDNA
    PORT radio2_ADC_RX_PWDNB = controller_radio2_RX_ADC_PWDNB
    PORT radio2_DIPSW0 = controller_radio2_DIPSW0, IO_IS = radio2_DIPSW[0]
    PORT radio2_DIPSW1 = controller_radio2_DIPSW1, IO_IS = radio2_DIPSW[1]
    PORT radio2_DIPSW2 = controller_radio2_DIPSW2, IO_IS = radio2_DIPSW[2]
    PORT radio2_DIPSW3 = controller_radio2_DIPSW3, IO_IS = radio2_DIPSW[3]
    PORT radio2_RSSI_ADC_CLAMP = controller_radio2_RSSI_ADC_CLAMP
    PORT radio2_RSSI_ADC_HIZ = controller_radio2_RSSI_ADC_HIZ
    PORT radio2_RSSI_ADC_OTR = controller_radio2_RSSI_ADC_OTR
    PORT radio2_RSSI_ADC_SLEEP = controller_radio2_RSSI_ADC_SLEEP
    PORT radio2_RSSI_ADC_D0 = controller_radio2_RSSI_ADC_D0, IO_IS = radio2_RSSI_ADC_D[0]
    PORT radio2_RSSI_ADC_D1 = controller_radio2_RSSI_ADC_D1, IO_IS = radio2_RSSI_ADC_D[1]
    PORT radio2_RSSI_ADC_D2 = controller_radio2_RSSI_ADC_D2, IO_IS = radio2_RSSI_ADC_D[2]
    PORT radio2_RSSI_ADC_D3 = controller_radio2_RSSI_ADC_D3, IO_IS = radio2_RSSI_ADC_D[3]
    PORT radio2_RSSI_ADC_D4 = controller_radio2_RSSI_ADC_D4, IO_IS = radio2_RSSI_ADC_D[4]
    PORT radio2_RSSI_ADC_D5 = controller_radio2_RSSI_ADC_D5, IO_IS = radio2_RSSI_ADC_D[5]
    PORT radio2_RSSI_ADC_D6 = controller_radio2_RSSI_ADC_D6, IO_IS = radio2_RSSI_ADC_D[6]
    PORT radio2_RSSI_ADC_D7 = controller_radio2_RSSI_ADC_D7, IO_IS = radio2_RSSI_ADC_D[7]
    PORT radio2_RSSI_ADC_D8 = controller_radio2_RSSI_ADC_D8, IO_IS = radio2_RSSI_ADC_D[8]
    PORT radio2_RSSI_ADC_D9 = controller_radio2_RSSI_ADC_D9, IO_IS = radio2_RSSI_ADC_D[9]
    PORT radio2_TX_DAC_PLL_LOCK = controller_DAC2_PLL_LOCK
    PORT radio2_TX_DAC_RESET = controller_DAC2_RESET
    PORT radio2_SHDN_external = controller_radio2_SHDN_external
    PORT radio2_TxEn_external = controller_radio2_TxEn_external
    PORT radio2_RxEn_external = controller_radio2_RxEn_external
    PORT radio2_RxHP_external = controller_radio2_RxHP_external
    PORT radio2_TxGain0 = controller_radio2_TxGain0, IO_IS = radio2_TxGain[0]
    PORT radio2_TxGain1 = controller_radio2_TxGain1, IO_IS = radio2_TxGain[1]
    PORT radio2_TxGain2 = controller_radio2_TxGain2, IO_IS = radio2_TxGain[2]
    PORT radio2_TxGain3 = controller_radio2_TxGain3, IO_IS = radio2_TxGain[3]
    PORT radio2_TxGain4 = controller_radio2_TxGain4, IO_IS = radio2_TxGain[4]
    PORT radio2_TxGain5 = controller_radio2_TxGain5, IO_IS = radio2_TxGain[5]
    PORT radio2_TxStart = controller_radio2_TxStart

    #######################
    # Slot #3 Radio Ports #
    #######################
    PORT radio3_SHDN = controller_radio3_SHDN
    PORT radio3_TxEn = controller_radio3_TxEn
    PORT radio3_RxEn = controller_radio3_RxEn
    PORT radio3_RxHP = controller_radio3_RxHP
    PORT radio3_LD = controller_radio3_LD
    PORT radio3_24PA = controller_radio3_24PA
    PORT radio3_5PA = controller_radio3_5PA
    PORT radio3_ANTSW0 = controller_radio3_ANTSW0, IO_IS = radio3_antsw[0]
    PORT radio3_ANTSW1 = controller_radio3_ANTSW1, IO_IS = radio3_antsw[1]
    PORT radio3_LED0 = controller_radio3_LED0, IO_IS = radio3_LED[0]
    PORT radio3_LED1 = controller_radio3_LED1, IO_IS = radio3_LED[1]
    PORT radio3_LED2 = controller_radio3_LED2, IO_IS = radio3_LED[2]
    PORT radio3_ADC_RX_DCS = controller_radio3_RX_ADC_DCS
    PORT radio3_ADC_RX_DFS = controller_radio3_RX_ADC_DFS
    PORT radio3_ADC_RX_OTRA = controller_radio3_RX_ADC_OTRA
    PORT radio3_ADC_RX_OTRB = controller_radio3_RX_ADC_OTRB
    PORT radio3_ADC_RX_PWDNA = controller_radio3_RX_ADC_PWDNA
    PORT radio3_ADC_RX_PWDNB = controller_radio3_RX_ADC_PWDNB
    PORT radio3_DIPSW0 = controller_radio3_DIPSW0, IO_IS = radio3_DIPSW[0]
    PORT radio3_DIPSW1 = controller_radio3_DIPSW1, IO_IS = radio3_DIPSW[1]
    PORT radio3_DIPSW2 = controller_radio3_DIPSW2, IO_IS = radio3_DIPSW[2]
    PORT radio3_DIPSW3 = controller_radio3_DIPSW3, IO_IS = radio3_DIPSW[3]
    PORT radio3_RSSI_ADC_CLAMP = controller_radio3_RSSI_ADC_CLAMP
    PORT radio3_RSSI_ADC_HIZ = controller_radio3_RSSI_ADC_HIZ
    PORT radio3_RSSI_ADC_OTR = controller_radio3_RSSI_ADC_OTR
    PORT radio3_RSSI_ADC_SLEEP = controller_radio3_RSSI_ADC_SLEEP
    PORT radio3_RSSI_ADC_D0 = controller_radio3_RSSI_ADC_D0, IO_IS = radio3_RSSI_ADC_D[0]
    PORT radio3_RSSI_ADC_D1 = controller_radio3_RSSI_ADC_D1, IO_IS = radio3_RSSI_ADC_D[1]
    PORT radio3_RSSI_ADC_D2 = controller_radio3_RSSI_ADC_D2, IO_IS = radio3_RSSI_ADC_D[2]
    PORT radio3_RSSI_ADC_D3 = controller_radio3_RSSI_ADC_D3, IO_IS = radio3_RSSI_ADC_D[3]
    PORT radio3_RSSI_ADC_D4 = controller_radio3_RSSI_ADC_D4, IO_IS = radio3_RSSI_ADC_D[4]
    PORT radio3_RSSI_ADC_D5 = controller_radio3_RSSI_ADC_D5, IO_IS = radio3_RSSI_ADC_D[5]
    PORT radio3_RSSI_ADC_D6 = controller_radio3_RSSI_ADC_D6, IO_IS = radio3_RSSI_ADC_D[6]
    PORT radio3_RSSI_ADC_D7 = controller_radio3_RSSI_ADC_D7, IO_IS = radio3_RSSI_ADC_D[7]
    PORT radio3_RSSI_ADC_D8 = controller_radio3_RSSI_ADC_D8, IO_IS = radio3_RSSI_ADC_D[8]
    PORT radio3_RSSI_ADC_D9 = controller_radio3_RSSI_ADC_D9, IO_IS = radio3_RSSI_ADC_D[9]
    PORT radio3_TX_DAC_PLL_LOCK = controller_DAC3_PLL_LOCK
    PORT radio3_TX_DAC_RESET = controller_DAC3_RESET
    PORT radio3_SHDN_external = controller_radio3_SHDN_external
    PORT radio3_TxEn_external = controller_radio3_TxEn_external
    PORT radio3_RxEn_external = controller_radio3_RxEn_external
    PORT radio3_RxHP_external = controller_radio3_RxHP_external
    PORT radio3_TxGain0 = controller_radio3_TxGain0, IO_IS = radio3_TxGain[0]
    PORT radio3_TxGain1 = controller_radio3_TxGain1, IO_IS = radio3_TxGain[1]
    PORT radio3_TxGain2 = controller_radio3_TxGain2, IO_IS = radio3_TxGain[2]
    PORT radio3_TxGain3 = controller_radio3_TxGain3, IO_IS = radio3_TxGain[3]
    PORT radio3_TxGain4 = controller_radio3_TxGain4, IO_IS = radio3_TxGain[4]
    PORT radio3_TxGain5 = controller_radio3_TxGain5, IO_IS = radio3_TxGain[5]
    PORT radio3_TxStart = controller_radio3_TxStart

    #######################
    # Slot #4 Radio Ports #
    #######################
    PORT radio4_SHDN = controller_radio4_SHDN
    PORT radio4_TxEn = controller_radio4_TxEn
    PORT radio4_RxEn = controller_radio4_RxEn
    PORT radio4_RxHP = controller_radio4_RxHP
    PORT radio4_LD = controller_radio4_LD
    PORT radio4_24PA = controller_radio4_24PA
    PORT radio4_5PA = controller_radio4_5PA
    PORT radio4_ANTSW0 = controller_radio4_ANTSW0, IO_IS = radio4_antsw[0]
    PORT radio4_ANTSW1 = controller_radio4_ANTSW1, IO_IS = radio4_antsw[1]
    PORT radio4_LED0 = controller_radio4_LED0, IO_IS = radio4_LED[0]
    PORT radio4_LED1 = controller_radio4_LED1, IO_IS = radio4_LED[1]
    PORT radio4_LED2 = controller_radio4_LED2, IO_IS = radio4_LED[2]
    PORT radio4_ADC_RX_DCS = controller_radio4_RX_ADC_DCS
    PORT radio4_ADC_RX_DFS = controller_radio4_RX_ADC_DFS
    PORT radio4_ADC_RX_OTRA = controller_radio4_RX_ADC_OTRA
    PORT radio4_ADC_RX_OTRB = controller_radio4_RX_ADC_OTRB
    PORT radio4_ADC_RX_PWDNA = controller_radio4_RX_ADC_PWDNA
    PORT radio4_ADC_RX_PWDNB = controller_radio4_RX_ADC_PWDNB
    PORT radio4_DIPSW0 = controller_radio4_DIPSW0, IO_IS = radio4_DIPSW[0]
    PORT radio4_DIPSW1 = controller_radio4_DIPSW1, IO_IS = radio4_DIPSW[1]
    PORT radio4_DIPSW2 = controller_radio4_DIPSW2, IO_IS = radio4_DIPSW[2]
    PORT radio4_DIPSW3 = controller_radio4_DIPSW3, IO_IS = radio4_DIPSW[3]
    PORT radio4_RSSI_ADC_CLAMP = controller_radio4_RSSI_ADC_CLAMP
    PORT radio4_RSSI_ADC_HIZ = controller_radio4_RSSI_ADC_HIZ
    PORT radio4_RSSI_ADC_OTR = controller_radio4_RSSI_ADC_OTR
    PORT radio4_RSSI_ADC_SLEEP = controller_radio4_RSSI_ADC_SLEEP
    PORT radio4_RSSI_ADC_D0 = controller_radio4_RSSI_ADC_D0, IO_IS = radio4_RSSI_ADC_D[0]
    PORT radio4_RSSI_ADC_D1 = controller_radio4_RSSI_ADC_D1, IO_IS = radio4_RSSI_ADC_D[1]
    PORT radio4_RSSI_ADC_D2 = controller_radio4_RSSI_ADC_D2, IO_IS = radio4_RSSI_ADC_D[2]
    PORT radio4_RSSI_ADC_D3 = controller_radio4_RSSI_ADC_D3, IO_IS = radio4_RSSI_ADC_D[3]
    PORT radio4_RSSI_ADC_D4 = controller_radio4_RSSI_ADC_D4, IO_IS = radio4_RSSI_ADC_D[4]
    PORT radio4_RSSI_ADC_D5 = controller_radio4_RSSI_ADC_D5, IO_IS = radio4_RSSI_ADC_D[5]
    PORT radio4_RSSI_ADC_D6 = controller_radio4_RSSI_ADC_D6, IO_IS = radio4_RSSI_ADC_D[6]
    PORT radio4_RSSI_ADC_D7 = controller_radio4_RSSI_ADC_D7, IO_IS = radio4_RSSI_ADC_D[7]
    PORT radio4_RSSI_ADC_D8 = controller_radio4_RSSI_ADC_D8, IO_IS = radio4_RSSI_ADC_D[8]
    PORT radio4_RSSI_ADC_D9 = controller_radio4_RSSI_ADC_D9, IO_IS = radio4_RSSI_ADC_D[9]
    PORT radio4_TX_DAC_PLL_LOCK = controller_DAC4_PLL_LOCK
    PORT radio4_TX_DAC_RESET = controller_DAC4_RESET
    PORT radio4_SHDN_external = controller_radio4_SHDN_external
    PORT radio4_TxEn_external = controller_radio4_TxEn_external
    PORT radio4_RxEn_external = controller_radio4_RxEn_external
    PORT radio4_RxHP_external = controller_radio4_RxHP_external
    PORT radio4_TxGain0 = controller_radio4_TxGain0, IO_IS = radio4_TxGain[0]
    PORT radio4_TxGain1 = controller_radio4_TxGain1, IO_IS = radio4_TxGain[1]
    PORT radio4_TxGain2 = controller_radio4_TxGain2, IO_IS = radio4_TxGain[2]
    PORT radio4_TxGain3 = controller_radio4_TxGain3, IO_IS = radio4_TxGain[3]
    PORT radio4_TxGain4 = controller_radio4_TxGain4, IO_IS = radio4_TxGain[4]
    PORT radio4_TxGain5 = controller_radio4_TxGain5, IO_IS = radio4_TxGain[5]
    PORT radio4_TxStart = controller_radio4_TxStart
END

#Radio Controller -> Radio Board Bridge for Slot #1
BEGIN IO_INTERFACE
    ATTRIBUTE IOTYPE = WARP_RADIOBRIDGE_V1
    ATTRIBUTE INSTANCE = radio_bridge_slot_1
    ATTRIBUTE EXCLUSIVE = slot1
    ATTRIBUTE ALERT = 'Enable this peripheral only if a radio board is mounted in daughtercard slot 1.'

    PORT    converter_clock_out = radio1_conv_clk_p

    PORT    radio_b0 = radio1_b0, IO_IS = radioGain[0]
    PORT    radio_b1 = radio1_b1, IO_IS = radioGain[1]
    PORT    radio_b2 = radio1_b2, IO_IS = radioGain[2]
    PORT    radio_b3 = radio1_b3, IO_IS = radioGain[3]
    PORT    radio_b4 = radio1_b4, IO_IS = radioGain[4]
    PORT    radio_b5 = radio1_b5, IO_IS = radioGain[5]
    PORT    radio_b6 = radio1_b6, IO_IS = radioGain[6]

    PORT    radio_ADC_I0 = radio1_ADC_I0, IO_IS = radioADCI[0]
    PORT    radio_ADC_I1 = radio1_ADC_I1, IO_IS = radioADCI[1]
    PORT    radio_ADC_I2 = radio1_ADC_I2, IO_IS = radioADCI[2]
    PORT    radio_ADC_I3 = radio1_ADC_I3, IO_IS = radioADCI[3]
    PORT    radio_ADC_I4 = radio1_ADC_I4, IO_IS = radioADCI[4]
    PORT    radio_ADC_I5 = radio1_ADC_I5, IO_IS = radioADCI[5]
    PORT    radio_ADC_I6 = radio1_ADC_I6, IO_IS = radioADCI[6]
    PORT    radio_ADC_I7 = radio1_ADC_I7, IO_IS = radioADCI[7]
    PORT    radio_ADC_I8 = radio1_ADC_I8, IO_IS = radioADCI[8]
    PORT    radio_ADC_I9 = radio1_ADC_I9, IO_IS = radioADCI[9]
    PORT    radio_ADC_I10 = radio1_ADC_I10, IO_IS = radioADCI[10]
    PORT    radio_ADC_I11 = radio1_ADC_I11, IO_IS = radioADCI[11]
    PORT    radio_ADC_I12 = radio1_ADC_I12, IO_IS = radioADCI[12]
    PORT    radio_ADC_I13 = radio1_ADC_I13, IO_IS = radioADCI[13]

    PORT    radio_ADC_Q0 = radio1_ADC_Q0, IO_IS = radioADCQ[0]
    PORT    radio_ADC_Q1 = radio1_ADC_Q1, IO_IS = radioADCQ[1]
    PORT    radio_ADC_Q2 = radio1_ADC_Q2, IO_IS = radioADCQ[2]
    PORT    radio_ADC_Q3 = radio1_ADC_Q3, IO_IS = radioADCQ[3]
    PORT    radio_ADC_Q4 = radio1_ADC_Q4, IO_IS = radioADCQ[4]
    PORT    radio_ADC_Q5 = radio1_ADC_Q5, IO_IS = radioADCQ[5]
    PORT    radio_ADC_Q6 = radio1_ADC_Q6, IO_IS = radioADCQ[6]
    PORT    radio_ADC_Q7 = radio1_ADC_Q7, IO_IS = radioADCQ[7]
    PORT    radio_ADC_Q8 = radio1_ADC_Q8, IO_IS = radioADCQ[8]
    PORT    radio_ADC_Q9 = radio1_ADC_Q9, IO_IS = radioADCQ[9]
    PORT    radio_ADC_Q10 = radio1_ADC_Q10, IO_IS = radioADCQ[10]
    PORT    radio_ADC_Q11 = radio1_ADC_Q11, IO_IS = radioADCQ[11]
    PORT    radio_ADC_Q12 = radio1_ADC_Q12, IO_IS = radioADCQ[12]
    PORT    radio_ADC_Q13 = radio1_ADC_Q13, IO_IS = radioADCQ[13]

    PORT    radio_DAC_I0 = radio1_DAC_I0, IO_IS = radioDACI[0]
    PORT    radio_DAC_I1 = radio1_DAC_I1, IO_IS = radioDACI[1]
    PORT    radio_DAC_I2 = radio1_DAC_I2, IO_IS = radioDACI[2]
    PORT    radio_DAC_I3 = radio1_DAC_I3, IO_IS = radioDACI[3]
    PORT    radio_DAC_I4 = radio1_DAC_I4, IO_IS = radioDACI[4]
    PORT    radio_DAC_I5 = radio1_DAC_I5, IO_IS = radioDACI[5]
    PORT    radio_DAC_I6 = radio1_DAC_I6, IO_IS = radioDACI[6]
    PORT    radio_DAC_I7 = radio1_DAC_I7, IO_IS = radioDACI[7]
    PORT    radio_DAC_I8 = radio1_DAC_I8, IO_IS = radioDACI[8]
    PORT    radio_DAC_I9 = radio1_DAC_I9, IO_IS = radioDACI[9]
    PORT    radio_DAC_I10 = radio1_DAC_I10, IO_IS = radioDACI[10]
    PORT    radio_DAC_I11 = radio1_DAC_I11, IO_IS = radioDACI[11]
    PORT    radio_DAC_I12 = radio1_DAC_I12, IO_IS = radioDACI[12]
    PORT    radio_DAC_I13 = radio1_DAC_I13, IO_IS = radioDACI[13]
    PORT    radio_DAC_I14 = radio1_DAC_I14, IO_IS = radioDACI[14]
    PORT    radio_DAC_I15 = radio1_DAC_I15, IO_IS = radioDACI[15]

    PORT    radio_DAC_Q0 = radio1_DAC_Q0, IO_IS = radioDACQ[0]
    PORT    radio_DAC_Q1 = radio1_DAC_Q1, IO_IS = radioDACQ[1]
    PORT    radio_DAC_Q2 = radio1_DAC_Q2, IO_IS = radioDACQ[2]
    PORT    radio_DAC_Q3 = radio1_DAC_Q3, IO_IS = radioDACQ[3]
    PORT    radio_DAC_Q4 = radio1_DAC_Q4, IO_IS = radioDACQ[4]
    PORT    radio_DAC_Q5 = radio1_DAC_Q5, IO_IS = radioDACQ[5]
    PORT    radio_DAC_Q6 = radio1_DAC_Q6, IO_IS = radioDACQ[6]
    PORT    radio_DAC_Q7 = radio1_DAC_Q7, IO_IS = radioDACQ[7]
    PORT    radio_DAC_Q8 = radio1_DAC_Q8, IO_IS = radioDACQ[8]
    PORT    radio_DAC_Q9 = radio1_DAC_Q9, IO_IS = radioDACQ[9]
    PORT    radio_DAC_Q10 = radio1_DAC_Q10, IO_IS = radioDACQ[10]
    PORT    radio_DAC_Q11 = radio1_DAC_Q11, IO_IS = radioDACQ[11]
    PORT    radio_DAC_Q12 = radio1_DAC_Q12, IO_IS = radioDACQ[12]
    PORT    radio_DAC_Q13 = radio1_DAC_Q13, IO_IS = radioDACQ[13]
    PORT    radio_DAC_Q14 = radio1_DAC_Q14, IO_IS = radioDACQ[14]
    PORT    radio_DAC_Q15 = radio1_DAC_Q15, IO_IS = radioDACQ[15]

    ##########################################
    #Radio Controller <-> Radio Bridge Ports #
    ##########################################
    PORT    controller_logic_clk = controller_logic_clk
    PORT    controller_interpfiltbypass = controller_radio1_interpfiltbypass
    PORT    controller_decfiltbypass = controller_radio1_decfiltbypass
    PORT    controller_spi_clk = controller_spi_clk 
    PORT    controller_spi_data = controller_spi_data 
    PORT    controller_radio_cs = controller_radio1_cs 
    PORT    controller_dac_cs = controller_dac1_cs 
    PORT    controller_SHDN = controller_radio1_SHDN 
    PORT    controller_TxEn = controller_radio1_TxEn 
    PORT    controller_RxEn = controller_radio1_RxEn 
    PORT    controller_RxHP = controller_radio1_RxHP 
    PORT    controller_24PA = controller_radio1_24PA 
    PORT    controller_5PA = controller_radio1_5PA 
    PORT    controller_ANTSW0 = controller_radio1_ANTSW0, IO_IS = c2b_ANTSW[0]
    PORT    controller_ANTSW1 = controller_radio1_ANTSW1, IO_IS = c2b_ANTSW[1] 
    PORT    controller_LED0 = controller_radio1_LED0, IO_IS = c2b_LED[0]
    PORT    controller_LED1 = controller_radio1_LED1, IO_IS = c2b_LED[1]
    PORT    controller_LED2 = controller_radio1_LED2, IO_IS = c2b_LED[2]
    PORT    controller_RX_ADC_DCS = controller_radio1_RX_ADC_DCS
    PORT    controller_RX_ADC_DFS = controller_radio1_RX_ADC_DFS
    PORT    controller_RX_ADC_PWDNA = controller_radio1_RX_ADC_PWDNA
    PORT    controller_RX_ADC_PWDNB = controller_radio1_RX_ADC_PWDNB
    PORT    controller_DIPSW0 = controller_radio1_DIPSW0, IO_IS = c2b_DIPSW[0]
    PORT    controller_DIPSW1 = controller_radio1_DIPSW1, IO_IS = c2b_DIPSW[1]
    PORT    controller_DIPSW2 = controller_radio1_DIPSW2, IO_IS = c2b_DIPSW[2]
    PORT    controller_DIPSW3 = controller_radio1_DIPSW3, IO_IS = c2b_DIPSW[3]
    PORT    controller_RSSI_ADC_CLAMP = controller_radio1_RSSI_ADC_CLAMP
    PORT    controller_RSSI_ADC_HIZ = controller_radio1_RSSI_ADC_HIZ
    PORT    controller_RSSI_ADC_SLEEP = controller_radio1_RSSI_ADC_SLEEP
    PORT    controller_RSSI_ADC_D0 = controller_radio1_RSSI_ADC_D0, IO_IS = c2b_RSSI_ADC_D[0]
    PORT    controller_RSSI_ADC_D1 = controller_radio1_RSSI_ADC_D1, IO_IS = c2b_RSSI_ADC_D[1]
    PORT    controller_RSSI_ADC_D2 = controller_radio1_RSSI_ADC_D2, IO_IS = c2b_RSSI_ADC_D[2]
    PORT    controller_RSSI_ADC_D3 = controller_radio1_RSSI_ADC_D3, IO_IS = c2b_RSSI_ADC_D[3]
    PORT    controller_RSSI_ADC_D4 = controller_radio1_RSSI_ADC_D4, IO_IS = c2b_RSSI_ADC_D[4]
    PORT    controller_RSSI_ADC_D5 = controller_radio1_RSSI_ADC_D5, IO_IS = c2b_RSSI_ADC_D[5]
    PORT    controller_RSSI_ADC_D6 = controller_radio1_RSSI_ADC_D6, IO_IS = c2b_RSSI_ADC_D[6]
    PORT    controller_RSSI_ADC_D7 = controller_radio1_RSSI_ADC_D7, IO_IS = c2b_RSSI_ADC_D[7]
    PORT    controller_RSSI_ADC_D8 = controller_radio1_RSSI_ADC_D8, IO_IS = c2b_RSSI_ADC_D[8]
    PORT    controller_RSSI_ADC_D9 = controller_radio1_RSSI_ADC_D9, IO_IS = c2b_RSSI_ADC_D[9]
    PORT    controller_LD = controller_radio1_LD
    PORT    controller_RX_ADC_OTRA = controller_radio1_RX_ADC_OTRA
    PORT    controller_RX_ADC_OTRB = controller_radio1_RX_ADC_OTRB
    PORT    controller_RSSI_ADC_OTR = controller_radio1_RSSI_ADC_OTR
    PORT    controller_dac_PLL_LOCK = controller_dac1_PLL_LOCK
    PORT    controller_dac_RESET = controller_dac1_RESET
    PORT    user_Tx_gain0 = controller_radio1_TxGain0, IO_IS = userTxG[0]
    PORT    user_Tx_gain1 = controller_radio1_TxGain1, IO_IS = userTxG[1]
    PORT    user_Tx_gain2 = controller_radio1_TxGain2, IO_IS = userTxG[2]
    PORT    user_Tx_gain3 = controller_radio1_TxGain3, IO_IS = userTxG[3]
    PORT    user_Tx_gain4 = controller_radio1_TxGain4, IO_IS = userTxG[4]
    PORT    user_Tx_gain5 = controller_radio1_TxGain5, IO_IS = userTxG[5]
    PORT    controller_TxStart = controller_radio1_TxStart
    PORT    controller_SHDN_external = controller_radio1_SHDN_external
    PORT    controller_RxEn_external = controller_radio1_RxEn_external
    PORT    controller_TxEn_external = controller_radio1_TxEn_external
    PORT    controller_RxHP_external = controller_radio1_RxHP_external


    #####################################
    #Radio Bridge <-> Radio Board Ports #
    #####################################
    PORT    dac_spi_data = dac1_spi_data
    PORT    dac_spi_cs = dac1_spi_cs
    PORT    dac_spi_clk = dac1_spi_clk
    PORT    radio_spi_clk = radio1_spi_clk
    PORT    radio_spi_data = radio1_spi_data
    PORT    radio_spi_cs = radio1_spi_cs
    PORT    radio_SHDN = radio1_SHDN
    PORT    radio_TxEn = radio1_TxEn
    PORT    radio_RxEn = radio1_RxEn
    PORT    radio_RxHP = radio1_RxHP
    PORT    radio_24PA = radio1_24PA
    PORT    radio_5PA = radio1_5PA
    PORT    radio_ANTSW0 = radio1_ANTSW0, IO_IS = b2r_ANTSW[0]
    PORT    radio_ANTSW1 = radio1_ANTSW1, IO_IS = b2r_ANTSW[1]
    PORT    radio_LED0 = radio1_LED0, IO_IS = b2r_LED[0]
    PORT    radio_LED1 = radio1_LED1, IO_IS = b2r_LED[1]
    PORT    radio_LED2 = radio1_LED2, IO_IS = b2r_LED[2]
    PORT    radio_RX_ADC_DCS = radio1_RX_ADC_DCS
    PORT    radio_RX_ADC_DFS = radio1_RX_ADC_DFS
    PORT    radio_RX_ADC_PWDNA = radio1_RX_ADC_PWDNA
    PORT    radio_RX_ADC_PWDNB = radio1_RX_ADC_PWDNB
    PORT    radio_DIPSW0 = radio1_DIPSW0, IO_IS = b2r_DIPSW[0]
    PORT    radio_DIPSW1 = radio1_DIPSW1, IO_IS = b2r_DIPSW[1]
    PORT    radio_DIPSW2 = radio1_DIPSW2, IO_IS = b2r_DIPSW[2]
    PORT    radio_DIPSW3 = radio1_DIPSW3, IO_IS = b2r_DIPSW[3]
    PORT    radio_RSSI_ADC_clk = radio1_RSSI_ADC_clk
    PORT    radio_RSSI_ADC_CLAMP = radio1_RSSI_ADC_CLAMP
    PORT    radio_RSSI_ADC_HIZ = radio1_RSSI_ADC_HIZ
    PORT    radio_RSSI_ADC_SLEEP = radio1_RSSI_ADC_SLEEP
    PORT    radio_RSSI_ADC_D0 = radio1_RSSI_ADC_D0, IO_IS = b2r_RSSI_ADC_D[0]
    PORT    radio_RSSI_ADC_D1 = radio1_RSSI_ADC_D1, IO_IS = b2r_RSSI_ADC_D[1]
    PORT    radio_RSSI_ADC_D2 = radio1_RSSI_ADC_D2, IO_IS = b2r_RSSI_ADC_D[2]
    PORT    radio_RSSI_ADC_D3 = radio1_RSSI_ADC_D3, IO_IS = b2r_RSSI_ADC_D[3]
    PORT    radio_RSSI_ADC_D4 = radio1_RSSI_ADC_D4, IO_IS = b2r_RSSI_ADC_D[4]
    PORT    radio_RSSI_ADC_D5 = radio1_RSSI_ADC_D5, IO_IS = b2r_RSSI_ADC_D[5]
    PORT    radio_RSSI_ADC_D6 = radio1_RSSI_ADC_D6, IO_IS = b2r_RSSI_ADC_D[6]
    PORT    radio_RSSI_ADC_D7 = radio1_RSSI_ADC_D7, IO_IS = b2r_RSSI_ADC_D[7]
    PORT    radio_RSSI_ADC_D8 = radio1_RSSI_ADC_D8, IO_IS = b2r_RSSI_ADC_D[8]
    PORT    radio_RSSI_ADC_D9 = radio1_RSSI_ADC_D9, IO_IS = b2r_RSSI_ADC_D[9]
    PORT    radio_LD = radio1_LD
    PORT    radio_RX_ADC_OTRA = radio1_RX_ADC_OTRA
    PORT    radio_RX_ADC_OTRB = radio1_RX_ADC_OTRB
    PORT    radio_RSSI_ADC_OTR = radio1_RSSI_ADC_OTR
    PORT    radio_dac_PLL_LOCK = radio1_dac1_PLL_LOCK
    PORT    radio_dac_RESET = radio1_dac1_RESET

    PORT    user_EEPROM_IO_T = DQ1_T_user_EEPROM_IO_T
    PORT    user_EEPROM_IO_O = DQ1_O_user_EEPROM_IO_O
    PORT    user_EEPROM_IO_I = DQ1_I_user_EEPROM_IO_I
    PORT    radio_EEPROM_IO = radio1_EEPROM_IO
END

#Radio Controller -> Radio Board Bridge for Slot #2
BEGIN IO_INTERFACE
    ATTRIBUTE IOTYPE = WARP_RADIOBRIDGE_V1
    ATTRIBUTE INSTANCE = radio_bridge_slot_2
    ATTRIBUTE EXCLUSIVE = slot2
    ATTRIBUTE ALERT = 'Enable this peripheral only if a radio board is mounted in daughtercard slot 2.'

    PORT    converter_clock_out = radio2_conv_clk_p

    PORT    radio_b0 = radio2_b0, IO_IS = radioGain[0]
    PORT    radio_b1 = radio2_b1, IO_IS = radioGain[1]
    PORT    radio_b2 = radio2_b2, IO_IS = radioGain[2]
    PORT    radio_b3 = radio2_b3, IO_IS = radioGain[3]
    PORT    radio_b4 = radio2_b4, IO_IS = radioGain[4]
    PORT    radio_b5 = radio2_b5, IO_IS = radioGain[5]
    PORT    radio_b6 = radio2_b6, IO_IS = radioGain[6]

    PORT    radio_ADC_I0 = radio2_ADC_I0, IO_IS = radioADCI[0]
    PORT    radio_ADC_I1 = radio2_ADC_I1, IO_IS = radioADCI[1]
    PORT    radio_ADC_I2 = radio2_ADC_I2, IO_IS = radioADCI[2]
    PORT    radio_ADC_I3 = radio2_ADC_I3, IO_IS = radioADCI[3]
    PORT    radio_ADC_I4 = radio2_ADC_I4, IO_IS = radioADCI[4]
    PORT    radio_ADC_I5 = radio2_ADC_I5, IO_IS = radioADCI[5]
    PORT    radio_ADC_I6 = radio2_ADC_I6, IO_IS = radioADCI[6]
    PORT    radio_ADC_I7 = radio2_ADC_I7, IO_IS = radioADCI[7]
    PORT    radio_ADC_I8 = radio2_ADC_I8, IO_IS = radioADCI[8]
    PORT    radio_ADC_I9 = radio2_ADC_I9, IO_IS = radioADCI[9]
    PORT    radio_ADC_I10 = radio2_ADC_I10, IO_IS = radioADCI[10]
    PORT    radio_ADC_I11 = radio2_ADC_I11, IO_IS = radioADCI[11]
    PORT    radio_ADC_I12 = radio2_ADC_I12, IO_IS = radioADCI[12]
    PORT    radio_ADC_I13 = radio2_ADC_I13, IO_IS = radioADCI[13]

    PORT    radio_ADC_Q0 = radio2_ADC_Q0, IO_IS = radioADCQ[0]
    PORT    radio_ADC_Q1 = radio2_ADC_Q1, IO_IS = radioADCQ[1]
    PORT    radio_ADC_Q2 = radio2_ADC_Q2, IO_IS = radioADCQ[2]
    PORT    radio_ADC_Q3 = radio2_ADC_Q3, IO_IS = radioADCQ[3]
    PORT    radio_ADC_Q4 = radio2_ADC_Q4, IO_IS = radioADCQ[4]
    PORT    radio_ADC_Q5 = radio2_ADC_Q5, IO_IS = radioADCQ[5]
    PORT    radio_ADC_Q6 = radio2_ADC_Q6, IO_IS = radioADCQ[6]
    PORT    radio_ADC_Q7 = radio2_ADC_Q7, IO_IS = radioADCQ[7]
    PORT    radio_ADC_Q8 = radio2_ADC_Q8, IO_IS = radioADCQ[8]
    PORT    radio_ADC_Q9 = radio2_ADC_Q9, IO_IS = radioADCQ[9]
    PORT    radio_ADC_Q10 = radio2_ADC_Q10, IO_IS = radioADCQ[10]
    PORT    radio_ADC_Q11 = radio2_ADC_Q11, IO_IS = radioADCQ[11]
    PORT    radio_ADC_Q12 = radio2_ADC_Q12, IO_IS = radioADCQ[12]
    PORT    radio_ADC_Q13 = radio2_ADC_Q13, IO_IS = radioADCQ[13]

    PORT    radio_DAC_I0 = radio2_DAC_I0, IO_IS = radioDACI[0]
    PORT    radio_DAC_I1 = radio2_DAC_I1, IO_IS = radioDACI[1]
    PORT    radio_DAC_I2 = radio2_DAC_I2, IO_IS = radioDACI[2]
    PORT    radio_DAC_I3 = radio2_DAC_I3, IO_IS = radioDACI[3]
    PORT    radio_DAC_I4 = radio2_DAC_I4, IO_IS = radioDACI[4]
    PORT    radio_DAC_I5 = radio2_DAC_I5, IO_IS = radioDACI[5]
    PORT    radio_DAC_I6 = radio2_DAC_I6, IO_IS = radioDACI[6]
    PORT    radio_DAC_I7 = radio2_DAC_I7, IO_IS = radioDACI[7]
    PORT    radio_DAC_I8 = radio2_DAC_I8, IO_IS = radioDACI[8]
    PORT    radio_DAC_I9 = radio2_DAC_I9, IO_IS = radioDACI[9]
    PORT    radio_DAC_I10 = radio2_DAC_I10, IO_IS = radioDACI[10]
    PORT    radio_DAC_I11 = radio2_DAC_I11, IO_IS = radioDACI[11]
    PORT    radio_DAC_I12 = radio2_DAC_I12, IO_IS = radioDACI[12]
    PORT    radio_DAC_I13 = radio2_DAC_I13, IO_IS = radioDACI[13]
    PORT    radio_DAC_I14 = radio2_DAC_I14, IO_IS = radioDACI[14]
    PORT    radio_DAC_I15 = radio2_DAC_I15, IO_IS = radioDACI[15]

    PORT    radio_DAC_Q0 = radio2_DAC_Q0, IO_IS = radioDACQ[0]
    PORT    radio_DAC_Q1 = radio2_DAC_Q1, IO_IS = radioDACQ[1]
    PORT    radio_DAC_Q2 = radio2_DAC_Q2, IO_IS = radioDACQ[2]
    PORT    radio_DAC_Q3 = radio2_DAC_Q3, IO_IS = radioDACQ[3]
    PORT    radio_DAC_Q4 = radio2_DAC_Q4, IO_IS = radioDACQ[4]
    PORT    radio_DAC_Q5 = radio2_DAC_Q5, IO_IS = radioDACQ[5]
    PORT    radio_DAC_Q6 = radio2_DAC_Q6, IO_IS = radioDACQ[6]
    PORT    radio_DAC_Q7 = radio2_DAC_Q7, IO_IS = radioDACQ[7]
    PORT    radio_DAC_Q8 = radio2_DAC_Q8, IO_IS = radioDACQ[8]
    PORT    radio_DAC_Q9 = radio2_DAC_Q9, IO_IS = radioDACQ[9]
    PORT    radio_DAC_Q10 = radio2_DAC_Q10, IO_IS = radioDACQ[10]
    PORT    radio_DAC_Q11 = radio2_DAC_Q11, IO_IS = radioDACQ[11]
    PORT    radio_DAC_Q12 = radio2_DAC_Q12, IO_IS = radioDACQ[12]
    PORT    radio_DAC_Q13 = radio2_DAC_Q13, IO_IS = radioDACQ[13]
    PORT    radio_DAC_Q14 = radio2_DAC_Q14, IO_IS = radioDACQ[14]
    PORT    radio_DAC_Q15 = radio2_DAC_Q15, IO_IS = radioDACQ[15]

    ##########################################
    #Radio Controller <-> Radio Bridge Ports #
    ##########################################
    PORT    controller_logic_clk = controller_logic_clk
    PORT    controller_interpfiltbypass = controller_radio2_interpfiltbypass
    PORT    controller_decfiltbypass = controller_radio2_decfiltbypass
    PORT    controller_spi_clk = controller_spi_clk 
    PORT    controller_spi_data = controller_spi_data 
    PORT    controller_radio_cs = controller_radio2_cs 
    PORT    controller_dac_cs = controller_dac2_cs 
    PORT    controller_SHDN = controller_radio2_SHDN 
    PORT    controller_TxEn = controller_radio2_TxEn 
    PORT    controller_RxEn = controller_radio2_RxEn 
    PORT    controller_RxHP = controller_radio2_RxHP 
    PORT    controller_24PA = controller_radio2_24PA 
    PORT    controller_5PA = controller_radio2_5PA 
    PORT    controller_ANTSW0 = controller_radio2_ANTSW0, IO_IS = c2b_ANTSW[0]
    PORT    controller_ANTSW1 = controller_radio2_ANTSW1, IO_IS = c2b_ANTSW[1] 
    PORT    controller_LED0 = controller_radio2_LED0, IO_IS = c2b_LED[0]
    PORT    controller_LED1 = controller_radio2_LED1, IO_IS = c2b_LED[1]
    PORT    controller_LED2 = controller_radio2_LED2, IO_IS = c2b_LED[2]
    PORT    controller_RX_ADC_DCS = controller_radio2_RX_ADC_DCS
    PORT    controller_RX_ADC_DFS = controller_radio2_RX_ADC_DFS
    PORT    controller_RX_ADC_PWDNA = controller_radio2_RX_ADC_PWDNA
    PORT    controller_RX_ADC_PWDNB = controller_radio2_RX_ADC_PWDNB
    PORT    controller_DIPSW0 = controller_radio2_DIPSW0, IO_IS = c2b_DIPSW[0]
    PORT    controller_DIPSW1 = controller_radio2_DIPSW1, IO_IS = c2b_DIPSW[1]
    PORT    controller_DIPSW2 = controller_radio2_DIPSW2, IO_IS = c2b_DIPSW[2]
    PORT    controller_DIPSW3 = controller_radio2_DIPSW3, IO_IS = c2b_DIPSW[3]
    PORT    controller_RSSI_ADC_CLAMP = controller_radio2_RSSI_ADC_CLAMP
    PORT    controller_RSSI_ADC_HIZ = controller_radio2_RSSI_ADC_HIZ
    PORT    controller_RSSI_ADC_SLEEP = controller_radio2_RSSI_ADC_SLEEP
    PORT    controller_RSSI_ADC_D0 = controller_radio2_RSSI_ADC_D0, IO_IS = c2b_RSSI_ADC_D[0]
    PORT    controller_RSSI_ADC_D1 = controller_radio2_RSSI_ADC_D1, IO_IS = c2b_RSSI_ADC_D[1]
    PORT    controller_RSSI_ADC_D2 = controller_radio2_RSSI_ADC_D2, IO_IS = c2b_RSSI_ADC_D[2]
    PORT    controller_RSSI_ADC_D3 = controller_radio2_RSSI_ADC_D3, IO_IS = c2b_RSSI_ADC_D[3]
    PORT    controller_RSSI_ADC_D4 = controller_radio2_RSSI_ADC_D4, IO_IS = c2b_RSSI_ADC_D[4]
    PORT    controller_RSSI_ADC_D5 = controller_radio2_RSSI_ADC_D5, IO_IS = c2b_RSSI_ADC_D[5]
    PORT    controller_RSSI_ADC_D6 = controller_radio2_RSSI_ADC_D6, IO_IS = c2b_RSSI_ADC_D[6]
    PORT    controller_RSSI_ADC_D7 = controller_radio2_RSSI_ADC_D7, IO_IS = c2b_RSSI_ADC_D[7]
    PORT    controller_RSSI_ADC_D8 = controller_radio2_RSSI_ADC_D8, IO_IS = c2b_RSSI_ADC_D[8]
    PORT    controller_RSSI_ADC_D9 = controller_radio2_RSSI_ADC_D9, IO_IS = c2b_RSSI_ADC_D[9]
    PORT    controller_LD = controller_radio2_LD
    PORT    controller_RX_ADC_OTRA = controller_radio2_RX_ADC_OTRA
    PORT    controller_RX_ADC_OTRB = controller_radio2_RX_ADC_OTRB
    PORT    controller_RSSI_ADC_OTR = controller_radio2_RSSI_ADC_OTR
    PORT    controller_dac_PLL_LOCK = controller_dac2_PLL_LOCK
    PORT    controller_dac_RESET = controller_dac2_RESET
    PORT    user_Tx_gain0 = controller_radio2_TxGain0, IO_IS = userTxG[0]
    PORT    user_Tx_gain1 = controller_radio2_TxGain1, IO_IS = userTxG[1]
    PORT    user_Tx_gain2 = controller_radio2_TxGain2, IO_IS = userTxG[2]
    PORT    user_Tx_gain3 = controller_radio2_TxGain3, IO_IS = userTxG[3]
    PORT    user_Tx_gain4 = controller_radio2_TxGain4, IO_IS = userTxG[4]
    PORT    user_Tx_gain5 = controller_radio2_TxGain5, IO_IS = userTxG[5]
    PORT    controller_TxStart = controller_radio2_TxStart
    PORT    controller_SHDN_external = controller_radio2_SHDN_external
    PORT    controller_RxEn_external = controller_radio2_RxEn_external
    PORT    controller_TxEn_external = controller_radio2_TxEn_external
    PORT    controller_RxHP_external = controller_radio2_RxHP_external

    #####################################
    #Radio Bridge <-> Radio Board Ports #
    #####################################
    PORT    dac_spi_data = dac2_spi_data
    PORT    dac_spi_cs = dac2_spi_cs
    PORT    dac_spi_clk = dac2_spi_clk
    PORT    radio_spi_clk = radio2_spi_clk
    PORT    radio_spi_data = radio2_spi_data
    PORT    radio_spi_cs = radio2_spi_cs
    PORT    radio_SHDN = radio2_SHDN
    PORT    radio_TxEn = radio2_TxEn
    PORT    radio_RxEn = radio2_RxEn
    PORT    radio_RxHP = radio2_RxHP
    PORT    radio_24PA = radio2_24PA
    PORT    radio_5PA = radio2_5PA
    PORT    radio_ANTSW0 = radio2_ANTSW0, IO_IS = b2r_ANTSW[0]
    PORT    radio_ANTSW1 = radio2_ANTSW1, IO_IS = b2r_ANTSW[1]
    PORT    radio_LED0 = radio2_LED0, IO_IS = b2r_LED[0]
    PORT    radio_LED1 = radio2_LED1, IO_IS = b2r_LED[1]
    PORT    radio_LED2 = radio2_LED2, IO_IS = b2r_LED[2]
    PORT    radio_RX_ADC_DCS = radio2_RX_ADC_DCS
    PORT    radio_RX_ADC_DFS = radio2_RX_ADC_DFS
    PORT    radio_RX_ADC_PWDNA = radio2_RX_ADC_PWDNA
    PORT    radio_RX_ADC_PWDNB = radio2_RX_ADC_PWDNB
    PORT    radio_DIPSW0 = radio2_DIPSW0, IO_IS = b2r_DIPSW[0]
    PORT    radio_DIPSW1 = radio2_DIPSW1, IO_IS = b2r_DIPSW[1]
    PORT    radio_DIPSW2 = radio2_DIPSW2, IO_IS = b2r_DIPSW[2]
    PORT    radio_DIPSW3 = radio2_DIPSW3, IO_IS = b2r_DIPSW[3]
    PORT    radio_RSSI_ADC_clk = radio2_RSSI_ADC_clk
    PORT    radio_RSSI_ADC_CLAMP = radio2_RSSI_ADC_CLAMP
    PORT    radio_RSSI_ADC_HIZ = radio2_RSSI_ADC_HIZ
    PORT    radio_RSSI_ADC_SLEEP = radio2_RSSI_ADC_SLEEP
    PORT    radio_RSSI_ADC_D0 = radio2_RSSI_ADC_D0, IO_IS = b2r_RSSI_ADC_D[0]
    PORT    radio_RSSI_ADC_D1 = radio2_RSSI_ADC_D1, IO_IS = b2r_RSSI_ADC_D[1]
    PORT    radio_RSSI_ADC_D2 = radio2_RSSI_ADC_D2, IO_IS = b2r_RSSI_ADC_D[2]
    PORT    radio_RSSI_ADC_D3 = radio2_RSSI_ADC_D3, IO_IS = b2r_RSSI_ADC_D[3]
    PORT    radio_RSSI_ADC_D4 = radio2_RSSI_ADC_D4, IO_IS = b2r_RSSI_ADC_D[4]
    PORT    radio_RSSI_ADC_D5 = radio2_RSSI_ADC_D5, IO_IS = b2r_RSSI_ADC_D[5]
    PORT    radio_RSSI_ADC_D6 = radio2_RSSI_ADC_D6, IO_IS = b2r_RSSI_ADC_D[6]
    PORT    radio_RSSI_ADC_D7 = radio2_RSSI_ADC_D7, IO_IS = b2r_RSSI_ADC_D[7]
    PORT    radio_RSSI_ADC_D8 = radio2_RSSI_ADC_D8, IO_IS = b2r_RSSI_ADC_D[8]
    PORT    radio_RSSI_ADC_D9 = radio2_RSSI_ADC_D9, IO_IS = b2r_RSSI_ADC_D[9]
    PORT    radio_LD = radio2_LD
    PORT    radio_RX_ADC_OTRA = radio2_RX_ADC_OTRA
    PORT    radio_RX_ADC_OTRB = radio2_RX_ADC_OTRB
    PORT    radio_RSSI_ADC_OTR = radio2_RSSI_ADC_OTR
    PORT    radio_dac_PLL_LOCK = radio2_dac2_PLL_LOCK
    PORT    radio_dac_RESET = radio2_dac2_RESET

    PORT    user_EEPROM_IO_T = DQ2_T_user_EEPROM_IO_T
    PORT    user_EEPROM_IO_O = DQ2_O_user_EEPROM_IO_O
    PORT    user_EEPROM_IO_I = DQ2_I_user_EEPROM_IO_I
    PORT    radio_EEPROM_IO = radio2_EEPROM_IO
END

#Radio Controller -> Radio Board Bridge for Slot #3
BEGIN IO_INTERFACE
    ATTRIBUTE IOTYPE = WARP_RADIOBRIDGE_V1
    ATTRIBUTE INSTANCE = radio_bridge_slot_3
    ATTRIBUTE EXCLUSIVE = slot3
    ATTRIBUTE ALERT = 'Enable this peripheral only if a radio board is mounted in daughtercard slot 3.'

    PORT    converter_clock_out = radio3_conv_clk_p

    PORT    radio_b0 = radio3_b0, IO_IS = radioGain[0]
    PORT    radio_b1 = radio3_b1, IO_IS = radioGain[1]
    PORT    radio_b2 = radio3_b2, IO_IS = radioGain[2]
    PORT    radio_b3 = radio3_b3, IO_IS = radioGain[3]
    PORT    radio_b4 = radio3_b4, IO_IS = radioGain[4]
    PORT    radio_b5 = radio3_b5, IO_IS = radioGain[5]
    PORT    radio_b6 = radio3_b6, IO_IS = radioGain[6]

    PORT    radio_ADC_I0 = radio3_ADC_I0, IO_IS = radioADCI[0]
    PORT    radio_ADC_I1 = radio3_ADC_I1, IO_IS = radioADCI[1]
    PORT    radio_ADC_I2 = radio3_ADC_I2, IO_IS = radioADCI[2]
    PORT    radio_ADC_I3 = radio3_ADC_I3, IO_IS = radioADCI[3]
    PORT    radio_ADC_I4 = radio3_ADC_I4, IO_IS = radioADCI[4]
    PORT    radio_ADC_I5 = radio3_ADC_I5, IO_IS = radioADCI[5]
    PORT    radio_ADC_I6 = radio3_ADC_I6, IO_IS = radioADCI[6]
    PORT    radio_ADC_I7 = radio3_ADC_I7, IO_IS = radioADCI[7]
    PORT    radio_ADC_I8 = radio3_ADC_I8, IO_IS = radioADCI[8]
    PORT    radio_ADC_I9 = radio3_ADC_I9, IO_IS = radioADCI[9]
    PORT    radio_ADC_I10 = radio3_ADC_I10, IO_IS = radioADCI[10]
    PORT    radio_ADC_I11 = radio3_ADC_I11, IO_IS = radioADCI[11]
    PORT    radio_ADC_I12 = radio3_ADC_I12, IO_IS = radioADCI[12]
    PORT    radio_ADC_I13 = radio3_ADC_I13, IO_IS = radioADCI[13]

    PORT    radio_ADC_Q0 = radio3_ADC_Q0, IO_IS = radioADCQ[0]
    PORT    radio_ADC_Q1 = radio3_ADC_Q1, IO_IS = radioADCQ[1]
    PORT    radio_ADC_Q2 = radio3_ADC_Q2, IO_IS = radioADCQ[2]
    PORT    radio_ADC_Q3 = radio3_ADC_Q3, IO_IS = radioADCQ[3]
    PORT    radio_ADC_Q4 = radio3_ADC_Q4, IO_IS = radioADCQ[4]
    PORT    radio_ADC_Q5 = radio3_ADC_Q5, IO_IS = radioADCQ[5]
    PORT    radio_ADC_Q6 = radio3_ADC_Q6, IO_IS = radioADCQ[6]
    PORT    radio_ADC_Q7 = radio3_ADC_Q7, IO_IS = radioADCQ[7]
    PORT    radio_ADC_Q8 = radio3_ADC_Q8, IO_IS = radioADCQ[8]
    PORT    radio_ADC_Q9 = radio3_ADC_Q9, IO_IS = radioADCQ[9]
    PORT    radio_ADC_Q10 = radio3_ADC_Q10, IO_IS = radioADCQ[10]
    PORT    radio_ADC_Q11 = radio3_ADC_Q11, IO_IS = radioADCQ[11]
    PORT    radio_ADC_Q12 = radio3_ADC_Q12, IO_IS = radioADCQ[12]
    PORT    radio_ADC_Q13 = radio3_ADC_Q13, IO_IS = radioADCQ[13]

    PORT    radio_DAC_I0 = radio3_DAC_I0, IO_IS = radioDACI[0]
    PORT    radio_DAC_I1 = radio3_DAC_I1, IO_IS = radioDACI[1]
    PORT    radio_DAC_I2 = radio3_DAC_I2, IO_IS = radioDACI[2]
    PORT    radio_DAC_I3 = radio3_DAC_I3, IO_IS = radioDACI[3]
    PORT    radio_DAC_I4 = radio3_DAC_I4, IO_IS = radioDACI[4]
    PORT    radio_DAC_I5 = radio3_DAC_I5, IO_IS = radioDACI[5]
    PORT    radio_DAC_I6 = radio3_DAC_I6, IO_IS = radioDACI[6]
    PORT    radio_DAC_I7 = radio3_DAC_I7, IO_IS = radioDACI[7]
    PORT    radio_DAC_I8 = radio3_DAC_I8, IO_IS = radioDACI[8]
    PORT    radio_DAC_I9 = radio3_DAC_I9, IO_IS = radioDACI[9]
    PORT    radio_DAC_I10 = radio3_DAC_I10, IO_IS = radioDACI[10]
    PORT    radio_DAC_I11 = radio3_DAC_I11, IO_IS = radioDACI[11]
    PORT    radio_DAC_I12 = radio3_DAC_I12, IO_IS = radioDACI[12]
    PORT    radio_DAC_I13 = radio3_DAC_I13, IO_IS = radioDACI[13]
    PORT    radio_DAC_I14 = radio3_DAC_I14, IO_IS = radioDACI[14]
    PORT    radio_DAC_I15 = radio3_DAC_I15, IO_IS = radioDACI[15]

    PORT    radio_DAC_Q0 = radio3_DAC_Q0, IO_IS = radioDACQ[0]
    PORT    radio_DAC_Q1 = radio3_DAC_Q1, IO_IS = radioDACQ[1]
    PORT    radio_DAC_Q2 = radio3_DAC_Q2, IO_IS = radioDACQ[2]
    PORT    radio_DAC_Q3 = radio3_DAC_Q3, IO_IS = radioDACQ[3]
    PORT    radio_DAC_Q4 = radio3_DAC_Q4, IO_IS = radioDACQ[4]
    PORT    radio_DAC_Q5 = radio3_DAC_Q5, IO_IS = radioDACQ[5]
    PORT    radio_DAC_Q6 = radio3_DAC_Q6, IO_IS = radioDACQ[6]
    PORT    radio_DAC_Q7 = radio3_DAC_Q7, IO_IS = radioDACQ[7]
    PORT    radio_DAC_Q8 = radio3_DAC_Q8, IO_IS = radioDACQ[8]
    PORT    radio_DAC_Q9 = radio3_DAC_Q9, IO_IS = radioDACQ[9]
    PORT    radio_DAC_Q10 = radio3_DAC_Q10, IO_IS = radioDACQ[10]
    PORT    radio_DAC_Q11 = radio3_DAC_Q11, IO_IS = radioDACQ[11]
    PORT    radio_DAC_Q12 = radio3_DAC_Q12, IO_IS = radioDACQ[12]
    PORT    radio_DAC_Q13 = radio3_DAC_Q13, IO_IS = radioDACQ[13]
    PORT    radio_DAC_Q14 = radio3_DAC_Q14, IO_IS = radioDACQ[14]
    PORT    radio_DAC_Q15 = radio3_DAC_Q15, IO_IS = radioDACQ[15]

    ##########################################
    #Radio Controller <-> Radio Bridge Ports #
    ##########################################
    PORT    controller_logic_clk = controller_logic_clk
    PORT    controller_interpfiltbypass = controller_radio3_interpfiltbypass
    PORT    controller_decfiltbypass = controller_radio3_decfiltbypass
    PORT    controller_spi_clk = controller_spi_clk 
    PORT    controller_spi_data = controller_spi_data 
    PORT    controller_radio_cs = controller_radio3_cs 
    PORT    controller_dac_cs = controller_dac3_cs 
    PORT    controller_SHDN = controller_radio3_SHDN 
    PORT    controller_TxEn = controller_radio3_TxEn 
    PORT    controller_RxEn = controller_radio3_RxEn 
    PORT    controller_RxHP = controller_radio3_RxHP 
    PORT    controller_24PA = controller_radio3_24PA 
    PORT    controller_5PA = controller_radio3_5PA 
    PORT    controller_ANTSW0 = controller_radio3_ANTSW0, IO_IS = c2b_ANTSW[0]
    PORT    controller_ANTSW1 = controller_radio3_ANTSW1, IO_IS = c2b_ANTSW[1] 
    PORT    controller_LED0 = controller_radio3_LED0, IO_IS = c2b_LED[0]
    PORT    controller_LED1 = controller_radio3_LED1, IO_IS = c2b_LED[1]
    PORT    controller_LED2 = controller_radio3_LED2, IO_IS = c2b_LED[2]
    PORT    controller_RX_ADC_DCS = controller_radio3_RX_ADC_DCS
    PORT    controller_RX_ADC_DFS = controller_radio3_RX_ADC_DFS
    PORT    controller_RX_ADC_PWDNA = controller_radio3_RX_ADC_PWDNA
    PORT    controller_RX_ADC_PWDNB = controller_radio3_RX_ADC_PWDNB
    PORT    controller_DIPSW0 = controller_radio3_DIPSW0, IO_IS = c2b_DIPSW[0]
    PORT    controller_DIPSW1 = controller_radio3_DIPSW1, IO_IS = c2b_DIPSW[1]
    PORT    controller_DIPSW2 = controller_radio3_DIPSW2, IO_IS = c2b_DIPSW[2]
    PORT    controller_DIPSW3 = controller_radio3_DIPSW3, IO_IS = c2b_DIPSW[3]
    PORT    controller_RSSI_ADC_CLAMP = controller_radio3_RSSI_ADC_CLAMP
    PORT    controller_RSSI_ADC_HIZ = controller_radio3_RSSI_ADC_HIZ
    PORT    controller_RSSI_ADC_SLEEP = controller_radio3_RSSI_ADC_SLEEP
    PORT    controller_RSSI_ADC_D0 = controller_radio3_RSSI_ADC_D0, IO_IS = c2b_RSSI_ADC_D[0]
    PORT    controller_RSSI_ADC_D1 = controller_radio3_RSSI_ADC_D1, IO_IS = c2b_RSSI_ADC_D[1]
    PORT    controller_RSSI_ADC_D2 = controller_radio3_RSSI_ADC_D2, IO_IS = c2b_RSSI_ADC_D[2]
    PORT    controller_RSSI_ADC_D3 = controller_radio3_RSSI_ADC_D3, IO_IS = c2b_RSSI_ADC_D[3]
    PORT    controller_RSSI_ADC_D4 = controller_radio3_RSSI_ADC_D4, IO_IS = c2b_RSSI_ADC_D[4]
    PORT    controller_RSSI_ADC_D5 = controller_radio3_RSSI_ADC_D5, IO_IS = c2b_RSSI_ADC_D[5]
    PORT    controller_RSSI_ADC_D6 = controller_radio3_RSSI_ADC_D6, IO_IS = c2b_RSSI_ADC_D[6]
    PORT    controller_RSSI_ADC_D7 = controller_radio3_RSSI_ADC_D7, IO_IS = c2b_RSSI_ADC_D[7]
    PORT    controller_RSSI_ADC_D8 = controller_radio3_RSSI_ADC_D8, IO_IS = c2b_RSSI_ADC_D[8]
    PORT    controller_RSSI_ADC_D9 = controller_radio3_RSSI_ADC_D9, IO_IS = c2b_RSSI_ADC_D[9]
    PORT    controller_LD = controller_radio3_LD
    PORT    controller_RX_ADC_OTRA = controller_radio3_RX_ADC_OTRA
    PORT    controller_RX_ADC_OTRB = controller_radio3_RX_ADC_OTRB
    PORT    controller_RSSI_ADC_OTR = controller_radio3_RSSI_ADC_OTR
    PORT    controller_dac_PLL_LOCK = controller_dac3_PLL_LOCK
    PORT    controller_dac_RESET = controller_dac3_RESET
    PORT    user_Tx_gain0 = controller_radio3_TxGain0, IO_IS = userTxG[0]
    PORT    user_Tx_gain1 = controller_radio3_TxGain1, IO_IS = userTxG[1]
    PORT    user_Tx_gain2 = controller_radio3_TxGain2, IO_IS = userTxG[2]
    PORT    user_Tx_gain3 = controller_radio3_TxGain3, IO_IS = userTxG[3]
    PORT    user_Tx_gain4 = controller_radio3_TxGain4, IO_IS = userTxG[4]
    PORT    user_Tx_gain5 = controller_radio3_TxGain5, IO_IS = userTxG[5]
    PORT    controller_TxStart = controller_radio3_TxStart
    PORT    controller_SHDN_external = controller_radio3_SHDN_external
    PORT    controller_RxEn_external = controller_radio3_RxEn_external
    PORT    controller_TxEn_external = controller_radio3_TxEn_external
    PORT    controller_RxHP_external = controller_radio3_RxHP_external

    #####################################
    #Radio Bridge <-> Radio Board Ports #
    #####################################
    PORT    dac_spi_data = dac3_spi_data
    PORT    dac_spi_cs = dac3_spi_cs
    PORT    dac_spi_clk = dac3_spi_clk
    PORT    radio_spi_clk = radio3_spi_clk
    PORT    radio_spi_data = radio3_spi_data
    PORT    radio_spi_cs = radio3_spi_cs
    PORT    radio_SHDN = radio3_SHDN
    PORT    radio_TxEn = radio3_TxEn
    PORT    radio_RxEn = radio3_RxEn
    PORT    radio_RxHP = radio3_RxHP
    PORT    radio_24PA = radio3_24PA
    PORT    radio_5PA = radio3_5PA
    PORT    radio_ANTSW0 = radio3_ANTSW0, IO_IS = b2r_ANTSW[0]
    PORT    radio_ANTSW1 = radio3_ANTSW1, IO_IS = b2r_ANTSW[1]
    PORT    radio_LED0 = radio3_LED0, IO_IS = b2r_LED[0]
    PORT    radio_LED1 = radio3_LED1, IO_IS = b2r_LED[1]
    PORT    radio_LED2 = radio3_LED2, IO_IS = b2r_LED[2]
    PORT    radio_RX_ADC_DCS = radio3_RX_ADC_DCS
    PORT    radio_RX_ADC_DFS = radio3_RX_ADC_DFS
    PORT    radio_RX_ADC_PWDNA = radio3_RX_ADC_PWDNA
    PORT    radio_RX_ADC_PWDNB = radio3_RX_ADC_PWDNB
    PORT    radio_DIPSW0 = radio3_DIPSW0, IO_IS = b2r_DIPSW[0]
    PORT    radio_DIPSW1 = radio3_DIPSW1, IO_IS = b2r_DIPSW[1]
    PORT    radio_DIPSW2 = radio3_DIPSW2, IO_IS = b2r_DIPSW[2]
    PORT    radio_DIPSW3 = radio3_DIPSW3, IO_IS = b2r_DIPSW[3]
    PORT    radio_RSSI_ADC_clk = radio3_RSSI_ADC_clk
    PORT    radio_RSSI_ADC_CLAMP = radio3_RSSI_ADC_CLAMP
    PORT    radio_RSSI_ADC_HIZ = radio3_RSSI_ADC_HIZ
    PORT    radio_RSSI_ADC_SLEEP = radio3_RSSI_ADC_SLEEP
    PORT    radio_RSSI_ADC_D0 = radio3_RSSI_ADC_D0, IO_IS = b2r_RSSI_ADC_D[0]
    PORT    radio_RSSI_ADC_D1 = radio3_RSSI_ADC_D1, IO_IS = b2r_RSSI_ADC_D[1]
    PORT    radio_RSSI_ADC_D2 = radio3_RSSI_ADC_D2, IO_IS = b2r_RSSI_ADC_D[2]
    PORT    radio_RSSI_ADC_D3 = radio3_RSSI_ADC_D3, IO_IS = b2r_RSSI_ADC_D[3]
    PORT    radio_RSSI_ADC_D4 = radio3_RSSI_ADC_D4, IO_IS = b2r_RSSI_ADC_D[4]
    PORT    radio_RSSI_ADC_D5 = radio3_RSSI_ADC_D5, IO_IS = b2r_RSSI_ADC_D[5]
    PORT    radio_RSSI_ADC_D6 = radio3_RSSI_ADC_D6, IO_IS = b2r_RSSI_ADC_D[6]
    PORT    radio_RSSI_ADC_D7 = radio3_RSSI_ADC_D7, IO_IS = b2r_RSSI_ADC_D[7]
    PORT    radio_RSSI_ADC_D8 = radio3_RSSI_ADC_D8, IO_IS = b2r_RSSI_ADC_D[8]
    PORT    radio_RSSI_ADC_D9 = radio3_RSSI_ADC_D9, IO_IS = b2r_RSSI_ADC_D[9]
    PORT    radio_LD = radio3_LD
    PORT    radio_RX_ADC_OTRA = radio3_RX_ADC_OTRA
    PORT    radio_RX_ADC_OTRB = radio3_RX_ADC_OTRB
    PORT    radio_RSSI_ADC_OTR = radio3_RSSI_ADC_OTR
    PORT    radio_dac_PLL_LOCK = radio3_dac3_PLL_LOCK
    PORT    radio_dac_RESET = radio3_dac3_RESET

    PORT    user_EEPROM_IO_T = DQ3_T_user_EEPROM_IO_T
    PORT    user_EEPROM_IO_O = DQ3_O_user_EEPROM_IO_O
    PORT    user_EEPROM_IO_I = DQ3_I_user_EEPROM_IO_I
    PORT    radio_EEPROM_IO = radio3_EEPROM_IO
END

#Radio Controller -> Radio Board Bridge for Slot #4
BEGIN IO_INTERFACE
    ATTRIBUTE IOTYPE = WARP_RADIOBRIDGE_V1
    ATTRIBUTE INSTANCE = radio_bridge_slot_4
    ATTRIBUTE EXCLUSIVE = slot4
    ATTRIBUTE ALERT = 'Enable this peripheral only if a radio board is mounted in daughtercard slot 4.'

    PORT    converter_clock_out = radio4_conv_clk_p

    PORT    radio_b0 = radio4_b0, IO_IS = radioGain[0]
    PORT    radio_b1 = radio4_b1, IO_IS = radioGain[1]
    PORT    radio_b2 = radio4_b2, IO_IS = radioGain[2]
    PORT    radio_b3 = radio4_b3, IO_IS = radioGain[3]
    PORT    radio_b4 = radio4_b4, IO_IS = radioGain[4]
    PORT    radio_b5 = radio4_b5, IO_IS = radioGain[5]
    PORT    radio_b6 = radio4_b6, IO_IS = radioGain[6]

    PORT    radio_ADC_I0 = radio4_ADC_I0, IO_IS = radioADCI[0]
    PORT    radio_ADC_I1 = radio4_ADC_I1, IO_IS = radioADCI[1]
    PORT    radio_ADC_I2 = radio4_ADC_I2, IO_IS = radioADCI[2]
    PORT    radio_ADC_I3 = radio4_ADC_I3, IO_IS = radioADCI[3]
    PORT    radio_ADC_I4 = radio4_ADC_I4, IO_IS = radioADCI[4]
    PORT    radio_ADC_I5 = radio4_ADC_I5, IO_IS = radioADCI[5]
    PORT    radio_ADC_I6 = radio4_ADC_I6, IO_IS = radioADCI[6]
    PORT    radio_ADC_I7 = radio4_ADC_I7, IO_IS = radioADCI[7]
    PORT    radio_ADC_I8 = radio4_ADC_I8, IO_IS = radioADCI[8]
    PORT    radio_ADC_I9 = radio4_ADC_I9, IO_IS = radioADCI[9]
    PORT    radio_ADC_I10 = radio4_ADC_I10, IO_IS = radioADCI[10]
    PORT    radio_ADC_I11 = radio4_ADC_I11, IO_IS = radioADCI[11]
    PORT    radio_ADC_I12 = radio4_ADC_I12, IO_IS = radioADCI[12]
    PORT    radio_ADC_I13 = radio4_ADC_I13, IO_IS = radioADCI[13]

    PORT    radio_ADC_Q0 = radio4_ADC_Q0, IO_IS = radioADCQ[0]
    PORT    radio_ADC_Q1 = radio4_ADC_Q1, IO_IS = radioADCQ[1]
    PORT    radio_ADC_Q2 = radio4_ADC_Q2, IO_IS = radioADCQ[2]
    PORT    radio_ADC_Q3 = radio4_ADC_Q3, IO_IS = radioADCQ[3]
    PORT    radio_ADC_Q4 = radio4_ADC_Q4, IO_IS = radioADCQ[4]
    PORT    radio_ADC_Q5 = radio4_ADC_Q5, IO_IS = radioADCQ[5]
    PORT    radio_ADC_Q6 = radio4_ADC_Q6, IO_IS = radioADCQ[6]
    PORT    radio_ADC_Q7 = radio4_ADC_Q7, IO_IS = radioADCQ[7]
    PORT    radio_ADC_Q8 = radio4_ADC_Q8, IO_IS = radioADCQ[8]
    PORT    radio_ADC_Q9 = radio4_ADC_Q9, IO_IS = radioADCQ[9]
    PORT    radio_ADC_Q10 = radio4_ADC_Q10, IO_IS = radioADCQ[10]
    PORT    radio_ADC_Q11 = radio4_ADC_Q11, IO_IS = radioADCQ[11]
    PORT    radio_ADC_Q12 = radio4_ADC_Q12, IO_IS = radioADCQ[12]
    PORT    radio_ADC_Q13 = radio4_ADC_Q13, IO_IS = radioADCQ[13]

    PORT    radio_DAC_I0 = radio4_DAC_I0, IO_IS = radioDACI[0]
    PORT    radio_DAC_I1 = radio4_DAC_I1, IO_IS = radioDACI[1]
    PORT    radio_DAC_I2 = radio4_DAC_I2, IO_IS = radioDACI[2]
    PORT    radio_DAC_I3 = radio4_DAC_I3, IO_IS = radioDACI[3]
    PORT    radio_DAC_I4 = radio4_DAC_I4, IO_IS = radioDACI[4]
    PORT    radio_DAC_I5 = radio4_DAC_I5, IO_IS = radioDACI[5]
    PORT    radio_DAC_I6 = radio4_DAC_I6, IO_IS = radioDACI[6]
    PORT    radio_DAC_I7 = radio4_DAC_I7, IO_IS = radioDACI[7]
    PORT    radio_DAC_I8 = radio4_DAC_I8, IO_IS = radioDACI[8]
    PORT    radio_DAC_I9 = radio4_DAC_I9, IO_IS = radioDACI[9]
    PORT    radio_DAC_I10 = radio4_DAC_I10, IO_IS = radioDACI[10]
    PORT    radio_DAC_I11 = radio4_DAC_I11, IO_IS = radioDACI[11]
    PORT    radio_DAC_I12 = radio4_DAC_I12, IO_IS = radioDACI[12]
    PORT    radio_DAC_I13 = radio4_DAC_I13, IO_IS = radioDACI[13]
    PORT    radio_DAC_I14 = radio4_DAC_I14, IO_IS = radioDACI[14]
    PORT    radio_DAC_I15 = radio4_DAC_I15, IO_IS = radioDACI[15]

    PORT    radio_DAC_Q0 = radio4_DAC_Q0, IO_IS = radioDACQ[0]
    PORT    radio_DAC_Q1 = radio4_DAC_Q1, IO_IS = radioDACQ[1]
    PORT    radio_DAC_Q2 = radio4_DAC_Q2, IO_IS = radioDACQ[2]
    PORT    radio_DAC_Q3 = radio4_DAC_Q3, IO_IS = radioDACQ[3]
    PORT    radio_DAC_Q4 = radio4_DAC_Q4, IO_IS = radioDACQ[4]
    PORT    radio_DAC_Q5 = radio4_DAC_Q5, IO_IS = radioDACQ[5]
    PORT    radio_DAC_Q6 = radio4_DAC_Q6, IO_IS = radioDACQ[6]
    PORT    radio_DAC_Q7 = radio4_DAC_Q7, IO_IS = radioDACQ[7]
    PORT    radio_DAC_Q8 = radio4_DAC_Q8, IO_IS = radioDACQ[8]
    PORT    radio_DAC_Q9 = radio4_DAC_Q9, IO_IS = radioDACQ[9]
    PORT    radio_DAC_Q10 = radio4_DAC_Q10, IO_IS = radioDACQ[10]
    PORT    radio_DAC_Q11 = radio4_DAC_Q11, IO_IS = radioDACQ[11]
    PORT    radio_DAC_Q12 = radio4_DAC_Q12, IO_IS = radioDACQ[12]
    PORT    radio_DAC_Q13 = radio4_DAC_Q13, IO_IS = radioDACQ[13]
    PORT    radio_DAC_Q14 = radio4_DAC_Q14, IO_IS = radioDACQ[14]
    PORT    radio_DAC_Q15 = radio4_DAC_Q15, IO_IS = radioDACQ[15]

    ##########################################
    #Radio Controller <-> Radio Bridge Ports #
    ##########################################
    PORT    controller_logic_clk = controller_logic_clk
    PORT    controller_interpfiltbypass = controller_radio4_interpfiltbypass
    PORT    controller_decfiltbypass = controller_radio4_decfiltbypass
    PORT    controller_spi_clk = controller_spi_clk 
    PORT    controller_spi_data = controller_spi_data 
    PORT    controller_radio_cs = controller_radio4_cs 
    PORT    controller_dac_cs = controller_dac4_cs 
    PORT    controller_SHDN = controller_radio4_SHDN 
    PORT    controller_TxEn = controller_radio4_TxEn 
    PORT    controller_RxEn = controller_radio4_RxEn 
    PORT    controller_RxHP = controller_radio4_RxHP 
    PORT    controller_24PA = controller_radio4_24PA 
    PORT    controller_5PA = controller_radio4_5PA 
    PORT    controller_ANTSW0 = controller_radio4_ANTSW0, IO_IS = c2b_ANTSW[0]
    PORT    controller_ANTSW1 = controller_radio4_ANTSW1, IO_IS = c2b_ANTSW[1] 
    PORT    controller_LED0 = controller_radio4_LED0, IO_IS = c2b_LED[0]
    PORT    controller_LED1 = controller_radio4_LED1, IO_IS = c2b_LED[1]
    PORT    controller_LED2 = controller_radio4_LED2, IO_IS = c2b_LED[2]
    PORT    controller_RX_ADC_DCS = controller_radio4_RX_ADC_DCS
    PORT    controller_RX_ADC_DFS = controller_radio4_RX_ADC_DFS
    PORT    controller_RX_ADC_PWDNA = controller_radio4_RX_ADC_PWDNA
    PORT    controller_RX_ADC_PWDNB = controller_radio4_RX_ADC_PWDNB
    PORT    controller_DIPSW0 = controller_radio4_DIPSW0, IO_IS = c2b_DIPSW[0]
    PORT    controller_DIPSW1 = controller_radio4_DIPSW1, IO_IS = c2b_DIPSW[1]
    PORT    controller_DIPSW2 = controller_radio4_DIPSW2, IO_IS = c2b_DIPSW[2]
    PORT    controller_DIPSW3 = controller_radio4_DIPSW3, IO_IS = c2b_DIPSW[3]
    PORT    controller_RSSI_ADC_CLAMP = controller_radio4_RSSI_ADC_CLAMP
    PORT    controller_RSSI_ADC_HIZ = controller_radio4_RSSI_ADC_HIZ
    PORT    controller_RSSI_ADC_SLEEP = controller_radio4_RSSI_ADC_SLEEP
    PORT    controller_RSSI_ADC_D0 = controller_radio4_RSSI_ADC_D0, IO_IS = c2b_RSSI_ADC_D[0]
    PORT    controller_RSSI_ADC_D1 = controller_radio4_RSSI_ADC_D1, IO_IS = c2b_RSSI_ADC_D[1]
    PORT    controller_RSSI_ADC_D2 = controller_radio4_RSSI_ADC_D2, IO_IS = c2b_RSSI_ADC_D[2]
    PORT    controller_RSSI_ADC_D3 = controller_radio4_RSSI_ADC_D3, IO_IS = c2b_RSSI_ADC_D[3]
    PORT    controller_RSSI_ADC_D4 = controller_radio4_RSSI_ADC_D4, IO_IS = c2b_RSSI_ADC_D[4]
    PORT    controller_RSSI_ADC_D5 = controller_radio4_RSSI_ADC_D5, IO_IS = c2b_RSSI_ADC_D[5]
    PORT    controller_RSSI_ADC_D6 = controller_radio4_RSSI_ADC_D6, IO_IS = c2b_RSSI_ADC_D[6]
    PORT    controller_RSSI_ADC_D7 = controller_radio4_RSSI_ADC_D7, IO_IS = c2b_RSSI_ADC_D[7]
    PORT    controller_RSSI_ADC_D8 = controller_radio4_RSSI_ADC_D8, IO_IS = c2b_RSSI_ADC_D[8]
    PORT    controller_RSSI_ADC_D9 = controller_radio4_RSSI_ADC_D9, IO_IS = c2b_RSSI_ADC_D[9]
    PORT    controller_LD = controller_radio4_LD
    PORT    controller_RX_ADC_OTRA = controller_radio4_RX_ADC_OTRA
    PORT    controller_RX_ADC_OTRB = controller_radio4_RX_ADC_OTRB
    PORT    controller_RSSI_ADC_OTR = controller_radio4_RSSI_ADC_OTR
    PORT    controller_dac_PLL_LOCK = controller_dac4_PLL_LOCK
    PORT    controller_dac_RESET = controller_dac4_RESET
    PORT    user_Tx_gain0 = controller_radio4_TxGain0, IO_IS = userTxG[0]
    PORT    user_Tx_gain1 = controller_radio4_TxGain1, IO_IS = userTxG[1]
    PORT    user_Tx_gain2 = controller_radio4_TxGain2, IO_IS = userTxG[2]
    PORT    user_Tx_gain3 = controller_radio4_TxGain3, IO_IS = userTxG[3]
    PORT    user_Tx_gain4 = controller_radio4_TxGain4, IO_IS = userTxG[4]
    PORT    user_Tx_gain5 = controller_radio4_TxGain5, IO_IS = userTxG[5]
    PORT    controller_TxStart = controller_radio4_TxStart
    PORT    controller_SHDN_external = controller_radio4_SHDN_external
    PORT    controller_RxEn_external = controller_radio4_RxEn_external
    PORT    controller_TxEn_external = controller_radio4_TxEn_external
    PORT    controller_RxHP_external = controller_radio4_RxHP_external

    #####################################
    #Radio Bridge <-> Radio Board Ports #
    #####################################
    PORT    dac_spi_data = dac4_spi_data
    PORT    dac_spi_cs = dac4_spi_cs
    PORT    dac_spi_clk = dac4_spi_clk
    PORT    radio_spi_clk = radio4_spi_clk
    PORT    radio_spi_data = radio4_spi_data
    PORT    radio_spi_cs = radio4_spi_cs
    PORT    radio_SHDN = radio4_SHDN
    PORT    radio_TxEn = radio4_TxEn
    PORT    radio_RxEn = radio4_RxEn
    PORT    radio_RxHP = radio4_RxHP
    PORT    radio_24PA = radio4_24PA
    PORT    radio_5PA = radio4_5PA
    PORT    radio_ANTSW0 = radio4_ANTSW0, IO_IS = b2r_ANTSW[0]
    PORT    radio_ANTSW1 = radio4_ANTSW1, IO_IS = b2r_ANTSW[1]
    PORT    radio_LED0 = radio4_LED0, IO_IS = b2r_LED[0]
    PORT    radio_LED1 = radio4_LED1, IO_IS = b2r_LED[1]
    PORT    radio_LED2 = radio4_LED2, IO_IS = b2r_LED[2]
    PORT    radio_RX_ADC_DCS = radio4_RX_ADC_DCS
    PORT    radio_RX_ADC_DFS = radio4_RX_ADC_DFS
    PORT    radio_RX_ADC_PWDNA = radio4_RX_ADC_PWDNA
    PORT    radio_RX_ADC_PWDNB = radio4_RX_ADC_PWDNB
    PORT    radio_DIPSW0 = radio4_DIPSW0, IO_IS = b2r_DIPSW[0]
    PORT    radio_DIPSW1 = radio4_DIPSW1, IO_IS = b2r_DIPSW[1]
    PORT    radio_DIPSW2 = radio4_DIPSW2, IO_IS = b2r_DIPSW[2]
    PORT    radio_DIPSW3 = radio4_DIPSW3, IO_IS = b2r_DIPSW[3]
    PORT    radio_RSSI_ADC_clk = radio4_RSSI_ADC_clk
    PORT    radio_RSSI_ADC_CLAMP = radio4_RSSI_ADC_CLAMP
    PORT    radio_RSSI_ADC_HIZ = radio4_RSSI_ADC_HIZ
    PORT    radio_RSSI_ADC_SLEEP = radio4_RSSI_ADC_SLEEP
    PORT    radio_RSSI_ADC_D0 = radio4_RSSI_ADC_D0, IO_IS = b2r_RSSI_ADC_D[0]
    PORT    radio_RSSI_ADC_D1 = radio4_RSSI_ADC_D1, IO_IS = b2r_RSSI_ADC_D[1]
    PORT    radio_RSSI_ADC_D2 = radio4_RSSI_ADC_D2, IO_IS = b2r_RSSI_ADC_D[2]
    PORT    radio_RSSI_ADC_D3 = radio4_RSSI_ADC_D3, IO_IS = b2r_RSSI_ADC_D[3]
    PORT    radio_RSSI_ADC_D4 = radio4_RSSI_ADC_D4, IO_IS = b2r_RSSI_ADC_D[4]
    PORT    radio_RSSI_ADC_D5 = radio4_RSSI_ADC_D5, IO_IS = b2r_RSSI_ADC_D[5]
    PORT    radio_RSSI_ADC_D6 = radio4_RSSI_ADC_D6, IO_IS = b2r_RSSI_ADC_D[6]
    PORT    radio_RSSI_ADC_D7 = radio4_RSSI_ADC_D7, IO_IS = b2r_RSSI_ADC_D[7]
    PORT    radio_RSSI_ADC_D8 = radio4_RSSI_ADC_D8, IO_IS = b2r_RSSI_ADC_D[8]
    PORT    radio_RSSI_ADC_D9 = radio4_RSSI_ADC_D9, IO_IS = b2r_RSSI_ADC_D[9]
    PORT    radio_LD = radio4_LD
    PORT    radio_RX_ADC_OTRA = radio4_RX_ADC_OTRA
    PORT    radio_RX_ADC_OTRB = radio4_RX_ADC_OTRB
    PORT    radio_RSSI_ADC_OTR = radio4_RSSI_ADC_OTR
    PORT    radio_dac_PLL_LOCK = radio4_dac4_PLL_LOCK
    PORT    radio_dac_RESET = radio4_dac4_RESET

    PORT    user_EEPROM_IO_T = DQ4_T_user_EEPROM_IO_T
    PORT    user_EEPROM_IO_O = DQ4_O_user_EEPROM_IO_O
    PORT    user_EEPROM_IO_I = DQ4_I_user_EEPROM_IO_I
    PORT    radio_EEPROM_IO = radio4_EEPROM_IO
END

#Analog Bridge for Slot 1
BEGIN IO_INTERFACE
    ATTRIBUTE IOTYPE = WARP_ANALOGBRIDGE_V1
    ATTRIBUTE INSTANCE = analog_bridge_slot_1
    ATTRIBUTE EXCLUSIVE = slot1
    ATTRIBUTE ALERT = 'Enable this peripheral only if a analog board is mounted in daughtercard slot 1.'
    
    PORT    clock_out = analog1_clock_out

    PORT    analog_DAC1_A0 = analog1_DAC1_A0, IO_IS = analogDAC1A[0]
    PORT    analog_DAC1_A1 = analog1_DAC1_A1, IO_IS = analogDAC1A[1]
    PORT    analog_DAC1_A2 = analog1_DAC1_A2, IO_IS = analogDAC1A[2]
    PORT    analog_DAC1_A3 = analog1_DAC1_A3, IO_IS = analogDAC1A[3]
    PORT    analog_DAC1_A4 = analog1_DAC1_A4, IO_IS = analogDAC1A[4]
    PORT    analog_DAC1_A5 = analog1_DAC1_A5, IO_IS = analogDAC1A[5]
    PORT    analog_DAC1_A6 = analog1_DAC1_A6, IO_IS = analogDAC1A[6]
    PORT    analog_DAC1_A7 = analog1_DAC1_A7, IO_IS = analogDAC1A[7]
    PORT    analog_DAC1_A8 = analog1_DAC1_A8, IO_IS = analogDAC1A[8]
    PORT    analog_DAC1_A9 = analog1_DAC1_A9, IO_IS = analogDAC1A[9]
    PORT    analog_DAC1_A10 = analog1_DAC1_A10, IO_IS = analogDAC1A[10]
    PORT    analog_DAC1_A11 = analog1_DAC1_A11, IO_IS = analogDAC1A[11]
    PORT    analog_DAC1_A12 = analog1_DAC1_A12, IO_IS = analogDAC1A[12]
    PORT    analog_DAC1_A13 = analog1_DAC1_A13, IO_IS = analogDAC1A[13]

    PORT    analog_DAC1_B0 = analog1_DAC1_B0, IO_IS = analogDAC1B[0]
    PORT    analog_DAC1_B1 = analog1_DAC1_B1, IO_IS = analogDAC1B[1]
    PORT    analog_DAC1_B2 = analog1_DAC1_B2, IO_IS = analogDAC1B[2]
    PORT    analog_DAC1_B3 = analog1_DAC1_B3, IO_IS = analogDAC1B[3]
    PORT    analog_DAC1_B4 = analog1_DAC1_B4, IO_IS = analogDAC1B[4]
    PORT    analog_DAC1_B5 = analog1_DAC1_B5, IO_IS = analogDAC1B[5]
    PORT    analog_DAC1_B6 = analog1_DAC1_B6, IO_IS = analogDAC1B[6]
    PORT    analog_DAC1_B7 = analog1_DAC1_B7, IO_IS = analogDAC1B[7]
    PORT    analog_DAC1_B8 = analog1_DAC1_B8, IO_IS = analogDAC1B[8]
    PORT    analog_DAC1_B9 = analog1_DAC1_B9, IO_IS = analogDAC1B[9]
    PORT    analog_DAC1_B10 = analog1_DAC1_B10, IO_IS = analogDAC1B[10]
    PORT    analog_DAC1_B11 = analog1_DAC1_B11, IO_IS = analogDAC1B[11]
    PORT    analog_DAC1_B12 = analog1_DAC1_B12, IO_IS = analogDAC1B[12]
    PORT    analog_DAC1_B13 = analog1_DAC1_B13, IO_IS = analogDAC1B[13]

    PORT    analog_DAC2_A0 = analog1_DAC2_A0, IO_IS = analogDAC2A[0]
    PORT    analog_DAC2_A1 = analog1_DAC2_A1, IO_IS = analogDAC2A[1]
    PORT    analog_DAC2_A2 = analog1_DAC2_A2, IO_IS = analogDAC2A[2]
    PORT    analog_DAC2_A3 = analog1_DAC2_A3, IO_IS = analogDAC2A[3]
    PORT    analog_DAC2_A4 = analog1_DAC2_A4, IO_IS = analogDAC2A[4]
    PORT    analog_DAC2_A5 = analog1_DAC2_A5, IO_IS = analogDAC2A[5]
    PORT    analog_DAC2_A6 = analog1_DAC2_A6, IO_IS = analogDAC2A[6]
    PORT    analog_DAC2_A7 = analog1_DAC2_A7, IO_IS = analogDAC2A[7]
    PORT    analog_DAC2_A8 = analog1_DAC2_A8, IO_IS = analogDAC2A[8]
    PORT    analog_DAC2_A9 = analog1_DAC2_A9, IO_IS = analogDAC2A[9]
    PORT    analog_DAC2_A10 = analog1_DAC2_A10, IO_IS = analogDAC2A[10]
    PORT    analog_DAC2_A11 = analog1_DAC2_A11, IO_IS = analogDAC2A[11]
    PORT    analog_DAC2_A12 = analog1_DAC2_A12, IO_IS = analogDAC2A[12]
    PORT    analog_DAC2_A13 = analog1_DAC2_A13, IO_IS = analogDAC2A[13]

    PORT    analog_DAC2_B0 = analog1_DAC2_B0, IO_IS = analogDAC2B[0]
    PORT    analog_DAC2_B1 = analog1_DAC2_B1, IO_IS = analogDAC2B[1]
    PORT    analog_DAC2_B2 = analog1_DAC2_B2, IO_IS = analogDAC2B[2]
    PORT    analog_DAC2_B3 = analog1_DAC2_B3, IO_IS = analogDAC2B[3]
    PORT    analog_DAC2_B4 = analog1_DAC2_B4, IO_IS = analogDAC2B[4]
    PORT    analog_DAC2_B5 = analog1_DAC2_B5, IO_IS = analogDAC2B[5]
    PORT    analog_DAC2_B6 = analog1_DAC2_B6, IO_IS = analogDAC2B[6]
    PORT    analog_DAC2_B7 = analog1_DAC2_B7, IO_IS = analogDAC2B[7]
    PORT    analog_DAC2_B8 = analog1_DAC2_B8, IO_IS = analogDAC2B[8]
    PORT    analog_DAC2_B9 = analog1_DAC2_B9, IO_IS = analogDAC2B[9]
    PORT    analog_DAC2_B10 = analog1_DAC2_B10, IO_IS = analogDAC2B[10]
    PORT    analog_DAC2_B11 = analog1_DAC2_B11, IO_IS = analogDAC2B[11]
    PORT    analog_DAC2_B12 = analog1_DAC2_B12, IO_IS = analogDAC2B[12]
    PORT    analog_DAC2_B13 = analog1_DAC2_B13, IO_IS = analogDAC2B[13]

    PORT    analog_DAC1_sleep = analog1_DAC1_sleep
    PORT    analog_DAC2_sleep = analog1_DAC2_sleep

    PORT    analog_ADC_A0 = analog1_ADC_A0, IO_IS = analogADCA[0]
    PORT    analog_ADC_A1 = analog1_ADC_A1, IO_IS = analogADCA[1]
    PORT    analog_ADC_A2 = analog1_ADC_A2, IO_IS = analogADCA[2]
    PORT    analog_ADC_A3 = analog1_ADC_A3, IO_IS = analogADCA[3]
    PORT    analog_ADC_A4 = analog1_ADC_A4, IO_IS = analogADCA[4]
    PORT    analog_ADC_A5 = analog1_ADC_A5, IO_IS = analogADCA[5]
    PORT    analog_ADC_A6 = analog1_ADC_A6, IO_IS = analogADCA[6]
    PORT    analog_ADC_A7 = analog1_ADC_A7, IO_IS = analogADCA[7]
    PORT    analog_ADC_A8 = analog1_ADC_A8, IO_IS = analogADCA[8]
    PORT    analog_ADC_A9 = analog1_ADC_A9, IO_IS = analogADCA[9]
    PORT    analog_ADC_A10 = analog1_ADC_A10, IO_IS = analogADCA[10]
    PORT    analog_ADC_A11 = analog1_ADC_A11, IO_IS = analogADCA[11]
    PORT    analog_ADC_A12 = analog1_ADC_A12, IO_IS = analogADCA[12]
    PORT    analog_ADC_A13 = analog1_ADC_A13, IO_IS = analogADCA[13]

    PORT    analog_ADC_B0 = analog1_ADC_B0, IO_IS = analogADCB[0]
    PORT    analog_ADC_B1 = analog1_ADC_B1, IO_IS = analogADCB[1]
    PORT    analog_ADC_B2 = analog1_ADC_B2, IO_IS = analogADCB[2]
    PORT    analog_ADC_B3 = analog1_ADC_B3, IO_IS = analogADCB[3]
    PORT    analog_ADC_B4 = analog1_ADC_B4, IO_IS = analogADCB[4]
    PORT    analog_ADC_B5 = analog1_ADC_B5, IO_IS = analogADCB[5]
    PORT    analog_ADC_B6 = analog1_ADC_B6, IO_IS = analogADCB[6]
    PORT    analog_ADC_B7 = analog1_ADC_B7, IO_IS = analogADCB[7]
    PORT    analog_ADC_B8 = analog1_ADC_B8, IO_IS = analogADCB[8]
    PORT    analog_ADC_B9 = analog1_ADC_B9, IO_IS = analogADCB[9]
    PORT    analog_ADC_B10 = analog1_ADC_B10, IO_IS = analogADCB[10]
    PORT    analog_ADC_B11 = analog1_ADC_B11, IO_IS = analogADCB[11]
    PORT    analog_ADC_B12 = analog1_ADC_B12, IO_IS = analogADCB[12]
    PORT    analog_ADC_B13 = analog1_ADC_B13, IO_IS = analogADCB[13]

    PORT    analog_ADC_DFS = analog1_ADC_DFS
    PORT    analog_ADC_DCS = analog1_ADC_DCS
    PORT    analog_ADC_pdwnA = analog1_ADC_pdwnA
    PORT    analog_ADC_pdwnB = analog1_ADC_pdwnB
    PORT    analog_ADC_otrA = analog1_ADC_otrA
    PORT    analog_ADC_otrB = analog1_ADC_otrB
    
    PORT    analog_LED0 = analog1_LED0, IO_IS = analogLED[0]
    PORT    analog_LED1 = analog1_LED1, IO_IS = analogLED[1]
    PORT    analog_LED2 = analog1_LED2, IO_IS = analogLED[2]
    
END

#Analog Bridge for Slot 2
BEGIN IO_INTERFACE
    ATTRIBUTE IOTYPE = WARP_ANALOGBRIDGE_V1
    ATTRIBUTE INSTANCE = analog_bridge_slot_2
    ATTRIBUTE EXCLUSIVE = slot2
    ATTRIBUTE ALERT = 'Enable this peripheral only if a analog board is mounted in daughtercard slot 2.'
    
    PORT    clock_out = analog2_clock_out

    PORT    analog_DAC1_A0 = analog2_DAC1_A0, IO_IS = analogDAC1A[0]
    PORT    analog_DAC1_A1 = analog2_DAC1_A1, IO_IS = analogDAC1A[1]
    PORT    analog_DAC1_A2 = analog2_DAC1_A2, IO_IS = analogDAC1A[2]
    PORT    analog_DAC1_A3 = analog2_DAC1_A3, IO_IS = analogDAC1A[3]
    PORT    analog_DAC1_A4 = analog2_DAC1_A4, IO_IS = analogDAC1A[4]
    PORT    analog_DAC1_A5 = analog2_DAC1_A5, IO_IS = analogDAC1A[5]
    PORT    analog_DAC1_A6 = analog2_DAC1_A6, IO_IS = analogDAC1A[6]
    PORT    analog_DAC1_A7 = analog2_DAC1_A7, IO_IS = analogDAC1A[7]
    PORT    analog_DAC1_A8 = analog2_DAC1_A8, IO_IS = analogDAC1A[8]
    PORT    analog_DAC1_A9 = analog2_DAC1_A9, IO_IS = analogDAC1A[9]
    PORT    analog_DAC1_A10 = analog2_DAC1_A10, IO_IS = analogDAC1A[10]
    PORT    analog_DAC1_A11 = analog2_DAC1_A11, IO_IS = analogDAC1A[11]
    PORT    analog_DAC1_A12 = analog2_DAC1_A12, IO_IS = analogDAC1A[12]
    PORT    analog_DAC1_A13 = analog2_DAC1_A13, IO_IS = analogDAC1A[13]

    PORT    analog_DAC1_B0 = analog2_DAC1_B0, IO_IS = analogDAC1B[0]
    PORT    analog_DAC1_B1 = analog2_DAC1_B1, IO_IS = analogDAC1B[1]
    PORT    analog_DAC1_B2 = analog2_DAC1_B2, IO_IS = analogDAC1B[2]
    PORT    analog_DAC1_B3 = analog2_DAC1_B3, IO_IS = analogDAC1B[3]
    PORT    analog_DAC1_B4 = analog2_DAC1_B4, IO_IS = analogDAC1B[4]
    PORT    analog_DAC1_B5 = analog2_DAC1_B5, IO_IS = analogDAC1B[5]
    PORT    analog_DAC1_B6 = analog2_DAC1_B6, IO_IS = analogDAC1B[6]
    PORT    analog_DAC1_B7 = analog2_DAC1_B7, IO_IS = analogDAC1B[7]
    PORT    analog_DAC1_B8 = analog2_DAC1_B8, IO_IS = analogDAC1B[8]
    PORT    analog_DAC1_B9 = analog2_DAC1_B9, IO_IS = analogDAC1B[9]
    PORT    analog_DAC1_B10 = analog2_DAC1_B10, IO_IS = analogDAC1B[10]
    PORT    analog_DAC1_B11 = analog2_DAC1_B11, IO_IS = analogDAC1B[11]
    PORT    analog_DAC1_B12 = analog2_DAC1_B12, IO_IS = analogDAC1B[12]
    PORT    analog_DAC1_B13 = analog2_DAC1_B13, IO_IS = analogDAC1B[13]

    PORT    analog_DAC2_A0 = analog2_DAC2_A0, IO_IS = analogDAC2A[0]
    PORT    analog_DAC2_A1 = analog2_DAC2_A1, IO_IS = analogDAC2A[1]
    PORT    analog_DAC2_A2 = analog2_DAC2_A2, IO_IS = analogDAC2A[2]
    PORT    analog_DAC2_A3 = analog2_DAC2_A3, IO_IS = analogDAC2A[3]
    PORT    analog_DAC2_A4 = analog2_DAC2_A4, IO_IS = analogDAC2A[4]
    PORT    analog_DAC2_A5 = analog2_DAC2_A5, IO_IS = analogDAC2A[5]
    PORT    analog_DAC2_A6 = analog2_DAC2_A6, IO_IS = analogDAC2A[6]
    PORT    analog_DAC2_A7 = analog2_DAC2_A7, IO_IS = analogDAC2A[7]
    PORT    analog_DAC2_A8 = analog2_DAC2_A8, IO_IS = analogDAC2A[8]
    PORT    analog_DAC2_A9 = analog2_DAC2_A9, IO_IS = analogDAC2A[9]
    PORT    analog_DAC2_A10 = analog2_DAC2_A10, IO_IS = analogDAC2A[10]
    PORT    analog_DAC2_A11 = analog2_DAC2_A11, IO_IS = analogDAC2A[11]
    PORT    analog_DAC2_A12 = analog2_DAC2_A12, IO_IS = analogDAC2A[12]
    PORT    analog_DAC2_A13 = analog2_DAC2_A13, IO_IS = analogDAC2A[13]

    PORT    analog_DAC2_B0 = analog2_DAC2_B0, IO_IS = analogDAC2B[0]
    PORT    analog_DAC2_B1 = analog2_DAC2_B1, IO_IS = analogDAC2B[1]
    PORT    analog_DAC2_B2 = analog2_DAC2_B2, IO_IS = analogDAC2B[2]
    PORT    analog_DAC2_B3 = analog2_DAC2_B3, IO_IS = analogDAC2B[3]
    PORT    analog_DAC2_B4 = analog2_DAC2_B4, IO_IS = analogDAC2B[4]
    PORT    analog_DAC2_B5 = analog2_DAC2_B5, IO_IS = analogDAC2B[5]
    PORT    analog_DAC2_B6 = analog2_DAC2_B6, IO_IS = analogDAC2B[6]
    PORT    analog_DAC2_B7 = analog2_DAC2_B7, IO_IS = analogDAC2B[7]
    PORT    analog_DAC2_B8 = analog2_DAC2_B8, IO_IS = analogDAC2B[8]
    PORT    analog_DAC2_B9 = analog2_DAC2_B9, IO_IS = analogDAC2B[9]
    PORT    analog_DAC2_B10 = analog2_DAC2_B10, IO_IS = analogDAC2B[10]
    PORT    analog_DAC2_B11 = analog2_DAC2_B11, IO_IS = analogDAC2B[11]
    PORT    analog_DAC2_B12 = analog2_DAC2_B12, IO_IS = analogDAC2B[12]
    PORT    analog_DAC2_B13 = analog2_DAC2_B13, IO_IS = analogDAC2B[13]

    PORT    analog_DAC1_sleep = analog2_DAC1_sleep
    PORT    analog_DAC2_sleep = analog2_DAC2_sleep

    PORT    analog_ADC_A0 = analog2_ADC_A0, IO_IS = analogADCA[0]
    PORT    analog_ADC_A1 = analog2_ADC_A1, IO_IS = analogADCA[1]
    PORT    analog_ADC_A2 = analog2_ADC_A2, IO_IS = analogADCA[2]
    PORT    analog_ADC_A3 = analog2_ADC_A3, IO_IS = analogADCA[3]
    PORT    analog_ADC_A4 = analog2_ADC_A4, IO_IS = analogADCA[4]
    PORT    analog_ADC_A5 = analog2_ADC_A5, IO_IS = analogADCA[5]
    PORT    analog_ADC_A6 = analog2_ADC_A6, IO_IS = analogADCA[6]
    PORT    analog_ADC_A7 = analog2_ADC_A7, IO_IS = analogADCA[7]
    PORT    analog_ADC_A8 = analog2_ADC_A8, IO_IS = analogADCA[8]
    PORT    analog_ADC_A9 = analog2_ADC_A9, IO_IS = analogADCA[9]
    PORT    analog_ADC_A10 = analog2_ADC_A10, IO_IS = analogADCA[10]
    PORT    analog_ADC_A11 = analog2_ADC_A11, IO_IS = analogADCA[11]
    PORT    analog_ADC_A12 = analog2_ADC_A12, IO_IS = analogADCA[12]
    PORT    analog_ADC_A13 = analog2_ADC_A13, IO_IS = analogADCA[13]

    PORT    analog_ADC_B0 = analog2_ADC_B0, IO_IS = analogADCB[0]
    PORT    analog_ADC_B1 = analog2_ADC_B1, IO_IS = analogADCB[1]
    PORT    analog_ADC_B2 = analog2_ADC_B2, IO_IS = analogADCB[2]
    PORT    analog_ADC_B3 = analog2_ADC_B3, IO_IS = analogADCB[3]
    PORT    analog_ADC_B4 = analog2_ADC_B4, IO_IS = analogADCB[4]
    PORT    analog_ADC_B5 = analog2_ADC_B5, IO_IS = analogADCB[5]
    PORT    analog_ADC_B6 = analog2_ADC_B6, IO_IS = analogADCB[6]
    PORT    analog_ADC_B7 = analog2_ADC_B7, IO_IS = analogADCB[7]
    PORT    analog_ADC_B8 = analog2_ADC_B8, IO_IS = analogADCB[8]
    PORT    analog_ADC_B9 = analog2_ADC_B9, IO_IS = analogADCB[9]
    PORT    analog_ADC_B10 = analog2_ADC_B10, IO_IS = analogADCB[10]
    PORT    analog_ADC_B11 = analog2_ADC_B11, IO_IS = analogADCB[11]
    PORT    analog_ADC_B12 = analog2_ADC_B12, IO_IS = analogADCB[12]
    PORT    analog_ADC_B13 = analog2_ADC_B13, IO_IS = analogADCB[13]

    PORT    analog_ADC_DFS = analog2_ADC_DFS
    PORT    analog_ADC_DCS = analog2_ADC_DCS
    PORT    analog_ADC_pdwnA = analog2_ADC_pdwnA
    PORT    analog_ADC_pdwnB = analog2_ADC_pdwnB
    PORT    analog_ADC_otrA = analog2_ADC_otrA
    PORT    analog_ADC_otrB = analog2_ADC_otrB
    
    PORT    analog_LED0 = analog2_LED0, IO_IS = analogLED[0]
    PORT    analog_LED1 = analog2_LED1, IO_IS = analogLED[1]
    PORT    analog_LED2 = analog2_LED2, IO_IS = analogLED[2]
    
END

#Analog Bridge for Slot 3
BEGIN IO_INTERFACE
    ATTRIBUTE IOTYPE = WARP_ANALOGBRIDGE_V1
    ATTRIBUTE INSTANCE = analog_bridge_slot_3
    ATTRIBUTE EXCLUSIVE = slot3
    ATTRIBUTE ALERT = 'Enable this peripheral only if a analog board is mounted in daughtercard slot 3.'
    
    PORT    clock_out = analog3_clock_out

    PORT    analog_DAC1_A0 = analog3_DAC1_A0, IO_IS = analogDAC1A[0]
    PORT    analog_DAC1_A1 = analog3_DAC1_A1, IO_IS = analogDAC1A[1]
    PORT    analog_DAC1_A2 = analog3_DAC1_A2, IO_IS = analogDAC1A[2]
    PORT    analog_DAC1_A3 = analog3_DAC1_A3, IO_IS = analogDAC1A[3]
    PORT    analog_DAC1_A4 = analog3_DAC1_A4, IO_IS = analogDAC1A[4]
    PORT    analog_DAC1_A5 = analog3_DAC1_A5, IO_IS = analogDAC1A[5]
    PORT    analog_DAC1_A6 = analog3_DAC1_A6, IO_IS = analogDAC1A[6]
    PORT    analog_DAC1_A7 = analog3_DAC1_A7, IO_IS = analogDAC1A[7]
    PORT    analog_DAC1_A8 = analog3_DAC1_A8, IO_IS = analogDAC1A[8]
    PORT    analog_DAC1_A9 = analog3_DAC1_A9, IO_IS = analogDAC1A[9]
    PORT    analog_DAC1_A10 = analog3_DAC1_A10, IO_IS = analogDAC1A[10]
    PORT    analog_DAC1_A11 = analog3_DAC1_A11, IO_IS = analogDAC1A[11]
    PORT    analog_DAC1_A12 = analog3_DAC1_A12, IO_IS = analogDAC1A[12]
    PORT    analog_DAC1_A13 = analog3_DAC1_A13, IO_IS = analogDAC1A[13]

    PORT    analog_DAC1_B0 = analog3_DAC1_B0, IO_IS = analogDAC1B[0]
    PORT    analog_DAC1_B1 = analog3_DAC1_B1, IO_IS = analogDAC1B[1]
    PORT    analog_DAC1_B2 = analog3_DAC1_B2, IO_IS = analogDAC1B[2]
    PORT    analog_DAC1_B3 = analog3_DAC1_B3, IO_IS = analogDAC1B[3]
    PORT    analog_DAC1_B4 = analog3_DAC1_B4, IO_IS = analogDAC1B[4]
    PORT    analog_DAC1_B5 = analog3_DAC1_B5, IO_IS = analogDAC1B[5]
    PORT    analog_DAC1_B6 = analog3_DAC1_B6, IO_IS = analogDAC1B[6]
    PORT    analog_DAC1_B7 = analog3_DAC1_B7, IO_IS = analogDAC1B[7]
    PORT    analog_DAC1_B8 = analog3_DAC1_B8, IO_IS = analogDAC1B[8]
    PORT    analog_DAC1_B9 = analog3_DAC1_B9, IO_IS = analogDAC1B[9]
    PORT    analog_DAC1_B10 = analog3_DAC1_B10, IO_IS = analogDAC1B[10]
    PORT    analog_DAC1_B11 = analog3_DAC1_B11, IO_IS = analogDAC1B[11]
    PORT    analog_DAC1_B12 = analog3_DAC1_B12, IO_IS = analogDAC1B[12]
    PORT    analog_DAC1_B13 = analog3_DAC1_B13, IO_IS = analogDAC1B[13]

    PORT    analog_DAC2_A0 = analog3_DAC2_A0, IO_IS = analogDAC2A[0]
    PORT    analog_DAC2_A1 = analog3_DAC2_A1, IO_IS = analogDAC2A[1]
    PORT    analog_DAC2_A2 = analog3_DAC2_A2, IO_IS = analogDAC2A[2]
    PORT    analog_DAC2_A3 = analog3_DAC2_A3, IO_IS = analogDAC2A[3]
    PORT    analog_DAC2_A4 = analog3_DAC2_A4, IO_IS = analogDAC2A[4]
    PORT    analog_DAC2_A5 = analog3_DAC2_A5, IO_IS = analogDAC2A[5]
    PORT    analog_DAC2_A6 = analog3_DAC2_A6, IO_IS = analogDAC2A[6]
    PORT    analog_DAC2_A7 = analog3_DAC2_A7, IO_IS = analogDAC2A[7]
    PORT    analog_DAC2_A8 = analog3_DAC2_A8, IO_IS = analogDAC2A[8]
    PORT    analog_DAC2_A9 = analog3_DAC2_A9, IO_IS = analogDAC2A[9]
    PORT    analog_DAC2_A10 = analog3_DAC2_A10, IO_IS = analogDAC2A[10]
    PORT    analog_DAC2_A11 = analog3_DAC2_A11, IO_IS = analogDAC2A[11]
    PORT    analog_DAC2_A12 = analog3_DAC2_A12, IO_IS = analogDAC2A[12]
    PORT    analog_DAC2_A13 = analog3_DAC2_A13, IO_IS = analogDAC2A[13]

    PORT    analog_DAC2_B0 = analog3_DAC2_B0, IO_IS = analogDAC2B[0]
    PORT    analog_DAC2_B1 = analog3_DAC2_B1, IO_IS = analogDAC2B[1]
    PORT    analog_DAC2_B2 = analog3_DAC2_B2, IO_IS = analogDAC2B[2]
    PORT    analog_DAC2_B3 = analog3_DAC2_B3, IO_IS = analogDAC2B[3]
    PORT    analog_DAC2_B4 = analog3_DAC2_B4, IO_IS = analogDAC2B[4]
    PORT    analog_DAC2_B5 = analog3_DAC2_B5, IO_IS = analogDAC2B[5]
    PORT    analog_DAC2_B6 = analog3_DAC2_B6, IO_IS = analogDAC2B[6]
    PORT    analog_DAC2_B7 = analog3_DAC2_B7, IO_IS = analogDAC2B[7]
    PORT    analog_DAC2_B8 = analog3_DAC2_B8, IO_IS = analogDAC2B[8]
    PORT    analog_DAC2_B9 = analog3_DAC2_B9, IO_IS = analogDAC2B[9]
    PORT    analog_DAC2_B10 = analog3_DAC2_B10, IO_IS = analogDAC2B[10]
    PORT    analog_DAC2_B11 = analog3_DAC2_B11, IO_IS = analogDAC2B[11]
    PORT    analog_DAC2_B12 = analog3_DAC2_B12, IO_IS = analogDAC2B[12]
    PORT    analog_DAC2_B13 = analog3_DAC2_B13, IO_IS = analogDAC2B[13]

    PORT    analog_DAC1_sleep = analog3_DAC1_sleep
    PORT    analog_DAC2_sleep = analog3_DAC2_sleep

    PORT    analog_ADC_A0 = analog3_ADC_A0, IO_IS = analogADCA[0]
    PORT    analog_ADC_A1 = analog3_ADC_A1, IO_IS = analogADCA[1]
    PORT    analog_ADC_A2 = analog3_ADC_A2, IO_IS = analogADCA[2]
    PORT    analog_ADC_A3 = analog3_ADC_A3, IO_IS = analogADCA[3]
    PORT    analog_ADC_A4 = analog3_ADC_A4, IO_IS = analogADCA[4]
    PORT    analog_ADC_A5 = analog3_ADC_A5, IO_IS = analogADCA[5]
    PORT    analog_ADC_A6 = analog3_ADC_A6, IO_IS = analogADCA[6]
    PORT    analog_ADC_A7 = analog3_ADC_A7, IO_IS = analogADCA[7]
    PORT    analog_ADC_A8 = analog3_ADC_A8, IO_IS = analogADCA[8]
    PORT    analog_ADC_A9 = analog3_ADC_A9, IO_IS = analogADCA[9]
    PORT    analog_ADC_A10 = analog3_ADC_A10, IO_IS = analogADCA[10]
    PORT    analog_ADC_A11 = analog3_ADC_A11, IO_IS = analogADCA[11]
    PORT    analog_ADC_A12 = analog3_ADC_A12, IO_IS = analogADCA[12]
    PORT    analog_ADC_A13 = analog3_ADC_A13, IO_IS = analogADCA[13]

    PORT    analog_ADC_B0 = analog3_ADC_B0, IO_IS = analogADCB[0]
    PORT    analog_ADC_B1 = analog3_ADC_B1, IO_IS = analogADCB[1]
    PORT    analog_ADC_B2 = analog3_ADC_B2, IO_IS = analogADCB[2]
    PORT    analog_ADC_B3 = analog3_ADC_B3, IO_IS = analogADCB[3]
    PORT    analog_ADC_B4 = analog3_ADC_B4, IO_IS = analogADCB[4]
    PORT    analog_ADC_B5 = analog3_ADC_B5, IO_IS = analogADCB[5]
    PORT    analog_ADC_B6 = analog3_ADC_B6, IO_IS = analogADCB[6]
    PORT    analog_ADC_B7 = analog3_ADC_B7, IO_IS = analogADCB[7]
    PORT    analog_ADC_B8 = analog3_ADC_B8, IO_IS = analogADCB[8]
    PORT    analog_ADC_B9 = analog3_ADC_B9, IO_IS = analogADCB[9]
    PORT    analog_ADC_B10 = analog3_ADC_B10, IO_IS = analogADCB[10]
    PORT    analog_ADC_B11 = analog3_ADC_B11, IO_IS = analogADCB[11]
    PORT    analog_ADC_B12 = analog3_ADC_B12, IO_IS = analogADCB[12]
    PORT    analog_ADC_B13 = analog3_ADC_B13, IO_IS = analogADCB[13]

    PORT    analog_ADC_DFS = analog3_ADC_DFS
    PORT    analog_ADC_DCS = analog3_ADC_DCS
    PORT    analog_ADC_pdwnA = analog3_ADC_pdwnA
    PORT    analog_ADC_pdwnB = analog3_ADC_pdwnB
    PORT    analog_ADC_otrA = analog3_ADC_otrA
    PORT    analog_ADC_otrB = analog3_ADC_otrB
    
    PORT    analog_LED0 = analog3_LED0, IO_IS = analogLED[0]
    PORT    analog_LED1 = analog3_LED1, IO_IS = analogLED[1]
    PORT    analog_LED2 = analog3_LED2, IO_IS = analogLED[2]
    
END

#Analog Bridge for Slot 4
BEGIN IO_INTERFACE
    ATTRIBUTE IOTYPE = WARP_ANALOGBRIDGE_V1
    ATTRIBUTE INSTANCE = analog_bridge_slot_4
    ATTRIBUTE EXCLUSIVE = slot4
    ATTRIBUTE ALERT = 'Enable this peripheral only if a analog board is mounted in daughtercard slot 4.'
    
    PORT    clock_out = analog4_clock_out

    PORT    analog_DAC1_A0 = analog4_DAC1_A0, IO_IS = analogDAC1A[0]
    PORT    analog_DAC1_A1 = analog4_DAC1_A1, IO_IS = analogDAC1A[1]
    PORT    analog_DAC1_A2 = analog4_DAC1_A2, IO_IS = analogDAC1A[2]
    PORT    analog_DAC1_A3 = analog4_DAC1_A3, IO_IS = analogDAC1A[3]
    PORT    analog_DAC1_A4 = analog4_DAC1_A4, IO_IS = analogDAC1A[4]
    PORT    analog_DAC1_A5 = analog4_DAC1_A5, IO_IS = analogDAC1A[5]
    PORT    analog_DAC1_A6 = analog4_DAC1_A6, IO_IS = analogDAC1A[6]
    PORT    analog_DAC1_A7 = analog4_DAC1_A7, IO_IS = analogDAC1A[7]
    PORT    analog_DAC1_A8 = analog4_DAC1_A8, IO_IS = analogDAC1A[8]
    PORT    analog_DAC1_A9 = analog4_DAC1_A9, IO_IS = analogDAC1A[9]
    PORT    analog_DAC1_A10 = analog4_DAC1_A10, IO_IS = analogDAC1A[10]
    PORT    analog_DAC1_A11 = analog4_DAC1_A11, IO_IS = analogDAC1A[11]
    PORT    analog_DAC1_A12 = analog4_DAC1_A12, IO_IS = analogDAC1A[12]
    PORT    analog_DAC1_A13 = analog4_DAC1_A13, IO_IS = analogDAC1A[13]

    PORT    analog_DAC1_B0 = analog4_DAC1_B0, IO_IS = analogDAC1B[0]
    PORT    analog_DAC1_B1 = analog4_DAC1_B1, IO_IS = analogDAC1B[1]
    PORT    analog_DAC1_B2 = analog4_DAC1_B2, IO_IS = analogDAC1B[2]
    PORT    analog_DAC1_B3 = analog4_DAC1_B3, IO_IS = analogDAC1B[3]
    PORT    analog_DAC1_B4 = analog4_DAC1_B4, IO_IS = analogDAC1B[4]
    PORT    analog_DAC1_B5 = analog4_DAC1_B5, IO_IS = analogDAC1B[5]
    PORT    analog_DAC1_B6 = analog4_DAC1_B6, IO_IS = analogDAC1B[6]
    PORT    analog_DAC1_B7 = analog4_DAC1_B7, IO_IS = analogDAC1B[7]
    PORT    analog_DAC1_B8 = analog4_DAC1_B8, IO_IS = analogDAC1B[8]
    PORT    analog_DAC1_B9 = analog4_DAC1_B9, IO_IS = analogDAC1B[9]
    PORT    analog_DAC1_B10 = analog4_DAC1_B10, IO_IS = analogDAC1B[10]
    PORT    analog_DAC1_B11 = analog4_DAC1_B11, IO_IS = analogDAC1B[11]
    PORT    analog_DAC1_B12 = analog4_DAC1_B12, IO_IS = analogDAC1B[12]
    PORT    analog_DAC1_B13 = analog4_DAC1_B13, IO_IS = analogDAC1B[13]

    PORT    analog_DAC2_A0 = analog4_DAC2_A0, IO_IS = analogDAC2A[0]
    PORT    analog_DAC2_A1 = analog4_DAC2_A1, IO_IS = analogDAC2A[1]
    PORT    analog_DAC2_A2 = analog4_DAC2_A2, IO_IS = analogDAC2A[2]
    PORT    analog_DAC2_A3 = analog4_DAC2_A3, IO_IS = analogDAC2A[3]
    PORT    analog_DAC2_A4 = analog4_DAC2_A4, IO_IS = analogDAC2A[4]
    PORT    analog_DAC2_A5 = analog4_DAC2_A5, IO_IS = analogDAC2A[5]
    PORT    analog_DAC2_A6 = analog4_DAC2_A6, IO_IS = analogDAC2A[6]
    PORT    analog_DAC2_A7 = analog4_DAC2_A7, IO_IS = analogDAC2A[7]
    PORT    analog_DAC2_A8 = analog4_DAC2_A8, IO_IS = analogDAC2A[8]
    PORT    analog_DAC2_A9 = analog4_DAC2_A9, IO_IS = analogDAC2A[9]
    PORT    analog_DAC2_A10 = analog4_DAC2_A10, IO_IS = analogDAC2A[10]
    PORT    analog_DAC2_A11 = analog4_DAC2_A11, IO_IS = analogDAC2A[11]
    PORT    analog_DAC2_A12 = analog4_DAC2_A12, IO_IS = analogDAC2A[12]
    PORT    analog_DAC2_A13 = analog4_DAC2_A13, IO_IS = analogDAC2A[13]

    PORT    analog_DAC2_B0 = analog4_DAC2_B0, IO_IS = analogDAC2B[0]
    PORT    analog_DAC2_B1 = analog4_DAC2_B1, IO_IS = analogDAC2B[1]
    PORT    analog_DAC2_B2 = analog4_DAC2_B2, IO_IS = analogDAC2B[2]
    PORT    analog_DAC2_B3 = analog4_DAC2_B3, IO_IS = analogDAC2B[3]
    PORT    analog_DAC2_B4 = analog4_DAC2_B4, IO_IS = analogDAC2B[4]
    PORT    analog_DAC2_B5 = analog4_DAC2_B5, IO_IS = analogDAC2B[5]
    PORT    analog_DAC2_B6 = analog4_DAC2_B6, IO_IS = analogDAC2B[6]
    PORT    analog_DAC2_B7 = analog4_DAC2_B7, IO_IS = analogDAC2B[7]
    PORT    analog_DAC2_B8 = analog4_DAC2_B8, IO_IS = analogDAC2B[8]
    PORT    analog_DAC2_B9 = analog4_DAC2_B9, IO_IS = analogDAC2B[9]
    PORT    analog_DAC2_B10 = analog4_DAC2_B10, IO_IS = analogDAC2B[10]
    PORT    analog_DAC2_B11 = analog4_DAC2_B11, IO_IS = analogDAC2B[11]
    PORT    analog_DAC2_B12 = analog4_DAC2_B12, IO_IS = analogDAC2B[12]
    PORT    analog_DAC2_B13 = analog4_DAC2_B13, IO_IS = analogDAC2B[13]

    PORT    analog_DAC1_sleep = analog4_DAC1_sleep
    PORT    analog_DAC2_sleep = analog4_DAC2_sleep

    PORT    analog_ADC_A0 = analog4_ADC_A0, IO_IS = analogADCA[0]
    PORT    analog_ADC_A1 = analog4_ADC_A1, IO_IS = analogADCA[1]
    PORT    analog_ADC_A2 = analog4_ADC_A2, IO_IS = analogADCA[2]
    PORT    analog_ADC_A3 = analog4_ADC_A3, IO_IS = analogADCA[3]
    PORT    analog_ADC_A4 = analog4_ADC_A4, IO_IS = analogADCA[4]
    PORT    analog_ADC_A5 = analog4_ADC_A5, IO_IS = analogADCA[5]
    PORT    analog_ADC_A6 = analog4_ADC_A6, IO_IS = analogADCA[6]
    PORT    analog_ADC_A7 = analog4_ADC_A7, IO_IS = analogADCA[7]
    PORT    analog_ADC_A8 = analog4_ADC_A8, IO_IS = analogADCA[8]
    PORT    analog_ADC_A9 = analog4_ADC_A9, IO_IS = analogADCA[9]
    PORT    analog_ADC_A10 = analog4_ADC_A10, IO_IS = analogADCA[10]
    PORT    analog_ADC_A11 = analog4_ADC_A11, IO_IS = analogADCA[11]
    PORT    analog_ADC_A12 = analog4_ADC_A12, IO_IS = analogADCA[12]
    PORT    analog_ADC_A13 = analog4_ADC_A13, IO_IS = analogADCA[13]

    PORT    analog_ADC_B0 = analog4_ADC_B0, IO_IS = analogADCB[0]
    PORT    analog_ADC_B1 = analog4_ADC_B1, IO_IS = analogADCB[1]
    PORT    analog_ADC_B2 = analog4_ADC_B2, IO_IS = analogADCB[2]
    PORT    analog_ADC_B3 = analog4_ADC_B3, IO_IS = analogADCB[3]
    PORT    analog_ADC_B4 = analog4_ADC_B4, IO_IS = analogADCB[4]
    PORT    analog_ADC_B5 = analog4_ADC_B5, IO_IS = analogADCB[5]
    PORT    analog_ADC_B6 = analog4_ADC_B6, IO_IS = analogADCB[6]
    PORT    analog_ADC_B7 = analog4_ADC_B7, IO_IS = analogADCB[7]
    PORT    analog_ADC_B8 = analog4_ADC_B8, IO_IS = analogADCB[8]
    PORT    analog_ADC_B9 = analog4_ADC_B9, IO_IS = analogADCB[9]
    PORT    analog_ADC_B10 = analog4_ADC_B10, IO_IS = analogADCB[10]
    PORT    analog_ADC_B11 = analog4_ADC_B11, IO_IS = analogADCB[11]
    PORT    analog_ADC_B12 = analog4_ADC_B12, IO_IS = analogADCB[12]
    PORT    analog_ADC_B13 = analog4_ADC_B13, IO_IS = analogADCB[13]

    PORT    analog_ADC_DFS = analog4_ADC_DFS
    PORT    analog_ADC_DCS = analog4_ADC_DCS
    PORT    analog_ADC_pdwnA = analog4_ADC_pdwnA
    PORT    analog_ADC_pdwnB = analog4_ADC_pdwnB
    PORT    analog_ADC_otrA = analog4_ADC_otrA
    PORT    analog_ADC_otrB = analog4_ADC_otrB
    
    PORT    analog_LED0 = analog4_LED0, IO_IS = analogLED[0]
    PORT    analog_LED1 = analog4_LED1, IO_IS = analogLED[1]
    PORT    analog_LED2 = analog4_LED2, IO_IS = analogLED[2]
    
END

# One user I/O board controller handles a single board
#  The user can enabled up to four controllers (one per slot)
BEGIN IO_INTERFACE
    ATTRIBUTE IOTYPE = XIL_USERIOBOARD_V1
    ATTRIBUTE INSTANCE = user_io_board_controller_slot1
    ATTRIBUTE EXCLUSIVE = slot1

    #Hardware reset input (same as software reset)
    PORT reset = userio_board_slot1_reset, IO_IS = userio_board_reset

    #LCD SPI interface
    PORT sdi = user_ioboard_slot1_sdi, IO_IS = userio_board_sdi
    PORT scl = userio_board_slot1_scl, IO_IS = userio_board_scl
    PORT resetlcd = userio_board_slot1_resetlcd, IO_IS = userio_board_resetlcd
    PORT cs = userio_board_slot1_cs, IO_IS = userio_board_cs

    #Buzzer output
    PORT buzzer = userio_board_slot1_buzzer, IO_IS = userio_board_buzzer

    #Trackball I/O
    PORT trackball_yscn = userio_board_slot1_trackball_yscn, IO_IS = userio_board_trackball_yscn
    PORT trackball_sel1 = userio_board_slot1_trackball_sel1, IO_IS = userio_board_trackball_sel1
    PORT trackball_xscn = userio_board_slot1_trackball_xscn, IO_IS = userio_board_trackball_xscn
    PORT trackball_sel2 = userio_board_slot1_trackball_sel2, IO_IS = userio_board_trackball_sel2
    PORT trackball_oyn = userio_board_slot1_trackball_oyn, IO_IS = userio_board_trackball_oyn
    PORT trackball_oy = userio_board_slot1_trackball_oy, IO_IS = userio_board_trackball_oy
    PORT trackball_oxn = userio_board_slot1_trackball_oxn, IO_IS = userio_board_trackball_oxn
    PORT trackball_ox = userio_board_slot1_trackball_ox, IO_IS = userio_board_trackball_ox

    #Eight LEDs
    PORT leds_0 = userio_board_slot1_leds_0, IO_IS = userio_board_leds[0]
    PORT leds_1 = userio_board_slot1_leds_1, IO_IS = userio_board_leds[1]
    PORT leds_2 = userio_board_slot1_leds_2, IO_IS = userio_board_leds[2]
    PORT leds_3 = userio_board_slot1_leds_3, IO_IS = userio_board_leds[3]
    PORT leds_4 = userio_board_slot1_leds_4, IO_IS = userio_board_leds[4]
    PORT leds_5 = userio_board_slot1_leds_5, IO_IS = userio_board_leds[5]
    PORT leds_6 = userio_board_slot1_leds_6, IO_IS = userio_board_leds[6]
    PORT leds_7 = userio_board_slot1_leds_7, IO_IS = userio_board_leds[7]

    #DIP switch
    PORT dip_switch_0 = userio_board_slot1_dip_switch_0, IO_IS = userio_board_dip_switch[0]
    PORT dip_switch_1 = userio_board_slot1_dip_switch_1, IO_IS = userio_board_dip_switch[1]
    PORT dip_switch_2 = userio_board_slot1_dip_switch_2, IO_IS = userio_board_dip_switch[2]
    PORT dip_switch_3 = userio_board_slot1_dip_switch_3, IO_IS = userio_board_dip_switch[3]

    #Six small push buttons
    PORT buttons_small_0 = userio_board_slot1_buttons_small_0, IO_IS = userio_board_buttons_small[0]
    PORT buttons_small_1 = userio_board_slot1_buttons_small_1, IO_IS = userio_board_buttons_small[1]
    PORT buttons_small_2 = userio_board_slot1_buttons_small_2, IO_IS = userio_board_buttons_small[2]
    PORT buttons_small_3 = userio_board_slot1_buttons_small_3, IO_IS = userio_board_buttons_small[3]
    PORT buttons_small_4 = userio_board_slot1_buttons_small_4, IO_IS = userio_board_buttons_small[4]
    PORT buttons_small_5 = userio_board_slot1_buttons_small_5, IO_IS = userio_board_buttons_small[5]

    #Two big push buttons
    PORT buttons_big_0 = userio_board_slot1_buttons_big_0, IO_IS = userio_board_buttons_big[0]
    PORT buttons_big_1 = userio_board_slot1_buttons_big_1, IO_IS = userio_board_buttons_big[1]
END

BEGIN IO_INTERFACE
    ATTRIBUTE IOTYPE = XIL_EMC_V1
    ATTRIBUTE INSTANCE = SRAM0_ZBT_512Kx32
    PARAMETER C_NUM_BANKS_MEM = 1, IO_IS=C_NUM_BANKS_MEM
    PARAMETER C_DEV_MIR_ENABLE = 0, IO_IS=C_DEV_MIR_ENABLE
    PARAMETER C_MAX_MEM_WIDTH = 32, IO_IS=C_MAX_MEM_WIDTH
    PARAMETER C_INCLUDE_NEGEDGE_IOREGS = 1, IO_IS=C_INCLUDE_NEGEDGE_IOREGS

    PARAMETER C_INCLUDE_BURST_CACHELN_SUPPORT = 1, IO_IS=C_INCLUDE_BURST_CACHELN_SUPPORT
    PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1, IO_IS=C_INCLUDE_DATAWIDTH_MATCHING_0
    PARAMETER C_MEM0_BASEADDR = 0x0, IO_IS=C_MEM0_BASEADDR, SHORT_DESC=SRAM_256Kx32
    PARAMETER C_MEM0_HIGHADDR = 0x1FFFFF, IO_IS=C_MEM0_HIGHADDR
    PARAMETER C_MEM0_WIDTH = 32, IO_IS=C_MEM0_WIDTH
    PARAMETER C_SYNCH_MEM_0 = 1, IO_IS=C_SYNCH_MEM_0
    PARAMETER C_SYNCH_PIPEDELAY_0 = 2, IO_IS=C_SYNCH_PIPEDELAY_0

    PARAMETER C_READ_ADDR_TO_OUT_SLOW_PS_0 = 0,  IO_IS = C_READ_ADDR_TO_OUT_SLOW_PS_0
    PARAMETER C_WRITE_ADDR_TO_OUT_SLOW_PS_0 = 0, IO_IS = C_WRITE_ADDR_TO_OUT_SLOW_PS_0
    PARAMETER C_WRITE_MIN_PULSE_WIDTH_PS_0 = 0,  IO_IS = C_WRITE_MIN_PULSE_WIDTH_PS_0
    PARAMETER C_READ_ADDR_TO_OUT_FAST_PS_0 = 0,  IO_IS = C_READ_ADDR_TO_OUT_FAST_PS_0
    PARAMETER C_WRITE_ADDR_TO_OUT_FAST_PS_0 = 0, IO_IS = C_WRITE_ADDR_TO_OUT_FAST_PS_0
    PARAMETER C_READ_RECOVERY_BEFORE_WRITE_PS_0 = 0, IO_IS = C_READ_RECOVERY_BEFORE_WRITE_PS_0
    PARAMETER C_WRITE_RECOVERY_BEFORE_READ_PS_0 = 0, IO_IS = C_WRITE_RECOVERY_BEFORE_READ_PS_0

    PORT A0 = CONN_SRAM0_A0, IO_IS = emc_addr[29]
    PORT A1 = CONN_SRAM0_A1, IO_IS = emc_addr[28]
    PORT A2 = CONN_SRAM0_A2, IO_IS = emc_addr[27]
    PORT A3 = CONN_SRAM0_A3, IO_IS = emc_addr[26]
    PORT A4 = CONN_SRAM0_A4, IO_IS = emc_addr[25]
    PORT A5 = CONN_SRAM0_A5, IO_IS = emc_addr[24]
    PORT A6 = CONN_SRAM0_A6, IO_IS = emc_addr[23]
    PORT A7 = CONN_SRAM0_A7, IO_IS = emc_addr[22]
    PORT A8 = CONN_SRAM0_A8, IO_IS = emc_addr[21]
    PORT A9 = CONN_SRAM0_A9, IO_IS = emc_addr[20]
    PORT A10 = CONN_SRAM0_A10, IO_IS = emc_addr[19]
    PORT A11 = CONN_SRAM0_A11, IO_IS = emc_addr[18]
    PORT A12 = CONN_SRAM0_A12, IO_IS = emc_addr[17]
    PORT A13 = CONN_SRAM0_A13, IO_IS = emc_addr[16]
    PORT A14 = CONN_SRAM0_A14, IO_IS = emc_addr[15]
    PORT A15 = CONN_SRAM0_A15, IO_IS = emc_addr[14]
    PORT A16 = CONN_SRAM0_A16, IO_IS = emc_addr[13]
    PORT A17 = CONN_SRAM0_A17, IO_IS = emc_addr[12]
    PORT A18 = CONN_SRAM0_A18, IO_IS = emc_addr[11]

    PORT BEN0 = CONN_SRAM0_BEN0, IO_IS = emc_ben[3]
    PORT BEN1 = CONN_SRAM0_BEN1, IO_IS = emc_ben[2]
    PORT BEN2 = CONN_SRAM0_BEN2, IO_IS = emc_ben[1]
    PORT BEN3 = CONN_SRAM0_BEN3, IO_IS = emc_ben[0]
    PORT WEN = CONN_SRAM0_WEN, IO_IS=emc_wen

    PORT D0 = CONN_SRAM0_D0, IO_IS = emc_data[31]
    PORT D1 = CONN_SRAM0_D1, IO_IS = emc_data[30]
    PORT D2 = CONN_SRAM0_D2, IO_IS = emc_data[29]
    PORT D3 = CONN_SRAM0_D3, IO_IS = emc_data[28]
    PORT D4 = CONN_SRAM0_D4, IO_IS = emc_data[27]
    PORT D5 = CONN_SRAM0_D5, IO_IS = emc_data[26]
    PORT D6 = CONN_SRAM0_D6,  IO_IS = emc_data[25]
    PORT D7 = CONN_SRAM0_D7, IO_IS = emc_data[24]
    PORT D8 = CONN_SRAM0_D8, IO_IS = emc_data[23]
    PORT D9 = CONN_SRAM0_D9, IO_IS = emc_data[22]
    PORT D10 = CONN_SRAM0_D10, IO_IS = emc_data[21]
    PORT D11 = CONN_SRAM0_D11, IO_IS = emc_data[20]
    PORT D12 = CONN_SRAM0_D12, IO_IS = emc_data[19]
    PORT D13 = CONN_SRAM0_D13, IO_IS = emc_data[18]
    PORT D14 = CONN_SRAM0_D14, IO_IS = emc_data[17]
    PORT D15 = CONN_SRAM0_D15, IO_IS = emc_data[16]
    PORT D16 = CONN_SRAM0_D16, IO_IS = emc_data[15]
    PORT D17 = CONN_SRAM0_D17, IO_IS = emc_data[14]
    PORT D18 = CONN_SRAM0_D18, IO_IS = emc_data[13]
    PORT D19 = CONN_SRAM0_D19, IO_IS = emc_data[12]
    PORT D20 = CONN_SRAM0_D20, IO_IS = emc_data[11]
    PORT D21 = CONN_SRAM0_D21, IO_IS = emc_data[10]
    PORT D22 = CONN_SRAM0_D22, IO_IS = emc_data[9]
    PORT D23 = CONN_SRAM0_D23, IO_IS = emc_data[8]
    PORT D24 = CONN_SRAM0_D24, IO_IS = emc_data[7]
    PORT D25 = CONN_SRAM0_D25, IO_IS = emc_data[6]
    PORT D26 = CONN_SRAM0_D26, IO_IS = emc_data[5]
    PORT D27 = CONN_SRAM0_D27, IO_IS = emc_data[4]
    PORT D28 = CONN_SRAM0_D28, IO_IS = emc_data[3]
    PORT D29 = CONN_SRAM0_D29, IO_IS = emc_data[2]
    PORT D30 = CONN_SRAM0_D30, IO_IS = emc_data[1]
    PORT D31 = CONN_SRAM0_D31, IO_IS = emc_data[0]

    PORT OEN = CONN_SRAM0_OEN, IO_IS = emc_oen[0]
    PORT ADV_LDN = CONN_SRAM0_ADV_LDN, IO_IS = emc_adv_ldn
    PORT ZBT_CLK_OUT = CONN_SRAM0_CLK, IO_IS=EMC_CLK_OUT

    PORT CKEN_PORT = CONN_SRAM0_CKEN, IO_IS = emc_cken
    PORT CE_PORT = CONN_SRAM0_CE, IO_IS = emc_ce   
END

BEGIN IO_INTERFACE
    ATTRIBUTE IOTYPE = XIL_EMC_V1
    ATTRIBUTE INSTANCE = SRAM1_ZBT_512Kx32
    PARAMETER C_NUM_BANKS_MEM = 1, IO_IS=C_NUM_BANKS_MEM
    PARAMETER C_DEV_MIR_ENABLE = 0, IO_IS=C_DEV_MIR_ENABLE
    PARAMETER C_MAX_MEM_WIDTH = 32, IO_IS=C_MAX_MEM_WIDTH
    PARAMETER C_INCLUDE_NEGEDGE_IOREGS = 1, IO_IS=C_INCLUDE_NEGEDGE_IOREGS

    PARAMETER C_INCLUDE_BURST_CACHELN_SUPPORT = 1, IO_IS=C_INCLUDE_BURST_CACHELN_SUPPORT
    PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1, IO_IS=C_INCLUDE_DATAWIDTH_MATCHING_0
    PARAMETER C_MEM0_BASEADDR = 0x0, IO_IS=C_MEM0_BASEADDR, SHORT_DESC=SRAM_256Kx32
    PARAMETER C_MEM0_HIGHADDR = 0x1FFFFF, IO_IS=C_MEM0_HIGHADDR
    PARAMETER C_MEM0_WIDTH = 32, IO_IS=C_MEM0_WIDTH
    PARAMETER C_SYNCH_MEM_0 = 1, IO_IS=C_SYNCH_MEM_0
    PARAMETER C_SYNCH_PIPEDELAY_0 = 2, IO_IS=C_SYNCH_PIPEDELAY_0

    PARAMETER C_READ_ADDR_TO_OUT_SLOW_PS_0 = 0,  IO_IS = C_READ_ADDR_TO_OUT_SLOW_PS_0
    PARAMETER C_WRITE_ADDR_TO_OUT_SLOW_PS_0 = 0, IO_IS = C_WRITE_ADDR_TO_OUT_SLOW_PS_0
    PARAMETER C_WRITE_MIN_PULSE_WIDTH_PS_0 = 0,  IO_IS = C_WRITE_MIN_PULSE_WIDTH_PS_0
    PARAMETER C_READ_ADDR_TO_OUT_FAST_PS_0 = 0,  IO_IS = C_READ_ADDR_TO_OUT_FAST_PS_0
    PARAMETER C_WRITE_ADDR_TO_OUT_FAST_PS_0 = 0, IO_IS = C_WRITE_ADDR_TO_OUT_FAST_PS_0
    PARAMETER C_READ_RECOVERY_BEFORE_WRITE_PS_0 = 0, IO_IS = C_READ_RECOVERY_BEFORE_WRITE_PS_0
    PARAMETER C_WRITE_RECOVERY_BEFORE_READ_PS_0 = 0, IO_IS = C_WRITE_RECOVERY_BEFORE_READ_PS_0

    PORT A0 = CONN_SRAM1_A0, IO_IS = emc_addr[29]
    PORT A1 = CONN_SRAM1_A1, IO_IS = emc_addr[28]
    PORT A2 = CONN_SRAM1_A2, IO_IS = emc_addr[27]
    PORT A3 = CONN_SRAM1_A3, IO_IS = emc_addr[26]
    PORT A4 = CONN_SRAM1_A4, IO_IS = emc_addr[25]
    PORT A5 = CONN_SRAM1_A5, IO_IS = emc_addr[24]
    PORT A6 = CONN_SRAM1_A6, IO_IS = emc_addr[23]
    PORT A7 = CONN_SRAM1_A7, IO_IS = emc_addr[22]
    PORT A8 = CONN_SRAM1_A8, IO_IS = emc_addr[21]
    PORT A9 = CONN_SRAM1_A9, IO_IS = emc_addr[20]
    PORT A10 = CONN_SRAM1_A10, IO_IS = emc_addr[19]
    PORT A11 = CONN_SRAM1_A11, IO_IS = emc_addr[18]
    PORT A12 = CONN_SRAM1_A12, IO_IS = emc_addr[17]
    PORT A13 = CONN_SRAM1_A13, IO_IS = emc_addr[16]
    PORT A14 = CONN_SRAM1_A14, IO_IS = emc_addr[15]
    PORT A15 = CONN_SRAM1_A15, IO_IS = emc_addr[14]
    PORT A16 = CONN_SRAM1_A16, IO_IS = emc_addr[13]
    PORT A17 = CONN_SRAM1_A17, IO_IS = emc_addr[12]
    PORT A18 = CONN_SRAM1_A18, IO_IS = emc_addr[11]

    PORT BEN0 = CONN_SRAM1_BEN0, IO_IS = emc_ben[3]
    PORT BEN1 = CONN_SRAM1_BEN1, IO_IS = emc_ben[2]
    PORT BEN2 = CONN_SRAM1_BEN2, IO_IS = emc_ben[1]
    PORT BEN3 = CONN_SRAM1_BEN3, IO_IS = emc_ben[0]
    PORT WEN = CONN_SRAM1_WEN, IO_IS=emc_wen

    PORT D0 = CONN_SRAM1_D0, IO_IS = emc_data[31]
    PORT D1 = CONN_SRAM1_D1, IO_IS = emc_data[30]
    PORT D2 = CONN_SRAM1_D2, IO_IS = emc_data[29]
    PORT D3 = CONN_SRAM1_D3, IO_IS = emc_data[28]
    PORT D4 = CONN_SRAM1_D4, IO_IS = emc_data[27]
    PORT D5 = CONN_SRAM1_D5, IO_IS = emc_data[26]
    PORT D6 = CONN_SRAM1_D6,  IO_IS = emc_data[25]
    PORT D7 = CONN_SRAM1_D7, IO_IS = emc_data[24]
    PORT D8 = CONN_SRAM1_D8, IO_IS = emc_data[23]
    PORT D9 = CONN_SRAM1_D9, IO_IS = emc_data[22]
    PORT D10 = CONN_SRAM1_D10, IO_IS = emc_data[21]
    PORT D11 = CONN_SRAM1_D11, IO_IS = emc_data[20]
    PORT D12 = CONN_SRAM1_D12, IO_IS = emc_data[19]
    PORT D13 = CONN_SRAM1_D13, IO_IS = emc_data[18]
    PORT D14 = CONN_SRAM1_D14, IO_IS = emc_data[17]
    PORT D15 = CONN_SRAM1_D15, IO_IS = emc_data[16]
    PORT D16 = CONN_SRAM1_D16, IO_IS = emc_data[15]
    PORT D17 = CONN_SRAM1_D17, IO_IS = emc_data[14]
    PORT D18 = CONN_SRAM1_D18, IO_IS = emc_data[13]
    PORT D19 = CONN_SRAM1_D19, IO_IS = emc_data[12]
    PORT D20 = CONN_SRAM1_D20, IO_IS = emc_data[11]
    PORT D21 = CONN_SRAM1_D21, IO_IS = emc_data[10]
    PORT D22 = CONN_SRAM1_D22, IO_IS = emc_data[9]
    PORT D23 = CONN_SRAM1_D23, IO_IS = emc_data[8]
    PORT D24 = CONN_SRAM1_D24, IO_IS = emc_data[7]
    PORT D25 = CONN_SRAM1_D25, IO_IS = emc_data[6]
    PORT D26 = CONN_SRAM1_D26, IO_IS = emc_data[5]
    PORT D27 = CONN_SRAM1_D27, IO_IS = emc_data[4]
    PORT D28 = CONN_SRAM1_D28, IO_IS = emc_data[3]
    PORT D29 = CONN_SRAM1_D29, IO_IS = emc_data[2]
    PORT D30 = CONN_SRAM1_D30, IO_IS = emc_data[1]
    PORT D31 = CONN_SRAM1_D31, IO_IS = emc_data[0]

    PORT OEN = CONN_SRAM1_OEN, IO_IS = emc_oen[0]
    PORT ADV_LDN = CONN_SRAM1_ADV_LDN, IO_IS = emc_adv_ldn
    PORT ZBT_CLK_OUT = CONN_SRAM1_CLK, IO_IS=EMC_CLK_OUT

    PORT CKEN_PORT = CONN_SRAM1_CKEN, IO_IS = emc_cken
    PORT CE_PORT = CONN_SRAM1_CE, IO_IS = emc_ce   
END

# This is the FPGA definition. First characterize the processor.
BEGIN FPGA
    ATTRIBUTE INSTANCE = fpga_0
    ATTRIBUTE FAMILY = virtex2p
    ATTRIBUTE  DEVICE =  XC2VP70
    ATTRIBUTE PACKAGE =  FF1517
    ATTRIBUTE SPEED_GRADE = -6
    ATTRIBUTE JTAG_POSITION = 2 #SysaceCF is in position 1

### Clock ###  Use the same port connection names as defined above.
#   PORT CLK_0 = CONN_GCLK0_GCLK5S, UCF_NET_STRING=("LOC=AH21", "IOSTANDARD = LVTTL")
    PORT CLK_100 = clk100_osc, UCF_NET_STRING=("LOC=AH21", "IOSTANDARD = LVTTL")
    PORT CLK_40 = CONN_GCLK0_GCLK6P, UCF_NET_STRING=("LOC=AT20", "IOSTANDARD = LVTTL")

### RESET ### #Down push button
    PORT RESET = CONN_INIT_INIT, UCF_NET_STRING=("LOC=AM16", "IOSTANDARD = LVTTL") 

### Clock Board Configurator ###
    PORT clk_board_radio_DO = clk_board_radio_DO, UCF_NET_STRING=("LOC=AN25", "IOSTANDARD=LVTTL", "SLEW = SLOW")
    PORT clk_board_radio_CS = clk_board_radio_CS, UCF_NET_STRING=("LOC=AK26", "IOSTANDARD=LVTTL", "SLEW = SLOW")
    PORT clk_board_radio_EN = clk_board_radio_EN, UCF_NET_STRING=("LOC=AJ25", "IOSTANDARD=LVTTL", "SLEW = SLOW")
    PORT clk_board_radio_CLK = clk_board_radio_CLK, UCF_NET_STRING=("LOC=AL26", "IOSTANDARD=LVTTL", "SLEW = SLOW")
    PORT clk_board_logic_DO = clk_board_logic_DO, UCF_NET_STRING=("LOC=AT27", "IOSTANDARD=LVTTL", "SLEW = SLOW")
    PORT clk_board_logic_CS = clk_board_logic_CS, UCF_NET_STRING=("LOC=AR27", "IOSTANDARD=LVTTL", "SLEW = SLOW")
    PORT clk_board_logic_EN = clk_board_logic_EN, UCF_NET_STRING=("LOC=AN27", "IOSTANDARD=LVTTL", "SLEW = SLOW")
    PORT clk_board_logic_CLK = clk_board_logic_CLK, UCF_NET_STRING=("LOC=AM27", "IOSTANDARD=LVTTL", "SLEW = SLOW")

##Radio Bridge for Slot #1
#   PORT radio1_conv_clk_p = radio1_conv_clk_p, UCF_NET_STRING=("LOC=M8", "IOSTANDARD=LVDCI_33")
    PORT radio1_conv_clk_p = radio1_conv_clk_p, UCF_NET_STRING=("LOC=L2", "IOSTANDARD=LVTTL")
    PORT radio1_EEPROM_IO = radio1_EEPROM_IO, UCF_NET_STRING=("LOC=K3", "IOSTANDARD=LVTTL", "SLEW = SLOW", "DRIVE = 8")
    PORT dac1_spi_clk_pin = dac1_spi_clk, UCF_NET_STRING=("LOC=T7", "IOSTANDARD=LVTTL")
    PORT dac1_spi_cs_pin = dac1_spi_cs, UCF_NET_STRING=("LOC=T6", "IOSTANDARD=LVTTL")
    PORT dac1_spi_data_pin = dac1_spi_data, UCF_NET_STRING=("LOC=R8", "IOSTANDARD=LVTTL")
    PORT radio1_24PA_pin = radio1_24PA, UCF_NET_STRING=("LOC=E6", "IOSTANDARD=LVTTL", "SLEW = SLOW", "DRIVE = 2")
    PORT radio1_5PA_pin = radio1_5PA, UCF_NET_STRING=("LOC=N10", "IOSTANDARD=LVTTL", "SLEW = SLOW", "DRIVE = 2")
    PORT radio1_ANTSW0_pin = radio1_ANTSW0, UCF_NET_STRING=("LOC=D5", "IOSTANDARD=LVTTL", "SLEW = SLOW", "DRIVE = 2")
    PORT radio1_ANTSW1_pin = radio1_ANTSW1, UCF_NET_STRING=("LOC=K6", "IOSTANDARD=LVTTL", "SLEW = SLOW", "DRIVE = 2")
    PORT radio1_dac1_PLL_LOCK_pin = radio1_dac1_PLL_LOCK, UCF_NET_STRING=("LOC=V5", "IOSTANDARD=LVTTL")
    PORT radio1_dac1_RESET_pin = radio1_dac1_RESET, UCF_NET_STRING=("LOC=U2", "IOSTANDARD=LVTTL")
    PORT radio1_DIPSW0_pin = radio1_DIPSW0, UCF_NET_STRING=("LOC=T2", "IOSTANDARD=LVTTL")
    PORT radio1_DIPSW1_pin = radio1_DIPSW1, UCF_NET_STRING=("LOC=P3", "IOSTANDARD=LVTTL")
    PORT radio1_DIPSW2_pin = radio1_DIPSW2, UCF_NET_STRING=("LOC=R1", "IOSTANDARD=LVTTL")
    PORT radio1_DIPSW3_pin = radio1_DIPSW3, UCF_NET_STRING=("LOC=R2", "IOSTANDARD=LVTTL")
    PORT radio1_LD_pin = radio1_LD, UCF_NET_STRING=("LOC=P6", "IOSTANDARD=LVTTL")
    PORT radio1_LED0_pin = radio1_LED0, UCF_NET_STRING=("LOC=F7", "IOSTANDARD=LVTTL", "SLEW = SLOW", "DRIVE = 2")
    PORT radio1_LED1_pin = radio1_LED1, UCF_NET_STRING=("LOC=L8", "IOSTANDARD=LVTTL", "SLEW = SLOW", "DRIVE = 2")
    PORT radio1_LED2_pin = radio1_LED2, UCF_NET_STRING=("LOC=H2", "IOSTANDARD=LVTTL", "SLEW = SLOW", "DRIVE = 2")
    PORT radio1_rssi_ADC_clk_pin = radio1_rssi_ADC_clk, UCF_NET_STRING=("LOC=N1", "IOSTANDARD=LVTTL")
    PORT radio1_RSSI_ADC_CLAMP_pin = radio1_RSSI_ADC_CLAMP, UCF_NET_STRING=("LOC=V2", "IOSTANDARD=LVTTL")
    PORT radio1_RSSI_ADC_D0_pin = radio1_RSSI_ADC_D0, UCF_NET_STRING=("LOC=R9", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio1_RSSI_ADC_D1_pin = radio1_RSSI_ADC_D1, UCF_NET_STRING=("LOC=W3", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio1_RSSI_ADC_D2_pin = radio1_RSSI_ADC_D2, UCF_NET_STRING=("LOC=R6", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio1_RSSI_ADC_D3_pin = radio1_RSSI_ADC_D3, UCF_NET_STRING=("LOC=R7", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio1_RSSI_ADC_D4_pin = radio1_RSSI_ADC_D4, UCF_NET_STRING=("LOC=P5", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio1_RSSI_ADC_D5_pin = radio1_RSSI_ADC_D5, UCF_NET_STRING=("LOC=T12", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio1_RSSI_ADC_D6_pin = radio1_RSSI_ADC_D6, UCF_NET_STRING=("LOC=U6", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio1_RSSI_ADC_D7_pin = radio1_RSSI_ADC_D7, UCF_NET_STRING=("LOC=W6", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio1_RSSI_ADC_D8_pin = radio1_RSSI_ADC_D8, UCF_NET_STRING=("LOC=W7", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio1_RSSI_ADC_D9_pin = radio1_RSSI_ADC_D9, UCF_NET_STRING=("LOC=Y7", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio1_RSSI_ADC_HIZ_pin = radio1_RSSI_ADC_HIZ, UCF_NET_STRING=("LOC=V1", "IOSTANDARD=LVTTL")
    PORT radio1_RSSI_ADC_OTR_pin = radio1_RSSI_ADC_OTR, UCF_NET_STRING=("LOC=T8", "IOSTANDARD=LVTTL")
    PORT radio1_RSSI_ADC_SLEEP_pin = radio1_RSSI_ADC_SLEEP, UCF_NET_STRING=("LOC=P7", "IOSTANDARD=LVTTL")
    PORT radio1_RX_ADC_DCS_pin = radio1_RX_ADC_DCS, UCF_NET_STRING=("LOC=M7", "IOSTANDARD=LVTTL")
    PORT radio1_RX_ADC_DFS_pin = radio1_RX_ADC_DFS, UCF_NET_STRING=("LOC=N2", "IOSTANDARD=LVTTL")
    PORT radio1_RX_ADC_OTRA_pin = radio1_RX_ADC_OTRA, UCF_NET_STRING=("LOC=H7", "IOSTANDARD=LVTTL")
    PORT radio1_RX_ADC_OTRB_pin = radio1_RX_ADC_OTRB, UCF_NET_STRING=("LOC=K9", "IOSTANDARD=LVTTL")
    PORT radio1_RX_ADC_PWDNA_pin = radio1_RX_ADC_PWDNA, UCF_NET_STRING=("LOC=H8", "IOSTANDARD=LVTTL")
    PORT radio1_RX_ADC_PWDNB_pin = radio1_RX_ADC_PWDNB, UCF_NET_STRING=("LOC=R11", "IOSTANDARD=LVTTL")
    PORT radio1_TxEn_pin = radio1_TxEn, UCF_NET_STRING=("LOC=R4", "IOSTANDARD=LVTTL", "SLEW = SLOW")
    PORT radio1_RxEn_pin = radio1_RxEn, UCF_NET_STRING=("LOC=L4", "IOSTANDARD=LVTTL", "SLEW = SLOW")
    PORT radio1_RxHP_pin = radio1_RxHP, UCF_NET_STRING=("LOC=M6", "IOSTANDARD=LVTTL", "SLEW = SLOW")
    PORT radio1_SHDN_pin = radio1_SHDN, UCF_NET_STRING=("LOC=L5", "IOSTANDARD=LVTTL", "SLEW = SLOW")
    PORT radio1_spi_clk_pin = radio1_spi_clk, UCF_NET_STRING=("LOC=P9", "IOSTANDARD=LVTTL")
    PORT radio1_spi_cs_pin = radio1_spi_cs, UCF_NET_STRING=("LOC=R3", "IOSTANDARD=LVTTL")
    PORT radio1_spi_data_pin = radio1_spi_data, UCF_NET_STRING=("LOC=R5", "IOSTANDARD=LVTTL")

    PORT radio1_b0_pin = radio1_b0, UCF_NET_STRING=("LOC=P1", "IOSTANDARD = LVTTL", "SLEW = SLOW") #Radio_B1
    PORT radio1_b1_pin = radio1_b1, UCF_NET_STRING=("LOC=P8", "IOSTANDARD = LVTTL", "SLEW = SLOW") #Radio_B2
    PORT radio1_b2_pin = radio1_b2, UCF_NET_STRING=("LOC=P10", "IOSTANDARD = LVTTL", "SLEW = SLOW") #Radio_B3
    PORT radio1_b3_pin = radio1_b3, UCF_NET_STRING=("LOC=N3", "IOSTANDARD = LVTTL", "SLEW = SLOW") #Radio_B4
    PORT radio1_b4_pin = radio1_b4, UCF_NET_STRING=("LOC=P4", "IOSTANDARD = LVTTL", "SLEW = SLOW") #Radio_B5
    PORT radio1_b5_pin = radio1_b5, UCF_NET_STRING=("LOC=K1", "IOSTANDARD = LVTTL", "SLEW = SLOW") #Radio_B6
    PORT radio1_b6_pin = radio1_b6, UCF_NET_STRING=("LOC=K2", "IOSTANDARD = LVTTL", "SLEW = SLOW") #Radio_B7

    PORT radio1_DAC_I0_pin = radio1_DAC_I0, UCF_NET_STRING=("LOC=Y3", "IOSTANDARD = LVTTL")
    PORT radio1_DAC_I1_pin = radio1_DAC_I1, UCF_NET_STRING=("LOC=W13", "IOSTANDARD = LVTTL")
    PORT radio1_DAC_I2_pin = radio1_DAC_I2, UCF_NET_STRING=("LOC=V13", "IOSTANDARD = LVTTL")
    PORT radio1_DAC_I3_pin = radio1_DAC_I3, UCF_NET_STRING=("LOC=W12", "IOSTANDARD = LVTTL")
    PORT radio1_DAC_I4_pin = radio1_DAC_I4, UCF_NET_STRING=("LOC=Y4", "IOSTANDARD = LVTTL")
    PORT radio1_DAC_I5_pin = radio1_DAC_I5, UCF_NET_STRING=("LOC=V12", "IOSTANDARD = LVTTL")
    PORT radio1_DAC_I6_pin = radio1_DAC_I6, UCF_NET_STRING=("LOC=W10", "IOSTANDARD = LVTTL")
    PORT radio1_DAC_I7_pin = radio1_DAC_I7, UCF_NET_STRING=("LOC=Y8", "IOSTANDARD = LVTTL")
    PORT radio1_DAC_I8_pin = radio1_DAC_I8, UCF_NET_STRING=("LOC=Y9", "IOSTANDARD = LVTTL")
    PORT radio1_DAC_I9_pin = radio1_DAC_I9, UCF_NET_STRING=("LOC=V11", "IOSTANDARD = LVTTL")
    PORT radio1_DAC_I10_pin = radio1_DAC_I10, UCF_NET_STRING=("LOC=V10", "IOSTANDARD = LVTTL")
    PORT radio1_DAC_I11_pin = radio1_DAC_I11, UCF_NET_STRING=("LOC=W11", "IOSTANDARD = LVTTL")
    PORT radio1_DAC_I12_pin = radio1_DAC_I12, UCF_NET_STRING=("LOC=W9", "IOSTANDARD = LVTTL")
    PORT radio1_DAC_I13_pin = radio1_DAC_I13, UCF_NET_STRING=("LOC=W8", "IOSTANDARD = LVTTL")
    PORT radio1_DAC_I14_pin = radio1_DAC_I14, UCF_NET_STRING=("LOC=T10", "IOSTANDARD = LVTTL")
    PORT radio1_DAC_I15_pin = radio1_DAC_I15, UCF_NET_STRING=("LOC=U12", "IOSTANDARD = LVTTL")

    PORT radio1_DAC_Q0_pin = radio1_DAC_Q0, UCF_NET_STRING=("LOC=U8", "IOSTANDARD = LVTTL")
    PORT radio1_DAC_Q1_pin = radio1_DAC_Q1, UCF_NET_STRING=("LOC=V7", "IOSTANDARD = LVTTL")
    PORT radio1_DAC_Q2_pin = radio1_DAC_Q2, UCF_NET_STRING=("LOC=R10", "IOSTANDARD = LVTTL")
    PORT radio1_DAC_Q3_pin = radio1_DAC_Q3, UCF_NET_STRING=("LOC=U5", "IOSTANDARD = LVTTL")
    PORT radio1_DAC_Q4_pin = radio1_DAC_Q4, UCF_NET_STRING=("LOC=T4", "IOSTANDARD = LVTTL")
    PORT radio1_DAC_Q5_pin = radio1_DAC_Q5, UCF_NET_STRING=("LOC=T3", "IOSTANDARD = LVTTL")
    PORT radio1_DAC_Q6_pin = radio1_DAC_Q6, UCF_NET_STRING=("LOC=U9", "IOSTANDARD = LVTTL")
    PORT radio1_DAC_Q7_pin = radio1_DAC_Q7, UCF_NET_STRING=("LOC=U4", "IOSTANDARD = LVTTL")
    PORT radio1_DAC_Q8_pin = radio1_DAC_Q8, UCF_NET_STRING=("LOC=T11", "IOSTANDARD = LVTTL")
    PORT radio1_DAC_Q9_pin = radio1_DAC_Q9, UCF_NET_STRING=("LOC=V6", "IOSTANDARD = LVTTL")
    PORT radio1_DAC_Q10_pin = radio1_DAC_Q10, UCF_NET_STRING=("LOC=U10", "IOSTANDARD = LVTTL")
    PORT radio1_DAC_Q11_pin = radio1_DAC_Q11, UCF_NET_STRING=("LOC=V9", "IOSTANDARD = LVTTL")
    PORT radio1_DAC_Q12_pin = radio1_DAC_Q12, UCF_NET_STRING=("LOC=V4", "IOSTANDARD = LVTTL")
    PORT radio1_DAC_Q13_pin = radio1_DAC_Q13, UCF_NET_STRING=("LOC=V8", "IOSTANDARD = LVTTL")
    PORT radio1_DAC_Q14_pin = radio1_DAC_Q14, UCF_NET_STRING=("LOC=V3", "IOSTANDARD = LVTTL")
    PORT radio1_DAC_Q15_pin = radio1_DAC_Q15, UCF_NET_STRING=("LOC=W4", "IOSTANDARD = LVTTL")

    PORT radio1_ADC_I0_pin = radio1_ADC_I0, UCF_NET_STRING=("LOC=E7", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio1_ADC_I1_pin = radio1_ADC_I1, UCF_NET_STRING=("LOC=J1", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio1_ADC_I2_pin = radio1_ADC_I2, UCF_NET_STRING=("LOC=E3", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio1_ADC_I3_pin = radio1_ADC_I3, UCF_NET_STRING=("LOC=M20", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio1_ADC_I4_pin = radio1_ADC_I4, UCF_NET_STRING=("LOC=D6", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio1_ADC_I5_pin = radio1_ADC_I5, UCF_NET_STRING=("LOC=K4", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio1_ADC_I6_pin = radio1_ADC_I6, UCF_NET_STRING=("LOC=E2", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio1_ADC_I7_pin = radio1_ADC_I7, UCF_NET_STRING=("LOC=J7", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio1_ADC_I8_pin = radio1_ADC_I8, UCF_NET_STRING=("LOC=H6", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio1_ADC_I9_pin = radio1_ADC_I9, UCF_NET_STRING=("LOC=J2", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio1_ADC_I10_pin = radio1_ADC_I10, UCF_NET_STRING=("LOC=K8", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio1_ADC_I11_pin = radio1_ADC_I11, UCF_NET_STRING=("LOC=J6", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio1_ADC_I12_pin = radio1_ADC_I12, UCF_NET_STRING=("LOC=J9", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio1_ADC_I13_pin = radio1_ADC_I13, UCF_NET_STRING=("LOC=L9", "IOSTANDARD = LVTTL", "PULLDOWN")

    PORT radio1_ADC_Q0_pin = radio1_ADC_Q0, UCF_NET_STRING=("LOC=M2", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio1_ADC_Q1_pin = radio1_ADC_Q1, UCF_NET_STRING=("LOC=L3", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio1_ADC_Q2_pin = radio1_ADC_Q2, UCF_NET_STRING=("LOC=M10", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio1_ADC_Q3_pin = radio1_ADC_Q3, UCF_NET_STRING=("LOC=M4", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio1_ADC_Q4_pin = radio1_ADC_Q4, UCF_NET_STRING=("LOC=K5", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio1_ADC_Q5_pin = radio1_ADC_Q5, UCF_NET_STRING=("LOC=N7", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio1_ADC_Q6_pin = radio1_ADC_Q6, UCF_NET_STRING=("LOC=L7", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio1_ADC_Q7_pin = radio1_ADC_Q7, UCF_NET_STRING=("LOC=L1", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio1_ADC_Q8_pin = radio1_ADC_Q8, UCF_NET_STRING=("LOC=J3", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio1_ADC_Q9_pin = radio1_ADC_Q9, UCF_NET_STRING=("LOC=H4", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio1_ADC_Q10_pin = radio1_ADC_Q10, UCF_NET_STRING=("LOC=H3", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio1_ADC_Q11_pin = radio1_ADC_Q11, UCF_NET_STRING=("LOC=J5", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio1_ADC_Q12_pin = radio1_ADC_Q12, UCF_NET_STRING=("LOC=G9", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio1_ADC_Q13_pin = radio1_ADC_Q13, UCF_NET_STRING=("LOC=H9", "IOSTANDARD = LVTTL", "PULLDOWN")

#Radio Bridge for Slot #2
#   PORT radio2_conv_clk_p = radio2_conv_clk_p, UCF_NET_STRING=("LOC=AH2", "IOSTANDARD=LVDCI_33")
    PORT radio2_conv_clk_p = radio2_conv_clk_p, UCF_NET_STRING=("LOC=AG2", "IOSTANDARD=LVTTL")
    PORT radio2_EEPROM_IO = radio2_EEPROM_IO, UCF_NET_STRING=("LOC=AG3", "IOSTANDARD=LVTTL", "SLEW = SLOW", "DRIVE = 8")
    PORT dac2_spi_clk_pin = dac2_spi_clk, UCF_NET_STRING=("LOC=AK6", "IOSTANDARD=LVTTL")
    PORT dac2_spi_cs_pin = dac2_spi_cs, UCF_NET_STRING=("LOC=AJ6", "IOSTANDARD=LVTTL")
    PORT dac2_spi_data_pin = dac2_spi_data, UCF_NET_STRING=("LOC=AL5", "IOSTANDARD=LVTTL")
    PORT radio2_24PA_pin = radio2_24PA, UCF_NET_STRING=("LOC=AA9", "IOSTANDARD=LVTTL", "SLEW = SLOW", "DRIVE = 2")
    PORT radio2_5PA_pin = radio2_5PA, UCF_NET_STRING=("LOC=AB2", "IOSTANDARD=LVTTL", "SLEW = SLOW", "DRIVE = 2")
    PORT radio2_ANTSW0_pin = radio2_ANTSW0, UCF_NET_STRING=("LOC=AB1", "IOSTANDARD=LVTTL", "SLEW = SLOW", "DRIVE = 2")
    PORT radio2_ANTSW1_pin = radio2_ANTSW1, UCF_NET_STRING=("LOC=AA6", "IOSTANDARD=LVTTL", "SLEW = SLOW", "DRIVE = 2")
    PORT radio2_dac2_PLL_LOCK_pin = radio2_dac2_PLL_LOCK, UCF_NET_STRING=("LOC=AG10", "IOSTANDARD=LVTTL")
    PORT radio2_dac2_RESET_pin = radio2_dac2_RESET, UCF_NET_STRING=("LOC=AM3", "IOSTANDARD=LVTTL")
    PORT radio2_DIPSW0_pin = radio2_DIPSW0, UCF_NET_STRING=("LOC=AG7", "IOSTANDARD=LVTTL")
    PORT radio2_DIPSW1_pin = radio2_DIPSW1, UCF_NET_STRING=("LOC=AL2", "IOSTANDARD=LVTTL")
    PORT radio2_DIPSW2_pin = radio2_DIPSW2, UCF_NET_STRING=("LOC=AJ4", "IOSTANDARD=LVTTL")
    PORT radio2_DIPSW3_pin = radio2_DIPSW3, UCF_NET_STRING=("LOC=AK3", "IOSTANDARD=LVTTL")
    PORT radio2_LD_pin = radio2_LD, UCF_NET_STRING=("LOC=AK5", "IOSTANDARD=LVTTL")
    PORT radio2_LED0_pin = radio2_LED0, UCF_NET_STRING=("LOC=AA5", "IOSTANDARD=LVTTL", "SLEW = SLOW", "DRIVE = 2")
    PORT radio2_LED1_pin = radio2_LED1, UCF_NET_STRING=("LOC=AA8", "IOSTANDARD=LVTTL", "SLEW = SLOW", "DRIVE = 2")
    PORT radio2_LED2_pin = radio2_LED2, UCF_NET_STRING=("LOC=AC2", "IOSTANDARD=LVTTL", "SLEW = SLOW", "DRIVE = 2")
    PORT radio2_rssi_ADC_clk_pin = radio2_rssi_ADC_clk, UCF_NET_STRING=("LOC=AK2", "IOSTANDARD=LVTTL")
    PORT radio2_RSSI_ADC_CLAMP_pin = radio2_RSSI_ADC_CLAMP, UCF_NET_STRING=("LOC=AH6", "IOSTANDARD=LVTTL")
    PORT radio2_RSSI_ADC_D0_pin = radio2_RSSI_ADC_D0, UCF_NET_STRING=("LOC=AF11", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio2_RSSI_ADC_D1_pin = radio2_RSSI_ADC_D1, UCF_NET_STRING=("LOC=AE8", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio2_RSSI_ADC_D2_pin = radio2_RSSI_ADC_D2, UCF_NET_STRING=("LOC=AF10", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio2_RSSI_ADC_D3_pin = radio2_RSSI_ADC_D3, UCF_NET_STRING=("LOC=AD11", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio2_RSSI_ADC_D4_pin = radio2_RSSI_ADC_D4, UCF_NET_STRING=("LOC=AJ7", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio2_RSSI_ADC_D5_pin = radio2_RSSI_ADC_D5, UCF_NET_STRING=("LOC=AJ5", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio2_RSSI_ADC_D6_pin = radio2_RSSI_ADC_D6, UCF_NET_STRING=("LOC=AJ8", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio2_RSSI_ADC_D7_pin = radio2_RSSI_ADC_D7, UCF_NET_STRING=("LOC=AG11", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio2_RSSI_ADC_D8_pin = radio2_RSSI_ADC_D8, UCF_NET_STRING=("LOC=AM9", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio2_RSSI_ADC_D9_pin = radio2_RSSI_ADC_D9, UCF_NET_STRING=("LOC=AK7", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio2_RSSI_ADC_HIZ_pin = radio2_RSSI_ADC_HIZ, UCF_NET_STRING=("LOC=AF8", "IOSTANDARD=LVTTL")
    PORT radio2_RSSI_ADC_OTR_pin = radio2_RSSI_ADC_OTR, UCF_NET_STRING=("LOC=AJ9", "IOSTANDARD=LVTTL")
    PORT radio2_RSSI_ADC_SLEEP_pin = radio2_RSSI_ADC_SLEEP, UCF_NET_STRING=("LOC=AF7", "IOSTANDARD=LVTTL")
    PORT radio2_RX_ADC_DCS_pin = radio2_RX_ADC_DCS, UCF_NET_STRING=("LOC=AD8", "IOSTANDARD=LVTTL")
    PORT radio2_RX_ADC_DFS_pin = radio2_RX_ADC_DFS, UCF_NET_STRING=("LOC=AK1", "IOSTANDARD=LVTTL")
    PORT radio2_RX_ADC_OTRA_pin = radio2_RX_ADC_OTRA, UCF_NET_STRING=("LOC=AA4", "IOSTANDARD=LVTTL")
    PORT radio2_RX_ADC_OTRB_pin = radio2_RX_ADC_OTRB, UCF_NET_STRING=("LOC=AC4", "IOSTANDARD=LVTTL")
    PORT radio2_RX_ADC_PWDNA_pin = radio2_RX_ADC_PWDNA, UCF_NET_STRING=("LOC=AA3", "IOSTANDARD=LVTTL")
    PORT radio2_RX_ADC_PWDNB_pin = radio2_RX_ADC_PWDNB, UCF_NET_STRING=("LOC=AF6", "IOSTANDARD=LVTTL")
    PORT radio2_TxEn_pin = radio2_TxEn, UCF_NET_STRING=("LOC=AM2", "IOSTANDARD=LVTTL", "SLEW = SLOW")
    PORT radio2_RxEn_pin = radio2_RxEn, UCF_NET_STRING=("LOC=AD10", "IOSTANDARD=LVTTL", "SLEW = SLOW")
    PORT radio2_RxHP_pin = radio2_RxHP, UCF_NET_STRING=("LOC=AE6", "IOSTANDARD=LVTTL", "SLEW = SLOW")
    PORT radio2_SHDN_pin = radio2_SHDN, UCF_NET_STRING=("LOC=AF5", "IOSTANDARD=LVTTL", "SLEW = SLOW")
    PORT radio2_spi_clk_pin = radio2_spi_clk, UCF_NET_STRING=("LOC=AL3", "IOSTANDARD=LVTTL")
    PORT radio2_spi_cs_pin = radio2_spi_cs, UCF_NET_STRING=("LOC=AF9", "IOSTANDARD=LVTTL")
    PORT radio2_spi_data_pin = radio2_spi_data, UCF_NET_STRING=("LOC=AK4", "IOSTANDARD=LVTTL")

    PORT radio2_b0_pin = radio2_b0, UCF_NET_STRING=("LOC=AB7", "IOSTANDARD = LVTTL", "SLEW = SLOW") #Radio_B1
    PORT radio2_b1_pin = radio2_b1, UCF_NET_STRING=("LOC=AB8", "IOSTANDARD = LVTTL", "SLEW = SLOW") #Radio_B2
    PORT radio2_b2_pin = radio2_b2, UCF_NET_STRING=("LOC=AC10", "IOSTANDARD = LVTTL", "SLEW = SLOW") #Radio_B3
    PORT radio2_b3_pin = radio2_b3, UCF_NET_STRING=("LOC=AB9", "IOSTANDARD = LVTTL", "SLEW = SLOW") #Radio_B4
    PORT radio2_b4_pin = radio2_b4, UCF_NET_STRING=("LOC=AF3", "IOSTANDARD = LVTTL", "SLEW = SLOW") #Radio_B5
    PORT radio2_b5_pin = radio2_b5, UCF_NET_STRING=("LOC=AL1", "IOSTANDARD = LVTTL", "SLEW = SLOW") #Radio_B6
    PORT radio2_b6_pin = radio2_b6, UCF_NET_STRING=("LOC=AE4", "IOSTANDARD = LVTTL", "SLEW = SLOW") #Radio_B7

    PORT radio2_DAC_I0_pin = radio2_DAC_I0, UCF_NET_STRING=("LOC=AD13", "IOSTANDARD = LVTTL")
    PORT radio2_DAC_I1_pin = radio2_DAC_I1, UCF_NET_STRING=("LOC=AT8", "IOSTANDARD = LVTTL")
    PORT radio2_DAC_I2_pin = radio2_DAC_I2, UCF_NET_STRING=("LOC=AR8", "IOSTANDARD = LVTTL")
    PORT radio2_DAC_I3_pin = radio2_DAC_I3, UCF_NET_STRING=("LOC=AT5", "IOSTANDARD = LVTTL")
    PORT radio2_DAC_I4_pin = radio2_DAC_I4, UCF_NET_STRING=("LOC=AH11", "IOSTANDARD = LVTTL")
    PORT radio2_DAC_I5_pin = radio2_DAC_I5, UCF_NET_STRING=("LOC=AT6", "IOSTANDARD = LVTTL")
    PORT radio2_DAC_I6_pin = radio2_DAC_I6, UCF_NET_STRING=("LOC=AD12", "IOSTANDARD = LVTTL")
    PORT radio2_DAC_I7_pin = radio2_DAC_I7, UCF_NET_STRING=("LOC=AU5", "IOSTANDARD = LVTTL")
    PORT radio2_DAC_I8_pin = radio2_DAC_I8, UCF_NET_STRING=("LOC=AN9", "IOSTANDARD = LVTTL")
    PORT radio2_DAC_I9_pin = radio2_DAC_I9, UCF_NET_STRING=("LOC=AE13", "IOSTANDARD = LVTTL")
    PORT radio2_DAC_I10_pin = radio2_DAC_I10, UCF_NET_STRING=("LOC=AK9", "IOSTANDARD = LVTTL")
    PORT radio2_DAC_I11_pin = radio2_DAC_I11, UCF_NET_STRING=("LOC=AR7", "IOSTANDARD = LVTTL")
    PORT radio2_DAC_I12_pin = radio2_DAC_I12, UCF_NET_STRING=("LOC=AP7", "IOSTANDARD = LVTTL")
    PORT radio2_DAC_I13_pin = radio2_DAC_I13, UCF_NET_STRING=("LOC=AF12", "IOSTANDARD = LVTTL")
    PORT radio2_DAC_I14_pin = radio2_DAC_I14, UCF_NET_STRING=("LOC=AH10", "IOSTANDARD = LVTTL")
    PORT radio2_DAC_I15_pin = radio2_DAC_I15, UCF_NET_STRING=("LOC=AM6", "IOSTANDARD = LVTTL")

    PORT radio2_DAC_Q0_pin = radio2_DAC_Q0, UCF_NET_STRING=("LOC=AE10", "IOSTANDARD = LVTTL")
    PORT radio2_DAC_Q1_pin = radio2_DAC_Q1, UCF_NET_STRING=("LOC=AH8", "IOSTANDARD = LVTTL")
    PORT radio2_DAC_Q2_pin = radio2_DAC_Q2, UCF_NET_STRING=("LOC=AM4", "IOSTANDARD = LVTTL")
    PORT radio2_DAC_Q3_pin = radio2_DAC_Q3, UCF_NET_STRING=("LOC=AL7", "IOSTANDARD = LVTTL")
    PORT radio2_DAC_Q4_pin = radio2_DAC_Q4, UCF_NET_STRING=("LOC=AE11", "IOSTANDARD = LVTTL")
    PORT radio2_DAC_Q5_pin = radio2_DAC_Q5, UCF_NET_STRING=("LOC=AL6", "IOSTANDARD = LVTTL")
    PORT radio2_DAC_Q6_pin = radio2_DAC_Q6, UCF_NET_STRING=("LOC=AN6", "IOSTANDARD = LVTTL")
    PORT radio2_DAC_Q7_pin = radio2_DAC_Q7, UCF_NET_STRING=("LOC=AK8", "IOSTANDARD = LVTTL")
    PORT radio2_DAC_Q8_pin = radio2_DAC_Q8, UCF_NET_STRING=("LOC=AG9", "IOSTANDARD = LVTTL")
    PORT radio2_DAC_Q9_pin = radio2_DAC_Q9, UCF_NET_STRING=("LOC=AM7", "IOSTANDARD = LVTTL")
    PORT radio2_DAC_Q10_pin = radio2_DAC_Q10, UCF_NET_STRING=("LOC=AL9", "IOSTANDARD = LVTTL")
    PORT radio2_DAC_Q11_pin = radio2_DAC_Q11, UCF_NET_STRING=("LOC=AE12", "IOSTANDARD = LVTTL")
    PORT radio2_DAC_Q12_pin = radio2_DAC_Q12, UCF_NET_STRING=("LOC=AN7", "IOSTANDARD = LVTTL")
    PORT radio2_DAC_Q13_pin = radio2_DAC_Q13, UCF_NET_STRING=("LOC=AH7", "IOSTANDARD = LVTTL")
    PORT radio2_DAC_Q14_pin = radio2_DAC_Q14, UCF_NET_STRING=("LOC=AR6", "IOSTANDARD = LVTTL")
    PORT radio2_DAC_Q15_pin = radio2_DAC_Q15, UCF_NET_STRING=("LOC=AM8", "IOSTANDARD = LVTTL")

    PORT radio2_ADC_I0_pin = radio2_ADC_I0, UCF_NET_STRING=("LOC=AD4", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio2_ADC_I1_pin = radio2_ADC_I1, UCF_NET_STRING=("LOC=AB11", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio2_ADC_I2_pin = radio2_ADC_I2, UCF_NET_STRING=("LOC=AB10", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio2_ADC_I3_pin = radio2_ADC_I3, UCF_NET_STRING=("LOC=AG20", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio2_ADC_I4_pin = radio2_ADC_I4, UCF_NET_STRING=("LOC=AG1", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio2_ADC_I5_pin = radio2_ADC_I5, UCF_NET_STRING=("LOC=AE3", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio2_ADC_I6_pin = radio2_ADC_I6, UCF_NET_STRING=("LOC=AC5", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio2_ADC_I7_pin = radio2_ADC_I7, UCF_NET_STRING=("LOC=AE1", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio2_ADC_I8_pin = radio2_ADC_I8, UCF_NET_STRING=("LOC=AB5", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio2_ADC_I9_pin = radio2_ADC_I9, UCF_NET_STRING=("LOC=AB4", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio2_ADC_I10_pin = radio2_ADC_I10, UCF_NET_STRING=("LOC=AB6", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio2_ADC_I11_pin = radio2_ADC_I11, UCF_NET_STRING=("LOC=AD2", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio2_ADC_I12_pin = radio2_ADC_I12, UCF_NET_STRING=("LOC=AA7", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio2_ADC_I13_pin = radio2_ADC_I13, UCF_NET_STRING=("LOC=AB3", "IOSTANDARD = LVTTL", "PULLDOWN")

    PORT radio2_ADC_Q0_pin = radio2_ADC_Q0, UCF_NET_STRING=("LOC=AE7", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio2_ADC_Q1_pin = radio2_ADC_Q1, UCF_NET_STRING=("LOC=AC12", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio2_ADC_Q2_pin = radio2_ADC_Q2, UCF_NET_STRING=("LOC=AJ2", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio2_ADC_Q3_pin = radio2_ADC_Q3, UCF_NET_STRING=("LOC=AG5", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio2_ADC_Q4_pin = radio2_ADC_Q4, UCF_NET_STRING=("LOC=AJ1", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio2_ADC_Q5_pin = radio2_ADC_Q5, UCF_NET_STRING=("LOC=AH3", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio2_ADC_Q6_pin = radio2_ADC_Q6, UCF_NET_STRING=("LOC=AH4", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio2_ADC_Q7_pin = radio2_ADC_Q7, UCF_NET_STRING=("LOC=AJ3", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio2_ADC_Q8_pin = radio2_ADC_Q8, UCF_NET_STRING=("LOC=AA10", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio2_ADC_Q9_pin = radio2_ADC_Q9, UCF_NET_STRING=("LOC=AE2", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio2_ADC_Q10_pin = radio2_ADC_Q10, UCF_NET_STRING=("LOC=AA12", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio2_ADC_Q11_pin = radio2_ADC_Q11, UCF_NET_STRING=("LOC=AF1", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio2_ADC_Q12_pin = radio2_ADC_Q12, UCF_NET_STRING=("LOC=AD3", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio2_ADC_Q13_pin = radio2_ADC_Q13, UCF_NET_STRING=("LOC=AF2", "IOSTANDARD = LVTTL", "PULLDOWN")

##Radio Bridge for Slot #3
#   PORT radio3_conv_clk_p = radio3_conv_clk_p, UCF_NET_STRING=("LOC=AM31", "IOSTANDARD=LVDCI_33")
    PORT radio3_conv_clk_p = radio3_conv_clk_p, UCF_NET_STRING=("LOC=AP33", "IOSTANDARD=LVTTL")
    PORT radio3_EEPROM_IO = radio3_EEPROM_IO, UCF_NET_STRING=("LOC=AJ31", "IOSTANDARD=LVTTL", "SLEW = SLOW", "DRIVE = 8")
    PORT dac3_spi_clk_pin = dac3_spi_clk, UCF_NET_STRING=("LOC=AC31", "IOSTANDARD=LVTTL")
    PORT dac3_spi_cs_pin = dac3_spi_cs, UCF_NET_STRING=("LOC=AB31", "IOSTANDARD=LVTTL")
    PORT dac3_spi_data_pin = dac3_spi_data, UCF_NET_STRING=("LOC=AC32", "IOSTANDARD=LVTTL")
    PORT radio3_24PA_pin = radio3_24PA, UCF_NET_STRING=("LOC=AE33", "IOSTANDARD=LVTTL", "SLEW = SLOW", "DRIVE = 2")
    PORT radio3_5PA_pin = radio3_5PA, UCF_NET_STRING=("LOC=AH34", "IOSTANDARD=LVTTL", "SLEW = SLOW", "DRIVE = 2")
    PORT radio3_ANTSW0_pin = radio3_ANTSW0, UCF_NET_STRING=("LOC=AG33", "IOSTANDARD=LVTTL", "SLEW = SLOW", "DRIVE = 2")
    PORT radio3_ANTSW1_pin = radio3_ANTSW1, UCF_NET_STRING=("LOC=AH33", "IOSTANDARD=LVTTL", "SLEW = SLOW", "DRIVE = 2")
    PORT radio3_dac3_PLL_LOCK_pin = radio3_dac3_PLL_LOCK, UCF_NET_STRING=("LOC=AH38", "IOSTANDARD=LVTTL")
    PORT radio3_dac3_RESET_pin = radio3_dac3_RESET, UCF_NET_STRING=("LOC=AE35", "IOSTANDARD=LVTTL")
    PORT radio3_DIPSW0_pin = radio3_DIPSW0, UCF_NET_STRING=("LOC=AG37", "IOSTANDARD=LVTTL")
    PORT radio3_DIPSW1_pin = radio3_DIPSW1, UCF_NET_STRING=("LOC=AD34", "IOSTANDARD=LVTTL")
    PORT radio3_DIPSW2_pin = radio3_DIPSW2, UCF_NET_STRING=("LOC=AF36", "IOSTANDARD=LVTTL")
    PORT radio3_DIPSW3_pin = radio3_DIPSW3, UCF_NET_STRING=("LOC=AL39", "IOSTANDARD=LVTTL")
    PORT radio3_LD_pin = radio3_LD, UCF_NET_STRING=("LOC=AG35", "IOSTANDARD=LVTTL")
    PORT radio3_LED0_pin = radio3_LED0, UCF_NET_STRING=("LOC=AN34", "IOSTANDARD=LVTTL", "SLEW = SLOW", "DRIVE = 2")
    PORT radio3_LED1_pin = radio3_LED1, UCF_NET_STRING=("LOC=AK35", "IOSTANDARD=LVTTL", "SLEW = SLOW", "DRIVE = 2")
    PORT radio3_LED2_pin = radio3_LED2, UCF_NET_STRING=("LOC=AK34", "IOSTANDARD=LVTTL", "SLEW = SLOW", "DRIVE = 2")
    PORT radio3_rssi_ADC_clk_pin = radio3_rssi_ADC_clk, UCF_NET_STRING=("LOC=AM37", "IOSTANDARD=LVTTL")
    PORT radio3_RSSI_ADC_CLAMP_pin = radio3_RSSI_ADC_CLAMP, UCF_NET_STRING=("LOC=AA32", "IOSTANDARD=LVTTL")
    PORT radio3_RSSI_ADC_D0_pin = radio3_RSSI_ADC_D0, UCF_NET_STRING=("LOC=AA33", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio3_RSSI_ADC_D1_pin = radio3_RSSI_ADC_D1, UCF_NET_STRING=("LOC=AD36", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio3_RSSI_ADC_D2_pin = radio3_RSSI_ADC_D2, UCF_NET_STRING=("LOC=AC38", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio3_RSSI_ADC_D3_pin = radio3_RSSI_ADC_D3, UCF_NET_STRING=("LOC=AB37", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio3_RSSI_ADC_D4_pin = radio3_RSSI_ADC_D4, UCF_NET_STRING=("LOC=AA36", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio3_RSSI_ADC_D5_pin = radio3_RSSI_ADC_D5, UCF_NET_STRING=("LOC=AC39", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio3_RSSI_ADC_D6_pin = radio3_RSSI_ADC_D6, UCF_NET_STRING=("LOC=AA34", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio3_RSSI_ADC_D7_pin = radio3_RSSI_ADC_D7, UCF_NET_STRING=("LOC=AA31", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio3_RSSI_ADC_D8_pin = radio3_RSSI_ADC_D8, UCF_NET_STRING=("LOC=AA35", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio3_RSSI_ADC_D9_pin = radio3_RSSI_ADC_D9, UCF_NET_STRING=("LOC=AE37", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio3_RSSI_ADC_HIZ_pin = radio3_RSSI_ADC_HIZ, UCF_NET_STRING=("LOC=AB38", "IOSTANDARD=LVTTL")
    PORT radio3_RSSI_ADC_OTR_pin = radio3_RSSI_ADC_OTR, UCF_NET_STRING=("LOC=AD38", "IOSTANDARD=LVTTL")
    PORT radio3_RSSI_ADC_SLEEP_pin = radio3_RSSI_ADC_SLEEP, UCF_NET_STRING=("LOC=AA37", "IOSTANDARD=LVTTL")
    PORT radio3_RX_ADC_DCS_pin = radio3_RX_ADC_DCS, UCF_NET_STRING=("LOC=AH30", "IOSTANDARD=LVTTL")
    PORT radio3_RX_ADC_DFS_pin = radio3_RX_ADC_DFS, UCF_NET_STRING=("LOC=AM34", "IOSTANDARD=LVTTL")
    PORT radio3_RX_ADC_OTRA_pin = radio3_RX_ADC_OTRA, UCF_NET_STRING=("LOC=AG31", "IOSTANDARD=LVTTL")
    PORT radio3_RX_ADC_OTRB_pin = radio3_RX_ADC_OTRB, UCF_NET_STRING=("LOC=AF30", "IOSTANDARD=LVTTL")
    PORT radio3_RX_ADC_PWDNA_pin = radio3_RX_ADC_PWDNA, UCF_NET_STRING=("LOC=AD30", "IOSTANDARD=LVTTL")
    PORT radio3_RX_ADC_PWDNB_pin = radio3_RX_ADC_PWDNB, UCF_NET_STRING=("LOC=AF29", "IOSTANDARD=LVTTL")
    PORT radio3_TxEn_pin = radio3_TxEn, UCF_NET_STRING=("LOC=AC34", "IOSTANDARD=LVTTL", "SLEW = SLOW")
    PORT radio3_RxEn_pin = radio3_RxEn, UCF_NET_STRING=("LOC=AL34", "IOSTANDARD=LVTTL", "SLEW = SLOW")
    PORT radio3_RxHP_pin = radio3_RxHP, UCF_NET_STRING=("LOC=AK32", "IOSTANDARD=LVTTL", "SLEW = SLOW")
    PORT radio3_SHDN_pin = radio3_SHDN, UCF_NET_STRING=("LOC=AE30", "IOSTANDARD=LVTTL", "SLEW = SLOW")
    PORT radio3_spi_clk_pin = radio3_spi_clk, UCF_NET_STRING=("LOC=AD33", "IOSTANDARD=LVTTL")
    PORT radio3_spi_cs_pin = radio3_spi_cs, UCF_NET_STRING=("LOC=AC28", "IOSTANDARD=LVTTL")
    PORT radio3_spi_data_pin = radio3_spi_data, UCF_NET_STRING=("LOC=AK38", "IOSTANDARD=LVTTL")

    PORT radio3_b0_pin = radio3_b0, UCF_NET_STRING=("LOC=AJ33", "IOSTANDARD = LVTTL", "SLEW = SLOW") #Radio_B1
    PORT radio3_b1_pin = radio3_b1, UCF_NET_STRING=("LOC=AL37", "IOSTANDARD = LVTTL", "SLEW = SLOW") #Radio_B2
    PORT radio3_b2_pin = radio3_b2, UCF_NET_STRING=("LOC=AK36", "IOSTANDARD = LVTTL", "SLEW = SLOW") #Radio_B3
    PORT radio3_b3_pin = radio3_b3, UCF_NET_STRING=("LOC=AM38", "IOSTANDARD = LVTTL", "SLEW = SLOW") #Radio_B4
    PORT radio3_b4_pin = radio3_b4, UCF_NET_STRING=("LOC=AK37", "IOSTANDARD = LVTTL", "SLEW = SLOW") #Radio_B5
    PORT radio3_b5_pin = radio3_b5, UCF_NET_STRING=("LOC=AJ36", "IOSTANDARD = LVTTL", "SLEW = SLOW") #Radio_B6
    PORT radio3_b6_pin = radio3_b6, UCF_NET_STRING=("LOC=AL38", "IOSTANDARD = LVTTL", "SLEW = SLOW") #Radio_B7

    PORT radio3_DAC_I0_pin = radio3_DAC_I0, UCF_NET_STRING=("LOC=AB30", "IOSTANDARD = LVTTL")
    PORT radio3_DAC_I1_pin = radio3_DAC_I1, UCF_NET_STRING=("LOC=AF38", "IOSTANDARD = LVTTL")
    PORT radio3_DAC_I2_pin = radio3_DAC_I2, UCF_NET_STRING=("LOC=AD37", "IOSTANDARD = LVTTL")
    PORT radio3_DAC_I3_pin = radio3_DAC_I3, UCF_NET_STRING=("LOC=AF37", "IOSTANDARD = LVTTL")
    PORT radio3_DAC_I4_pin = radio3_DAC_I4, UCF_NET_STRING=("LOC=AB34", "IOSTANDARD = LVTTL")
    PORT radio3_DAC_I5_pin = radio3_DAC_I5, UCF_NET_STRING=("LOC=AF39", "IOSTANDARD = LVTTL")
    PORT radio3_DAC_I6_pin = radio3_DAC_I6, UCF_NET_STRING=("LOC=AA30", "IOSTANDARD = LVTTL")
    PORT radio3_DAC_I7_pin = radio3_DAC_I7, UCF_NET_STRING=("LOC=AC35", "IOSTANDARD = LVTTL")
    PORT radio3_DAC_I8_pin = radio3_DAC_I8, UCF_NET_STRING=("LOC=AC36", "IOSTANDARD = LVTTL")
    PORT radio3_DAC_I9_pin = radio3_DAC_I9, UCF_NET_STRING=("LOC=AE38", "IOSTANDARD = LVTTL")
    PORT radio3_DAC_I10_pin = radio3_DAC_I10, UCF_NET_STRING=("LOC=AE36", "IOSTANDARD = LVTTL")
    PORT radio3_DAC_I11_pin = radio3_DAC_I11, UCF_NET_STRING=("LOC=AB36", "IOSTANDARD = LVTTL")
    PORT radio3_DAC_I12_pin = radio3_DAC_I12, UCF_NET_STRING=("LOC=AB33", "IOSTANDARD = LVTTL")
    PORT radio3_DAC_I13_pin = radio3_DAC_I13, UCF_NET_STRING=("LOC=AE39", "IOSTANDARD = LVTTL")
    PORT radio3_DAC_I14_pin = radio3_DAC_I14, UCF_NET_STRING=("LOC=AB35", "IOSTANDARD = LVTTL")
    PORT radio3_DAC_I15_pin = radio3_DAC_I15, UCF_NET_STRING=("LOC=AB32", "IOSTANDARD = LVTTL")

    PORT radio3_DAC_Q0_pin = radio3_DAC_Q0, UCF_NET_STRING=("LOC=AD32", "IOSTANDARD = LVTTL")
    PORT radio3_DAC_Q1_pin = radio3_DAC_Q1, UCF_NET_STRING=("LOC=AK39", "IOSTANDARD = LVTTL")
    PORT radio3_DAC_Q2_pin = radio3_DAC_Q2, UCF_NET_STRING=("LOC=AF34", "IOSTANDARD = LVTTL")
    PORT radio3_DAC_Q3_pin = radio3_DAC_Q3, UCF_NET_STRING=("LOC=AB29", "IOSTANDARD = LVTTL")
    PORT radio3_DAC_Q4_pin = radio3_DAC_Q4, UCF_NET_STRING=("LOC=AC27", "IOSTANDARD = LVTTL")
    PORT radio3_DAC_Q5_pin = radio3_DAC_Q5, UCF_NET_STRING=("LOC=AE34", "IOSTANDARD = LVTTL")
    PORT radio3_DAC_Q6_pin = radio3_DAC_Q6, UCF_NET_STRING=("LOC=AJ37", "IOSTANDARD = LVTTL")
    PORT radio3_DAC_Q7_pin = radio3_DAC_Q7, UCF_NET_STRING=("LOC=AC30", "IOSTANDARD = LVTTL")
    PORT radio3_DAC_Q8_pin = radio3_DAC_Q8, UCF_NET_STRING=("LOC=AH36", "IOSTANDARD = LVTTL")
    PORT radio3_DAC_Q9_pin = radio3_DAC_Q9, UCF_NET_STRING=("LOC=AJ38", "IOSTANDARD = LVTTL")
    PORT radio3_DAC_Q10_pin = radio3_DAC_Q10, UCF_NET_STRING=("LOC=AJ39", "IOSTANDARD = LVTTL")
    PORT radio3_DAC_Q11_pin = radio3_DAC_Q11, UCF_NET_STRING=("LOC=AG39", "IOSTANDARD = LVTTL")
    PORT radio3_DAC_Q12_pin = radio3_DAC_Q12, UCF_NET_STRING=("LOC=AF33", "IOSTANDARD = LVTTL")
    PORT radio3_DAC_Q13_pin = radio3_DAC_Q13, UCF_NET_STRING=("LOC=AH37", "IOSTANDARD = LVTTL")
    PORT radio3_DAC_Q14_pin = radio3_DAC_Q14, UCF_NET_STRING=("LOC=AG34", "IOSTANDARD = LVTTL")
    PORT radio3_DAC_Q15_pin = radio3_DAC_Q15, UCF_NET_STRING=("LOC=AG38", "IOSTANDARD = LVTTL")

    PORT radio3_ADC_I0_pin = radio3_ADC_I0, UCF_NET_STRING=("LOC=AG29", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio3_ADC_I1_pin = radio3_ADC_I1, UCF_NET_STRING=("LOC=AR34", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio3_ADC_I2_pin = radio3_ADC_I2, UCF_NET_STRING=("LOC=AU35", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio3_ADC_I3_pin = radio3_ADC_I3, UCF_NET_STRING=("LOC=AJ21", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio3_ADC_I4_pin = radio3_ADC_I4, UCF_NET_STRING=("LOC=AT32", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio3_ADC_I5_pin = radio3_ADC_I5, UCF_NET_STRING=("LOC=AT34", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio3_ADC_I6_pin = radio3_ADC_I6, UCF_NET_STRING=("LOC=AR33", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio3_ADC_I7_pin = radio3_ADC_I7, UCF_NET_STRING=("LOC=AM36", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio3_ADC_I8_pin = radio3_ADC_I8, UCF_NET_STRING=("LOC=AD28", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio3_ADC_I9_pin = radio3_ADC_I9, UCF_NET_STRING=("LOC=AL33", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio3_ADC_I10_pin = radio3_ADC_I10, UCF_NET_STRING=("LOC=AH32", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio3_ADC_I11_pin = radio3_ADC_I11, UCF_NET_STRING=("LOC=AD29", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio3_ADC_I12_pin = radio3_ADC_I12, UCF_NET_STRING=("LOC=AK33", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio3_ADC_I13_pin = radio3_ADC_I13, UCF_NET_STRING=("LOC=AE31", "IOSTANDARD = LVTTL", "PULLDOWN")

    PORT radio3_ADC_Q0_pin = radio3_ADC_Q0, UCF_NET_STRING=("LOC=AH29", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio3_ADC_Q1_pin = radio3_ADC_Q1, UCF_NET_STRING=("LOC=AK31", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio3_ADC_Q2_pin = radio3_ADC_Q2, UCF_NET_STRING=("LOC=AE28", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio3_ADC_Q3_pin = radio3_ADC_Q3, UCF_NET_STRING=("LOC=AF28", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio3_ADC_Q4_pin = radio3_ADC_Q4, UCF_NET_STRING=("LOC=AE27", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio3_ADC_Q5_pin = radio3_ADC_Q5, UCF_NET_STRING=("LOC=AD27", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio3_ADC_Q6_pin = radio3_ADC_Q6, UCF_NET_STRING=("LOC=AN33", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio3_ADC_Q7_pin = radio3_ADC_Q7, UCF_NET_STRING=("LOC=AL31", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio3_ADC_Q8_pin = radio3_ADC_Q8, UCF_NET_STRING=("LOC=AR32", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio3_ADC_Q9_pin = radio3_ADC_Q9, UCF_NET_STRING=("LOC=AM33", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio3_ADC_Q10_pin = radio3_ADC_Q10, UCF_NET_STRING=("LOC=AG30", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio3_ADC_Q11_pin = radio3_ADC_Q11, UCF_NET_STRING=("LOC=AM32", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio3_ADC_Q12_pin = radio3_ADC_Q12, UCF_NET_STRING=("LOC=AE29", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio3_ADC_Q13_pin = radio3_ADC_Q13, UCF_NET_STRING=("LOC=AN31", "IOSTANDARD = LVTTL", "PULLDOWN")

##Radio Bridge for Slot #4
#   PORT radio4_conv_clk_p = radio4_conv_clk_p, UCF_NET_STRING=("LOC=U32", "IOSTANDARD=LVDCI_33")
    PORT radio4_conv_clk_p = radio4_conv_clk_p, UCF_NET_STRING=("LOC=W30", "IOSTANDARD=LVTTL")
    PORT radio4_EEPROM_IO = radio4_EEPROM_IO, UCF_NET_STRING=("LOC=P32", "IOSTANDARD=LVTTL", "SLEW = SLOW", "DRIVE = 8")
    PORT dac4_spi_clk_pin = dac4_spi_clk, UCF_NET_STRING=("LOC=M38", "IOSTANDARD=LVTTL")
    PORT dac4_spi_cs_pin = dac4_spi_cs, UCF_NET_STRING=("LOC=N34", "IOSTANDARD=LVTTL")
    PORT dac4_spi_data_pin = dac4_spi_data, UCF_NET_STRING=("LOC=L31", "IOSTANDARD=LVTTL")
    PORT radio4_24PA_pin = radio4_24PA, UCF_NET_STRING=("LOC=Y36", "IOSTANDARD=LVTTL", "SLEW = SLOW", "DRIVE = 2")
    PORT radio4_5PA_pin = radio4_5PA, UCF_NET_STRING=("LOC=P35", "IOSTANDARD=LVTTL", "SLEW = SLOW", "DRIVE = 2")
    PORT radio4_ANTSW0_pin = radio4_ANTSW0, UCF_NET_STRING=("LOC=R30", "IOSTANDARD=LVTTL", "SLEW = SLOW", "DRIVE = 2")
    PORT radio4_ANTSW1_pin = radio4_ANTSW1, UCF_NET_STRING=("LOC=R33", "IOSTANDARD=LVTTL", "SLEW = SLOW", "DRIVE = 2")
    PORT radio4_dac4_PLL_LOCK_pin = radio4_dac4_PLL_LOCK, UCF_NET_STRING=("LOC=K36", "IOSTANDARD=LVTTL")
    PORT radio4_dac4_RESET_pin = radio4_dac4_RESET, UCF_NET_STRING=("LOC=N35", "IOSTANDARD=LVTTL")
    PORT radio4_DIPSW0_pin = radio4_DIPSW0, UCF_NET_STRING=("LOC=P36", "IOSTANDARD=LVTTL")
    PORT radio4_DIPSW1_pin = radio4_DIPSW1, UCF_NET_STRING=("LOC=P39", "IOSTANDARD=LVTTL")
    PORT radio4_DIPSW2_pin = radio4_DIPSW2, UCF_NET_STRING=("LOC=P34", "IOSTANDARD=LVTTL")
    PORT radio4_DIPSW3_pin = radio4_DIPSW3, UCF_NET_STRING=("LOC=P37", "IOSTANDARD=LVTTL")
    PORT radio4_LD_pin = radio4_LD, UCF_NET_STRING=("LOC=P33", "IOSTANDARD=LVTTL")
    PORT radio4_LED0_pin = radio4_LED0, UCF_NET_STRING=("LOC=R28", "IOSTANDARD=LVTTL", "SLEW = SLOW", "DRIVE = 2")
    PORT radio4_LED1_pin = radio4_LED1, UCF_NET_STRING=("LOC=V34", "IOSTANDARD=LVTTL", "SLEW = SLOW", "DRIVE = 2")
    PORT radio4_LED2_pin = radio4_LED2, UCF_NET_STRING=("LOC=P31", "IOSTANDARD=LVTTL", "SLEW = SLOW", "DRIVE = 2")
    PORT radio4_rssi_ADC_clk_pin = radio4_rssi_ADC_clk, UCF_NET_STRING=("LOC=U39", "IOSTANDARD=LVTTL")
    PORT radio4_RSSI_ADC_CLAMP_pin = radio4_RSSI_ADC_CLAMP, UCF_NET_STRING=("LOC=K39", "IOSTANDARD=LVTTL")
    PORT radio4_RSSI_ADC_D0_pin = radio4_RSSI_ADC_D0, UCF_NET_STRING=("LOC=F39", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio4_RSSI_ADC_D1_pin = radio4_RSSI_ADC_D1, UCF_NET_STRING=("LOC=D39", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio4_RSSI_ADC_D2_pin = radio4_RSSI_ADC_D2, UCF_NET_STRING=("LOC=J35", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio4_RSSI_ADC_D3_pin = radio4_RSSI_ADC_D3, UCF_NET_STRING=("LOC=K33", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio4_RSSI_ADC_D4_pin = radio4_RSSI_ADC_D4, UCF_NET_STRING=("LOC=K34", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio4_RSSI_ADC_D5_pin = radio4_RSSI_ADC_D5, UCF_NET_STRING=("LOC=K35", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio4_RSSI_ADC_D6_pin = radio4_RSSI_ADC_D6, UCF_NET_STRING=("LOC=J34", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio4_RSSI_ADC_D7_pin = radio4_RSSI_ADC_D7, UCF_NET_STRING=("LOC=K32", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio4_RSSI_ADC_D8_pin = radio4_RSSI_ADC_D8, UCF_NET_STRING=("LOC=K31", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio4_RSSI_ADC_D9_pin = radio4_RSSI_ADC_D9, UCF_NET_STRING=("LOC=G39", "IOSTANDARD=LVTTL", "PULLDOWN")
    PORT radio4_RSSI_ADC_HIZ_pin = radio4_RSSI_ADC_HIZ, UCF_NET_STRING=("LOC=K38", "IOSTANDARD=LVTTL")
    PORT radio4_RSSI_ADC_OTR_pin = radio4_RSSI_ADC_OTR, UCF_NET_STRING=("LOC=J33", "IOSTANDARD=LVTTL")
    PORT radio4_RSSI_ADC_SLEEP_pin = radio4_RSSI_ADC_SLEEP, UCF_NET_STRING=("LOC=M30", "IOSTANDARD=LVTTL")
    PORT radio4_RX_ADC_DCS_pin = radio4_RX_ADC_DCS, UCF_NET_STRING=("LOC=R32", "IOSTANDARD=LVTTL")
    PORT radio4_RX_ADC_DFS_pin = radio4_RX_ADC_DFS, UCF_NET_STRING=("LOC=T34", "IOSTANDARD=LVTTL")
    PORT radio4_RX_ADC_OTRA_pin = radio4_RX_ADC_OTRA, UCF_NET_STRING=("LOC=W37", "IOSTANDARD=LVTTL")
    PORT radio4_RX_ADC_OTRB_pin = radio4_RX_ADC_OTRB, UCF_NET_STRING=("LOC=W31", "IOSTANDARD=LVTTL")
    PORT radio4_RX_ADC_PWDNA_pin = radio4_RX_ADC_PWDNA, UCF_NET_STRING=("LOC=V33", "IOSTANDARD=LVTTL")
    PORT radio4_RX_ADC_PWDNB_pin = radio4_RX_ADC_PWDNB, UCF_NET_STRING=("LOC=T30", "IOSTANDARD=LVTTL")
    PORT radio4_TxEn_pin = radio4_TxEn, UCF_NET_STRING=("LOC=P38", "IOSTANDARD=LVTTL", "SLEW = SLOW")
    PORT radio4_RxEn_pin = radio4_RxEn, UCF_NET_STRING=("LOC=T33", "IOSTANDARD=LVTTL", "SLEW = SLOW")
    PORT radio4_RxHP_pin = radio4_RxHP, UCF_NET_STRING=("LOC=V38", "IOSTANDARD=LVTTL", "SLEW = SLOW")
    PORT radio4_SHDN_pin = radio4_SHDN, UCF_NET_STRING=("LOC=V39", "IOSTANDARD=LVTTL", "SLEW = SLOW")
    PORT radio4_spi_clk_pin = radio4_spi_clk, UCF_NET_STRING=("LOC=N38", "IOSTANDARD=LVTTL")
    PORT radio4_spi_cs_pin = radio4_spi_cs, UCF_NET_STRING=("LOC=N37", "IOSTANDARD=LVTTL")
    PORT radio4_spi_data_pin = radio4_spi_data, UCF_NET_STRING=("LOC=N39", "IOSTANDARD=LVTTL")

    PORT radio4_b0_pin = radio4_b0, UCF_NET_STRING=("LOC=R34", "IOSTANDARD = LVTTL", "SLEW = SLOW") #Radio_B1
    PORT radio4_b1_pin = radio4_b1, UCF_NET_STRING=("LOC=R35", "IOSTANDARD = LVTTL", "SLEW = SLOW") #Radio_B2
    PORT radio4_b2_pin = radio4_b2, UCF_NET_STRING=("LOC=T38", "IOSTANDARD = LVTTL", "SLEW = SLOW") #Radio_B3
    PORT radio4_b3_pin = radio4_b3, UCF_NET_STRING=("LOC=R37", "IOSTANDARD = LVTTL", "SLEW = SLOW") #Radio_B4
    PORT radio4_b4_pin = radio4_b4, UCF_NET_STRING=("LOC=R36", "IOSTANDARD = LVTTL", "SLEW = SLOW") #Radio_B5
    PORT radio4_b5_pin = radio4_b5, UCF_NET_STRING=("LOC=R39", "IOSTANDARD = LVTTL", "SLEW = SLOW") #Radio_B6
    PORT radio4_b6_pin = radio4_b6, UCF_NET_STRING=("LOC=R38", "IOSTANDARD = LVTTL", "SLEW = SLOW") #Radio_B7

    PORT radio4_DAC_I0_pin = radio4_DAC_I0, UCF_NET_STRING=("LOC=H31", "IOSTANDARD = LVTTL")
    PORT radio4_DAC_I1_pin = radio4_DAC_I1, UCF_NET_STRING=("LOC=G31", "IOSTANDARD = LVTTL")
    PORT radio4_DAC_I2_pin = radio4_DAC_I2, UCF_NET_STRING=("LOC=F33", "IOSTANDARD = LVTTL")
    PORT radio4_DAC_I3_pin = radio4_DAC_I3, UCF_NET_STRING=("LOC=E33", "IOSTANDARD = LVTTL")
    PORT radio4_DAC_I4_pin = radio4_DAC_I4, UCF_NET_STRING=("LOC=E38", "IOSTANDARD = LVTTL")
    PORT radio4_DAC_I5_pin = radio4_DAC_I5, UCF_NET_STRING=("LOC=E34", "IOSTANDARD = LVTTL")
    PORT radio4_DAC_I6_pin = radio4_DAC_I6, UCF_NET_STRING=("LOC=D38", "IOSTANDARD = LVTTL")
    PORT radio4_DAC_I7_pin = radio4_DAC_I7, UCF_NET_STRING=("LOC=D35", "IOSTANDARD = LVTTL")
    PORT radio4_DAC_I8_pin = radio4_DAC_I8, UCF_NET_STRING=("LOC=H32", "IOSTANDARD = LVTTL")
    PORT radio4_DAC_I9_pin = radio4_DAC_I9, UCF_NET_STRING=("LOC=D34", "IOSTANDARD = LVTTL")
    PORT radio4_DAC_I10_pin = radio4_DAC_I10, UCF_NET_STRING=("LOC=C35", "IOSTANDARD = LVTTL")
    PORT radio4_DAC_I11_pin = radio4_DAC_I11, UCF_NET_STRING=("LOC=H33", "IOSTANDARD = LVTTL")
    PORT radio4_DAC_I12_pin = radio4_DAC_I12, UCF_NET_STRING=("LOC=J39", "IOSTANDARD = LVTTL")
    PORT radio4_DAC_I13_pin = radio4_DAC_I13, UCF_NET_STRING=("LOC=J38", "IOSTANDARD = LVTTL")
    PORT radio4_DAC_I14_pin = radio4_DAC_I14, UCF_NET_STRING=("LOC=H38", "IOSTANDARD = LVTTL")
    PORT radio4_DAC_I15_pin = radio4_DAC_I15, UCF_NET_STRING=("LOC=J31", "IOSTANDARD = LVTTL")

    PORT radio4_DAC_Q0_pin = radio4_DAC_Q0, UCF_NET_STRING=("LOC=N33", "IOSTANDARD = LVTTL")
    PORT radio4_DAC_Q1_pin = radio4_DAC_Q1, UCF_NET_STRING=("LOC=M37", "IOSTANDARD = LVTTL")
    PORT radio4_DAC_Q2_pin = radio4_DAC_Q2, UCF_NET_STRING=("LOC=M34", "IOSTANDARD = LVTTL")
    PORT radio4_DAC_Q3_pin = radio4_DAC_Q3, UCF_NET_STRING=("LOC=L39", "IOSTANDARD = LVTTL")
    PORT radio4_DAC_Q4_pin = radio4_DAC_Q4, UCF_NET_STRING=("LOC=M36", "IOSTANDARD = LVTTL")
    PORT radio4_DAC_Q5_pin = radio4_DAC_Q5, UCF_NET_STRING=("LOC=N30", "IOSTANDARD = LVTTL")
    PORT radio4_DAC_Q6_pin = radio4_DAC_Q6, UCF_NET_STRING=("LOC=L37", "IOSTANDARD = LVTTL")
    PORT radio4_DAC_Q7_pin = radio4_DAC_Q7, UCF_NET_STRING=("LOC=M33", "IOSTANDARD = LVTTL")
    PORT radio4_DAC_Q8_pin = radio4_DAC_Q8, UCF_NET_STRING=("LOC=L35", "IOSTANDARD = LVTTL")
    PORT radio4_DAC_Q9_pin = radio4_DAC_Q9, UCF_NET_STRING=("LOC=L38", "IOSTANDARD = LVTTL")
    PORT radio4_DAC_Q10_pin = radio4_DAC_Q10, UCF_NET_STRING=("LOC=N31", "IOSTANDARD = LVTTL")
    PORT radio4_DAC_Q11_pin = radio4_DAC_Q11, UCF_NET_STRING=("LOC=L36", "IOSTANDARD = LVTTL")
    PORT radio4_DAC_Q12_pin = radio4_DAC_Q12, UCF_NET_STRING=("LOC=M32", "IOSTANDARD = LVTTL")
    PORT radio4_DAC_Q13_pin = radio4_DAC_Q13, UCF_NET_STRING=("LOC=K37", "IOSTANDARD = LVTTL")
    PORT radio4_DAC_Q14_pin = radio4_DAC_Q14, UCF_NET_STRING=("LOC=L34", "IOSTANDARD = LVTTL")
    PORT radio4_DAC_Q15_pin = radio4_DAC_Q15, UCF_NET_STRING=("LOC=L33", "IOSTANDARD = LVTTL")

    PORT radio4_ADC_I0_pin = radio4_ADC_I0, UCF_NET_STRING=("LOC=Y31", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio4_ADC_I1_pin = radio4_ADC_I1, UCF_NET_STRING=("LOC=Y32", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio4_ADC_I2_pin = radio4_ADC_I2, UCF_NET_STRING=("LOC=W28", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio4_ADC_I3_pin = radio4_ADC_I3, UCF_NET_STRING=("LOC=L21", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio4_ADC_I4_pin = radio4_ADC_I4, UCF_NET_STRING=("LOC=W27", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio4_ADC_I5_pin = radio4_ADC_I5, UCF_NET_STRING=("LOC=V27", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio4_ADC_I6_pin = radio4_ADC_I6, UCF_NET_STRING=("LOC=W29", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio4_ADC_I7_pin = radio4_ADC_I7, UCF_NET_STRING=("LOC=V32", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio4_ADC_I8_pin = radio4_ADC_I8, UCF_NET_STRING=("LOC=W32", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio4_ADC_I9_pin = radio4_ADC_I9, UCF_NET_STRING=("LOC=W35", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio4_ADC_I10_pin = radio4_ADC_I10, UCF_NET_STRING=("LOC=T29", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio4_ADC_I11_pin = radio4_ADC_I11, UCF_NET_STRING=("LOC=V31", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio4_ADC_I12_pin = radio4_ADC_I12, UCF_NET_STRING=("LOC=V35", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio4_ADC_I13_pin = radio4_ADC_I13, UCF_NET_STRING=("LOC=U34", "IOSTANDARD = LVTTL", "PULLDOWN")

    PORT radio4_ADC_Q0_pin = radio4_ADC_Q0, UCF_NET_STRING=("LOC=U36", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio4_ADC_Q1_pin = radio4_ADC_Q1, UCF_NET_STRING=("LOC=U30", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio4_ADC_Q2_pin = radio4_ADC_Q2, UCF_NET_STRING=("LOC=V36", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio4_ADC_Q3_pin = radio4_ADC_Q3, UCF_NET_STRING=("LOC=T32", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio4_ADC_Q4_pin = radio4_ADC_Q4, UCF_NET_STRING=("LOC=V30", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio4_ADC_Q5_pin = radio4_ADC_Q5, UCF_NET_STRING=("LOC=U31", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio4_ADC_Q6_pin = radio4_ADC_Q6, UCF_NET_STRING=("LOC=V37", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio4_ADC_Q7_pin = radio4_ADC_Q7, UCF_NET_STRING=("LOC=W36", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio4_ADC_Q8_pin = radio4_ADC_Q8, UCF_NET_STRING=("LOC=Y33", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio4_ADC_Q9_pin = radio4_ADC_Q9, UCF_NET_STRING=("LOC=W34", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio4_ADC_Q10_pin = radio4_ADC_Q10, UCF_NET_STRING=("LOC=V29", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio4_ADC_Q11_pin = radio4_ADC_Q11, UCF_NET_STRING=("LOC=V28", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio4_ADC_Q12_pin = radio4_ADC_Q12, UCF_NET_STRING=("LOC=W33", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT radio4_ADC_Q13_pin = radio4_ADC_Q13, UCF_NET_STRING=("LOC=T28", "IOSTANDARD = LVTTL", "PULLDOWN")

### Analog Bridge slot1 ###
    PORT analog1_clock_out_pin = analog1_clock_out, UCF_NET_STRING=("LOC=W4", "IOSTANDARD = LVTTL")

    PORT analog1_DAC1_A0_pin = analog1_DAC1_A0, UCF_NET_STRING=("LOC=D5", "IOSTANDARD = LVTTL")
    PORT analog1_DAC1_A1_pin = analog1_DAC1_A1, UCF_NET_STRING=("LOC=K6", "IOSTANDARD = LVTTL")
    PORT analog1_DAC1_A2_pin = analog1_DAC1_A2, UCF_NET_STRING=("LOC=E6", "IOSTANDARD = LVTTL")
    PORT analog1_DAC1_A3_pin = analog1_DAC1_A3, UCF_NET_STRING=("LOC=N10", "IOSTANDARD = LVTTL")
    PORT analog1_DAC1_A4_pin = analog1_DAC1_A4, UCF_NET_STRING=("LOC=K7", "IOSTANDARD = LVTTL")
    PORT analog1_DAC1_A5_pin = analog1_DAC1_A5, UCF_NET_STRING=("LOC=F7", "IOSTANDARD = LVTTL")
    PORT analog1_DAC1_A6_pin = analog1_DAC1_A6, UCF_NET_STRING=("LOC=L8", "IOSTANDARD = LVTTL")
    PORT analog1_DAC1_A7_pin = analog1_DAC1_A7, UCF_NET_STRING=("LOC=H2", "IOSTANDARD = LVTTL")
    PORT analog1_DAC1_A8_pin = analog1_DAC1_A8, UCF_NET_STRING=("LOC=H8", "IOSTANDARD = LVTTL")
    PORT analog1_DAC1_A9_pin = analog1_DAC1_A9, UCF_NET_STRING=("LOC=H7", "IOSTANDARD = LVTTL")
    PORT analog1_DAC1_A10_pin = analog1_DAC1_A10, UCF_NET_STRING=("LOC=L9", "IOSTANDARD = LVTTL")
    PORT analog1_DAC1_A11_pin = analog1_DAC1_A11, UCF_NET_STRING=("LOC=J9", "IOSTANDARD = LVTTL")
    PORT analog1_DAC1_A12_pin = analog1_DAC1_A12, UCF_NET_STRING=("LOC=K8", "IOSTANDARD = LVTTL")
    PORT analog1_DAC1_A13_pin = analog1_DAC1_A13, UCF_NET_STRING=("LOC=J2", "IOSTANDARD = LVTTL")

    PORT analog1_DAC1_B0_pin = analog1_DAC1_B0, UCF_NET_STRING=("LOC=P2", "IOSTANDARD = LVTTL")
    PORT analog1_DAC1_B1_pin = analog1_DAC1_B1, UCF_NET_STRING=("LOC=M3", "IOSTANDARD = LVTTL")
    PORT analog1_DAC1_B2_pin = analog1_DAC1_B2, UCF_NET_STRING=("LOC=N9", "IOSTANDARD = LVTTL")
    PORT analog1_DAC1_B3_pin = analog1_DAC1_B3, UCF_NET_STRING=("LOC=N1", "IOSTANDARD = LVTTL")
    PORT analog1_DAC1_B4_pin = analog1_DAC1_B4, UCF_NET_STRING=("LOC=L6", "IOSTANDARD = LVTTL")
    PORT analog1_DAC1_B5_pin = analog1_DAC1_B5, UCF_NET_STRING=("LOC=N6", "IOSTANDARD = LVTTL")
    PORT analog1_DAC1_B6_pin = analog1_DAC1_B6, UCF_NET_STRING=("LOC=N5", "IOSTANDARD = LVTTL")
    PORT analog1_DAC1_B7_pin = analog1_DAC1_B7, UCF_NET_STRING=("LOC=P1", "IOSTANDARD = LVTTL")
    PORT analog1_DAC1_B8_pin = analog1_DAC1_B8, UCF_NET_STRING=("LOC=P8", "IOSTANDARD = LVTTL")
    PORT analog1_DAC1_B9_pin = analog1_DAC1_B9, UCF_NET_STRING=("LOC=P10", "IOSTANDARD = LVTTL")
    PORT analog1_DAC1_B10_pin = analog1_DAC1_B10, UCF_NET_STRING=("LOC=N3", "IOSTANDARD = LVTTL")
    PORT analog1_DAC1_B11_pin = analog1_DAC1_B11, UCF_NET_STRING=("LOC=P4", "IOSTANDARD = LVTTL")
    PORT analog1_DAC1_B12_pin = analog1_DAC1_B12, UCF_NET_STRING=("LOC=K1", "IOSTANDARD = LVTTL")
    PORT analog1_DAC1_B13_pin = analog1_DAC1_B13, UCF_NET_STRING=("LOC=K2", "IOSTANDARD = LVTTL")

    PORT analog1_DAC2_A0_pin = analog1_DAC2_A0, UCF_NET_STRING=("LOC=M6", "IOSTANDARD = LVTTL")
    PORT analog1_DAC2_A1_pin = analog1_DAC2_A1, UCF_NET_STRING=("LOC=L4", "IOSTANDARD = LVTTL")
    PORT analog1_DAC2_A2_pin = analog1_DAC2_A2, UCF_NET_STRING=("LOC=L5", "IOSTANDARD = LVTTL")
    PORT analog1_DAC2_A3_pin = analog1_DAC2_A3, UCF_NET_STRING=("LOC=M7", "IOSTANDARD = LVTTL")
    PORT analog1_DAC2_A4_pin = analog1_DAC2_A4, UCF_NET_STRING=("LOC=N2", "IOSTANDARD = LVTTL")
    PORT analog1_DAC2_A5_pin = analog1_DAC2_A5, UCF_NET_STRING=("LOC=R11", "IOSTANDARD = LVTTL")
    PORT analog1_DAC2_A6_pin = analog1_DAC2_A6, UCF_NET_STRING=("LOC=M2", "IOSTANDARD = LVTTL")
    PORT analog1_DAC2_A7_pin = analog1_DAC2_A7, UCF_NET_STRING=("LOC=L3", "IOSTANDARD = LVTTL")
    PORT analog1_DAC2_A8_pin = analog1_DAC2_A8, UCF_NET_STRING=("LOC=M10", "IOSTANDARD = LVTTL")
    PORT analog1_DAC2_A9_pin = analog1_DAC2_A9, UCF_NET_STRING=("LOC=M4", "IOSTANDARD = LVTTL")
    PORT analog1_DAC2_A10_pin = analog1_DAC2_A10, UCF_NET_STRING=("LOC=K5", "IOSTANDARD = LVTTL")
    PORT analog1_DAC2_A11_pin = analog1_DAC2_A11, UCF_NET_STRING=("LOC=N7", "IOSTANDARD = LVTTL")
    PORT analog1_DAC2_A12_pin = analog1_DAC2_A12, UCF_NET_STRING=("LOC=L7", "IOSTANDARD = LVTTL")
    PORT analog1_DAC2_A13_pin = analog1_DAC2_A13, UCF_NET_STRING=("LOC=L1", "IOSTANDARD = LVTTL")

    PORT analog1_DAC2_B0_pin = analog1_DAC2_B0, UCF_NET_STRING=("LOC=T3", "IOSTANDARD = LVTTL")
    PORT analog1_DAC2_B1_pin = analog1_DAC2_B1, UCF_NET_STRING=("LOC=T4", "IOSTANDARD = LVTTL")
    PORT analog1_DAC2_B2_pin = analog1_DAC2_B2, UCF_NET_STRING=("LOC=U5", "IOSTANDARD = LVTTL")
    PORT analog1_DAC2_B3_pin = analog1_DAC2_B3, UCF_NET_STRING=("LOC=R10", "IOSTANDARD = LVTTL")
    PORT analog1_DAC2_B4_pin = analog1_DAC2_B4, UCF_NET_STRING=("LOC=V7", "IOSTANDARD = LVTTL")
    PORT analog1_DAC2_B5_pin = analog1_DAC2_B5, UCF_NET_STRING=("LOC=U8", "IOSTANDARD = LVTTL")
    PORT analog1_DAC2_B6_pin = analog1_DAC2_B6, UCF_NET_STRING=("LOC=U1", "IOSTANDARD = LVTTL")
    PORT analog1_DAC2_B7_pin = analog1_DAC2_B7, UCF_NET_STRING=("LOC=R8", "IOSTANDARD = LVTTL")
    PORT analog1_DAC2_B8_pin = analog1_DAC2_B8, UCF_NET_STRING=("LOC=T7", "IOSTANDARD = LVTTL")
    PORT analog1_DAC2_B9_pin = analog1_DAC2_B9, UCF_NET_STRING=("LOC=T6", "IOSTANDARD = LVTTL")
    PORT analog1_DAC2_B10_pin = analog1_DAC2_B10, UCF_NET_STRING=("LOC=U2", "IOSTANDARD = LVTTL")
    PORT analog1_DAC2_B11_pin = analog1_DAC2_B11, UCF_NET_STRING=("LOC=P6", "IOSTANDARD = LVTTL")
    PORT analog1_DAC2_B12_pin = analog1_DAC2_B12, UCF_NET_STRING=("LOC=R3", "IOSTANDARD = LVTTL")
    PORT analog1_DAC2_B13_pin = analog1_DAC2_B13, UCF_NET_STRING=("LOC=P9", "IOSTANDARD = LVTTL")

    PORT analog1_DAC1_sleep_pin = analog1_DAC1_sleep, UCF_NET_STRING=("LOC=J6", "IOSTANDARD = LVTTL")
    PORT analog1_DAC2_sleep_pin = analog1_DAC2_sleep, UCF_NET_STRING=("LOC=J7", "IOSTANDARD = LVTTL")

    PORT analog1_ADC_A0_pin = analog1_ADC_A0, UCF_NET_STRING=("LOC=W7", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog1_ADC_A1_pin = analog1_ADC_A1, UCF_NET_STRING=("LOC=U12", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog1_ADC_A2_pin = analog1_ADC_A2, UCF_NET_STRING=("LOC=T10", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog1_ADC_A3_pin = analog1_ADC_A3, UCF_NET_STRING=("LOC=W8", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog1_ADC_A4_pin = analog1_ADC_A4, UCF_NET_STRING=("LOC=W9", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog1_ADC_A5_pin = analog1_ADC_A5, UCF_NET_STRING=("LOC=W11", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog1_ADC_A6_pin = analog1_ADC_A6, UCF_NET_STRING=("LOC=V10", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog1_ADC_A7_pin = analog1_ADC_A7, UCF_NET_STRING=("LOC=V11", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog1_ADC_A8_pin = analog1_ADC_A8, UCF_NET_STRING=("LOC=Y9", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog1_ADC_A9_pin = analog1_ADC_A9, UCF_NET_STRING=("LOC=Y8", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog1_ADC_A10_pin = analog1_ADC_A10, UCF_NET_STRING=("LOC=T2", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog1_ADC_A11_pin = analog1_ADC_A11, UCF_NET_STRING=("LOC=P3", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog1_ADC_A12_pin = analog1_ADC_A12, UCF_NET_STRING=("LOC=R2", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog1_ADC_A13_pin = analog1_ADC_A13, UCF_NET_STRING=("LOC=W12", "IOSTANDARD = LVTTL", "PULLDOWN")

    PORT analog1_ADC_B0_pin = analog1_ADC_B0, UCF_NET_STRING=("LOC=V2", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog1_ADC_B1_pin = analog1_ADC_B1, UCF_NET_STRING=("LOC=W5", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog1_ADC_B2_pin = analog1_ADC_B2, UCF_NET_STRING=("LOC=P7", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog1_ADC_B3_pin = analog1_ADC_B3, UCF_NET_STRING=("LOC=V1", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog1_ADC_B4_pin = analog1_ADC_B4, UCF_NET_STRING=("LOC=T12", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog1_ADC_B5_pin = analog1_ADC_B5, UCF_NET_STRING=("LOC=P5", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog1_ADC_B6_pin = analog1_ADC_B6, UCF_NET_STRING=("LOC=R7", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog1_ADC_B7_pin = analog1_ADC_B7, UCF_NET_STRING=("LOC=R6", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog1_ADC_B8_pin = analog1_ADC_B8, UCF_NET_STRING=("LOC=W3", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog1_ADC_B9_pin = analog1_ADC_B9, UCF_NET_STRING=("LOC=R9", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog1_ADC_B10_pin = analog1_ADC_B10, UCF_NET_STRING=("LOC=U6", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog1_ADC_B11_pin = analog1_ADC_B11, UCF_NET_STRING=("LOC=W6", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog1_ADC_B12_pin = analog1_ADC_B12, UCF_NET_STRING=("LOC=T8", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog1_ADC_B13_pin = analog1_ADC_B13, UCF_NET_STRING=("LOC=Y7", "IOSTANDARD = LVTTL", "PULLDOWN")

    PORT analog1_ADC_DFS_pin = analog1_ADC_DFS, UCF_NET_STRING=("LOC=V12", "IOSTANDARD = LVTTL")
    PORT analog1_ADC_DCS_pin = analog1_ADC_DCS, UCF_NET_STRING=("LOC=Y4", "IOSTANDARD = LVTTL")
    PORT analog1_ADC_pdwnA_pin = analog1_ADC_pdwnA, UCF_NET_STRING=("LOC=R4", "IOSTANDARD = LVTTL")
    PORT analog1_ADC_pdwnB_pin = analog1_ADC_pdwnB, UCF_NET_STRING=("LOC=W10", "IOSTANDARD = LVTTL")
    PORT analog1_ADC_otrA_pin = analog1_ADC_otrA, UCF_NET_STRING=("LOC=R5", "IOSTANDARD = LVTTL")
    PORT analog1_ADC_otrB_pin = analog1_ADC_otrB, UCF_NET_STRING=("LOC=R1", "IOSTANDARD = LVTTL")
    
    PORT analog1_LED0_pin = analog1_LED0, UCF_NET_STRING=("LOC=D6", "IOSTANDARD = LVTTL")
    PORT analog1_LED1_pin = analog1_LED1, UCF_NET_STRING=("LOC=E3", "IOSTANDARD = LVTTL")
    PORT analog1_LED2_pin = analog1_LED2, UCF_NET_STRING=("LOC=M20", "IOSTANDARD = LVTTL")

### Analog Bridge slot2 ###
    PORT analog2_clock_out_pin = analog2_clock_out, UCF_NET_STRING=("LOC=AM8", "IOSTANDARD = LVTTL")

    PORT analog2_DAC1_A0_pin = analog2_DAC1_A0, UCF_NET_STRING=("LOC=AB1", "IOSTANDARD = LVTTL")
    PORT analog2_DAC1_A1_pin = analog2_DAC1_A1, UCF_NET_STRING=("LOC=AA6", "IOSTANDARD = LVTTL")
    PORT analog2_DAC1_A2_pin = analog2_DAC1_A2, UCF_NET_STRING=("LOC=AA9", "IOSTANDARD = LVTTL")
    PORT analog2_DAC1_A3_pin = analog2_DAC1_A3, UCF_NET_STRING=("LOC=AB2", "IOSTANDARD = LVTTL")
    PORT analog2_DAC1_A4_pin = analog2_DAC1_A4, UCF_NET_STRING=("LOC=AC1", "IOSTANDARD = LVTTL")
    PORT analog2_DAC1_A5_pin = analog2_DAC1_A5, UCF_NET_STRING=("LOC=AA5", "IOSTANDARD = LVTTL")
    PORT analog2_DAC1_A6_pin = analog2_DAC1_A6, UCF_NET_STRING=("LOC=AA8", "IOSTANDARD = LVTTL")
    PORT analog2_DAC1_A7_pin = analog2_DAC1_A7, UCF_NET_STRING=("LOC=AC2", "IOSTANDARD = LVTTL")
    PORT analog2_DAC1_A8_pin = analog2_DAC1_A8, UCF_NET_STRING=("LOC=AA3", "IOSTANDARD = LVTTL")
    PORT analog2_DAC1_A9_pin = analog2_DAC1_A9, UCF_NET_STRING=("LOC=AA4", "IOSTANDARD = LVTTL")
    PORT analog2_DAC1_A10_pin = analog2_DAC1_A10, UCF_NET_STRING=("LOC=AB3", "IOSTANDARD = LVTTL")
    PORT analog2_DAC1_A11_pin = analog2_DAC1_A11, UCF_NET_STRING=("LOC=AA7", "IOSTANDARD = LVTTL")
    PORT analog2_DAC1_A12_pin = analog2_DAC1_A12, UCF_NET_STRING=("LOC=AB6", "IOSTANDARD = LVTTL")
    PORT analog2_DAC1_A13_pin = analog2_DAC1_A13, UCF_NET_STRING=("LOC=AB4", "IOSTANDARD = LVTTL")

    PORT analog2_DAC1_B0_pin = analog2_DAC1_B0, UCF_NET_STRING=("LOC=AF4", "IOSTANDARD = LVTTL")
    PORT analog2_DAC1_B1_pin = analog2_DAC1_B1, UCF_NET_STRING=("LOC=AD6", "IOSTANDARD = LVTTL")
    PORT analog2_DAC1_B2_pin = analog2_DAC1_B2, UCF_NET_STRING=("LOC=AE5", "IOSTANDARD = LVTTL")
    PORT analog2_DAC1_B3_pin = analog2_DAC1_B3, UCF_NET_STRING=("LOC=AK2", "IOSTANDARD = LVTTL")
    PORT analog2_DAC1_B4_pin = analog2_DAC1_B4, UCF_NET_STRING=("LOC=AD7", "IOSTANDARD = LVTTL")
    PORT analog2_DAC1_B5_pin = analog2_DAC1_B5, UCF_NET_STRING=("LOC=AC8", "IOSTANDARD = LVTTL")
    PORT analog2_DAC1_B6_pin = analog2_DAC1_B6, UCF_NET_STRING=("LOC=AC9", "IOSTANDARD = LVTTL")
    PORT analog2_DAC1_B7_pin = analog2_DAC1_B7, UCF_NET_STRING=("LOC=AB7", "IOSTANDARD = LVTTL")
    PORT analog2_DAC1_B8_pin = analog2_DAC1_B8, UCF_NET_STRING=("LOC=AB8", "IOSTANDARD = LVTTL")
    PORT analog2_DAC1_B9_pin = analog2_DAC1_B9, UCF_NET_STRING=("LOC=AC10", "IOSTANDARD = LVTTL")
    PORT analog2_DAC1_B10_pin = analog2_DAC1_B10, UCF_NET_STRING=("LOC=AB9", "IOSTANDARD = LVTTL")
    PORT analog2_DAC1_B11_pin = analog2_DAC1_B11, UCF_NET_STRING=("LOC=AF3", "IOSTANDARD = LVTTL")
    PORT analog2_DAC1_B12_pin = analog2_DAC1_B12, UCF_NET_STRING=("LOC=AL1", "IOSTANDARD = LVTTL")
    PORT analog2_DAC1_B13_pin = analog2_DAC1_B13, UCF_NET_STRING=("LOC=AE4", "IOSTANDARD = LVTTL")

    PORT analog2_DAC2_A0_pin = analog2_DAC2_A0, UCF_NET_STRING=("LOC=AE6", "IOSTANDARD = LVTTL")
    PORT analog2_DAC2_A1_pin = analog2_DAC2_A1, UCF_NET_STRING=("LOC=AD10", "IOSTANDARD = LVTTL")
    PORT analog2_DAC2_A2_pin = analog2_DAC2_A2, UCF_NET_STRING=("LOC=AF5", "IOSTANDARD = LVTTL")
    PORT analog2_DAC2_A3_pin = analog2_DAC2_A3, UCF_NET_STRING=("LOC=AD8", "IOSTANDARD = LVTTL")
    PORT analog2_DAC2_A4_pin = analog2_DAC2_A4, UCF_NET_STRING=("LOC=AK1", "IOSTANDARD = LVTTL")
    PORT analog2_DAC2_A5_pin = analog2_DAC2_A5, UCF_NET_STRING=("LOC=AF6", "IOSTANDARD = LVTTL")
    PORT analog2_DAC2_A6_pin = analog2_DAC2_A6, UCF_NET_STRING=("LOC=AE7", "IOSTANDARD = LVTTL")
    PORT analog2_DAC2_A7_pin = analog2_DAC2_A7, UCF_NET_STRING=("LOC=AC12", "IOSTANDARD = LVTTL")
    PORT analog2_DAC2_A8_pin = analog2_DAC2_A8, UCF_NET_STRING=("LOC=AJ2", "IOSTANDARD = LVTTL")
    PORT analog2_DAC2_A9_pin = analog2_DAC2_A9, UCF_NET_STRING=("LOC=AG5", "IOSTANDARD = LVTTL")
    PORT analog2_DAC2_A10_pin = analog2_DAC2_A10, UCF_NET_STRING=("LOC=AJ1", "IOSTANDARD = LVTTL")
    PORT analog2_DAC2_A11_pin = analog2_DAC2_A11, UCF_NET_STRING=("LOC=AH3", "IOSTANDARD = LVTTL")
    PORT analog2_DAC2_A12_pin = analog2_DAC2_A12, UCF_NET_STRING=("LOC=AH4", "IOSTANDARD = LVTTL")
    PORT analog2_DAC2_A13_pin = analog2_DAC2_A13, UCF_NET_STRING=("LOC=AJ3", "IOSTANDARD = LVTTL")

    PORT analog2_DAC2_B0_pin = analog2_DAC2_B0, UCF_NET_STRING=("LOC=AL6", "IOSTANDARD = LVTTL")
    PORT analog2_DAC2_B1_pin = analog2_DAC2_B1, UCF_NET_STRING=("LOC=AE11", "IOSTANDARD = LVTTL")
    PORT analog2_DAC2_B2_pin = analog2_DAC2_B2, UCF_NET_STRING=("LOC=AL7", "IOSTANDARD = LVTTL")
    PORT analog2_DAC2_B3_pin = analog2_DAC2_B3, UCF_NET_STRING=("LOC=AM4", "IOSTANDARD = LVTTL")
    PORT analog2_DAC2_B4_pin = analog2_DAC2_B4, UCF_NET_STRING=("LOC=AH8", "IOSTANDARD = LVTTL")
    PORT analog2_DAC2_B5_pin = analog2_DAC2_B5, UCF_NET_STRING=("LOC=AE10", "IOSTANDARD = LVTTL")
    PORT analog2_DAC2_B6_pin = analog2_DAC2_B6, UCF_NET_STRING=("LOC=AE9", "IOSTANDARD = LVTTL")
    PORT analog2_DAC2_B7_pin = analog2_DAC2_B7, UCF_NET_STRING=("LOC=AL5", "IOSTANDARD = LVTTL")
    PORT analog2_DAC2_B8_pin = analog2_DAC2_B8, UCF_NET_STRING=("LOC=AK6", "IOSTANDARD = LVTTL")
    PORT analog2_DAC2_B9_pin = analog2_DAC2_B9, UCF_NET_STRING=("LOC=AJ6", "IOSTANDARD = LVTTL")
    PORT analog2_DAC2_B10_pin = analog2_DAC2_B10, UCF_NET_STRING=("LOC=AM3", "IOSTANDARD = LVTTL")
    PORT analog2_DAC2_B11_pin = analog2_DAC2_B11, UCF_NET_STRING=("LOC=AK5", "IOSTANDARD = LVTTL")
    PORT analog2_DAC2_B12_pin = analog2_DAC2_B12, UCF_NET_STRING=("LOC=AF9", "IOSTANDARD = LVTTL")
    PORT analog2_DAC2_B13_pin = analog2_DAC2_B13, UCF_NET_STRING=("LOC=AL3", "IOSTANDARD = LVTTL")

    PORT analog2_DAC1_sleep_pin = analog2_DAC1_sleep, UCF_NET_STRING=("LOC=AD2", "IOSTANDARD = LVTTL")
    PORT analog2_DAC2_sleep_pin = analog2_DAC2_sleep, UCF_NET_STRING=("LOC=AE1", "IOSTANDARD = LVTTL")

    PORT analog2_ADC_A0_pin = analog2_ADC_A0, UCF_NET_STRING=("LOC=AM9", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog2_ADC_A1_pin = analog2_ADC_A1, UCF_NET_STRING=("LOC=AM6", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog2_ADC_A2_pin = analog2_ADC_A2, UCF_NET_STRING=("LOC=AH10", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog2_ADC_A3_pin = analog2_ADC_A3, UCF_NET_STRING=("LOC=AF12", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog2_ADC_A4_pin = analog2_ADC_A4, UCF_NET_STRING=("LOC=AP7", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog2_ADC_A5_pin = analog2_ADC_A5, UCF_NET_STRING=("LOC=AR7", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog2_ADC_A6_pin = analog2_ADC_A6, UCF_NET_STRING=("LOC=AK9", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog2_ADC_A7_pin = analog2_ADC_A7, UCF_NET_STRING=("LOC=AE13", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog2_ADC_A8_pin = analog2_ADC_A8, UCF_NET_STRING=("LOC=AN9", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog2_ADC_A9_pin = analog2_ADC_A9, UCF_NET_STRING=("LOC=AU5", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog2_ADC_A10_pin = analog2_ADC_A10, UCF_NET_STRING=("LOC=AG7", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog2_ADC_A11_pin = analog2_ADC_A11, UCF_NET_STRING=("LOC=AL2", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog2_ADC_A12_pin = analog2_ADC_A12, UCF_NET_STRING=("LOC=AK3", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog2_ADC_A13_pin = analog2_ADC_A13, UCF_NET_STRING=("LOC=AT5", "IOSTANDARD = LVTTL", "PULLDOWN")

    PORT analog2_ADC_B0_pin = analog2_ADC_B0, UCF_NET_STRING=("LOC=AH6", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog2_ADC_B1_pin = analog2_ADC_B1, UCF_NET_STRING=("LOC=AG6", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog2_ADC_B2_pin = analog2_ADC_B2, UCF_NET_STRING=("LOC=AF7", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog2_ADC_B3_pin = analog2_ADC_B3, UCF_NET_STRING=("LOC=AF8", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog2_ADC_B4_pin = analog2_ADC_B4, UCF_NET_STRING=("LOC=AJ5", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog2_ADC_B5_pin = analog2_ADC_B5, UCF_NET_STRING=("LOC=AJ7", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog2_ADC_B6_pin = analog2_ADC_B6, UCF_NET_STRING=("LOC=AD11", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog2_ADC_B7_pin = analog2_ADC_B7, UCF_NET_STRING=("LOC=AF10", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog2_ADC_B8_pin = analog2_ADC_B8, UCF_NET_STRING=("LOC=AE8", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog2_ADC_B9_pin = analog2_ADC_B9, UCF_NET_STRING=("LOC=AF11", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog2_ADC_B10_pin = analog2_ADC_B10, UCF_NET_STRING=("LOC=AJ8", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog2_ADC_B11_pin = analog2_ADC_B11, UCF_NET_STRING=("LOC=AG11", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog2_ADC_B12_pin = analog2_ADC_B12, UCF_NET_STRING=("LOC=AJ9", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog2_ADC_B13_pin = analog2_ADC_B13, UCF_NET_STRING=("LOC=AK7", "IOSTANDARD = LVTTL", "PULLDOWN")

    PORT analog2_ADC_DFS_pin = analog2_ADC_DFS, UCF_NET_STRING=("LOC=AT6", "IOSTANDARD = LVTTL")
    PORT analog2_ADC_DCS_pin = analog2_ADC_DCS, UCF_NET_STRING=("LOC=AH11", "IOSTANDARD = LVTTL")
    PORT analog2_ADC_pdwnA_pin = analog2_ADC_pdwnA, UCF_NET_STRING=("LOC=AM2", "IOSTANDARD = LVTTL")
    PORT analog2_ADC_pdwnB_pin = analog2_ADC_pdwnB, UCF_NET_STRING=("LOC=AD12", "IOSTANDARD = LVTTL")
    PORT analog2_ADC_otrA_pin = analog2_ADC_otrA, UCF_NET_STRING=("LOC=AK4", "IOSTANDARD = LVTTL")
    PORT analog2_ADC_otrB_pin = analog2_ADC_otrB, UCF_NET_STRING=("LOC=AJ4", "IOSTANDARD = LVTTL")
    
    PORT analog2_LED0_pin = analog2_LED0, UCF_NET_STRING=("LOC=AG1", "IOSTANDARD = LVTTL")
    PORT analog2_LED1_pin = analog2_LED1, UCF_NET_STRING=("LOC=AB10", "IOSTANDARD = LVTTL")
    PORT analog2_LED2_pin = analog2_LED2, UCF_NET_STRING=("LOC=AG20", "IOSTANDARD = LVTTL")

### Analog Bridge slot3 ###
    PORT analog3_clock_out_pin = analog3_clock_out, UCF_NET_STRING=("LOC=AG38", "IOSTANDARD = LVTTL")

    PORT analog3_DAC1_A0_pin = analog3_DAC1_A0, UCF_NET_STRING=("LOC=AG33", "IOSTANDARD = LVTTL")
    PORT analog3_DAC1_A1_pin = analog3_DAC1_A1, UCF_NET_STRING=("LOC=AH33", "IOSTANDARD = LVTTL")
    PORT analog3_DAC1_A2_pin = analog3_DAC1_A2, UCF_NET_STRING=("LOC=AE33", "IOSTANDARD = LVTTL")
    PORT analog3_DAC1_A3_pin = analog3_DAC1_A3, UCF_NET_STRING=("LOC=AH34", "IOSTANDARD = LVTTL")
    PORT analog3_DAC1_A4_pin = analog3_DAC1_A4, UCF_NET_STRING=("LOC=AJ34", "IOSTANDARD = LVTTL")
    PORT analog3_DAC1_A5_pin = analog3_DAC1_A5, UCF_NET_STRING=("LOC=AN34", "IOSTANDARD = LVTTL")
    PORT analog3_DAC1_A6_pin = analog3_DAC1_A6, UCF_NET_STRING=("LOC=AK35", "IOSTANDARD = LVTTL")
    PORT analog3_DAC1_A7_pin = analog3_DAC1_A7, UCF_NET_STRING=("LOC=AK34", "IOSTANDARD = LVTTL")
    PORT analog3_DAC1_A8_pin = analog3_DAC1_A8, UCF_NET_STRING=("LOC=AD30", "IOSTANDARD = LVTTL")
    PORT analog3_DAC1_A9_pin = analog3_DAC1_A9, UCF_NET_STRING=("LOC=AG31", "IOSTANDARD = LVTTL")
    PORT analog3_DAC1_A10_pin = analog3_DAC1_A10, UCF_NET_STRING=("LOC=AE31", "IOSTANDARD = LVTTL")
    PORT analog3_DAC1_A11_pin = analog3_DAC1_A11, UCF_NET_STRING=("LOC=AK33", "IOSTANDARD = LVTTL")
    PORT analog3_DAC1_A12_pin = analog3_DAC1_A12, UCF_NET_STRING=("LOC=AH32", "IOSTANDARD = LVTTL")
    PORT analog3_DAC1_A13_pin = analog3_DAC1_A13, UCF_NET_STRING=("LOC=AL33", "IOSTANDARD = LVTTL")

    PORT analog3_DAC1_B0_pin = analog3_DAC1_B0, UCF_NET_STRING=("LOC=AJ35", "IOSTANDARD = LVTTL")
    PORT analog3_DAC1_B1_pin = analog3_DAC1_B1, UCF_NET_STRING=("LOC=AF32", "IOSTANDARD = LVTTL")
    PORT analog3_DAC1_B2_pin = analog3_DAC1_B2, UCF_NET_STRING=("LOC=AF31", "IOSTANDARD = LVTTL")
    PORT analog3_DAC1_B3_pin = analog3_DAC1_B3, UCF_NET_STRING=("LOC=AM37", "IOSTANDARD = LVTTL")
    PORT analog3_DAC1_B4_pin = analog3_DAC1_B4, UCF_NET_STRING=("LOC=AE32", "IOSTANDARD = LVTTL")
    PORT analog3_DAC1_B5_pin = analog3_DAC1_B5, UCF_NET_STRING=("LOC=AJ32", "IOSTANDARD = LVTTL")
    PORT analog3_DAC1_B6_pin = analog3_DAC1_B6, UCF_NET_STRING=("LOC=AL35", "IOSTANDARD = LVTTL")
    PORT analog3_DAC1_B7_pin = analog3_DAC1_B7, UCF_NET_STRING=("LOC=AJ33", "IOSTANDARD = LVTTL")
    PORT analog3_DAC1_B8_pin = analog3_DAC1_B8, UCF_NET_STRING=("LOC=AL37", "IOSTANDARD = LVTTL")
    PORT analog3_DAC1_B9_pin = analog3_DAC1_B9, UCF_NET_STRING=("LOC=AK36", "IOSTANDARD = LVTTL")
    PORT analog3_DAC1_B10_pin = analog3_DAC1_B10, UCF_NET_STRING=("LOC=AM38", "IOSTANDARD = LVTTL")
    PORT analog3_DAC1_B11_pin = analog3_DAC1_B11, UCF_NET_STRING=("LOC=AK37", "IOSTANDARD = LVTTL")
    PORT analog3_DAC1_B12_pin = analog3_DAC1_B12, UCF_NET_STRING=("LOC=AJ36", "IOSTANDARD = LVTTL")
    PORT analog3_DAC1_B13_pin = analog3_DAC1_B13, UCF_NET_STRING=("LOC=AL38", "IOSTANDARD = LVTTL")

    PORT analog3_DAC2_A0_pin = analog3_DAC2_A0, UCF_NET_STRING=("LOC=AK32", "IOSTANDARD = LVTTL")
    PORT analog3_DAC2_A1_pin = analog3_DAC2_A1, UCF_NET_STRING=("LOC=AL34", "IOSTANDARD = LVTTL")
    PORT analog3_DAC2_A2_pin = analog3_DAC2_A2, UCF_NET_STRING=("LOC=AE30", "IOSTANDARD = LVTTL")
    PORT analog3_DAC2_A3_pin = analog3_DAC2_A3, UCF_NET_STRING=("LOC=AH30", "IOSTANDARD = LVTTL")
    PORT analog3_DAC2_A4_pin = analog3_DAC2_A4, UCF_NET_STRING=("LOC=AM34", "IOSTANDARD = LVTTL")
    PORT analog3_DAC2_A5_pin = analog3_DAC2_A5, UCF_NET_STRING=("LOC=AF29", "IOSTANDARD = LVTTL")
    PORT analog3_DAC2_A6_pin = analog3_DAC2_A6, UCF_NET_STRING=("LOC=AH29", "IOSTANDARD = LVTTL")
    PORT analog3_DAC2_A7_pin = analog3_DAC2_A7, UCF_NET_STRING=("LOC=AK31", "IOSTANDARD = LVTTL")
    PORT analog3_DAC2_A8_pin = analog3_DAC2_A8, UCF_NET_STRING=("LOC=AE28", "IOSTANDARD = LVTTL")
    PORT analog3_DAC2_A9_pin = analog3_DAC2_A9, UCF_NET_STRING=("LOC=AF28", "IOSTANDARD = LVTTL")
    PORT analog3_DAC2_A10_pin = analog3_DAC2_A10, UCF_NET_STRING=("LOC=AE27", "IOSTANDARD = LVTTL")
    PORT analog3_DAC2_A11_pin = analog3_DAC2_A11, UCF_NET_STRING=("LOC=AD27", "IOSTANDARD = LVTTL")
    PORT analog3_DAC2_A12_pin = analog3_DAC2_A12, UCF_NET_STRING=("LOC=AN33", "IOSTANDARD = LVTTL")
    PORT analog3_DAC2_A13_pin = analog3_DAC2_A13, UCF_NET_STRING=("LOC=AL31", "IOSTANDARD = LVTTL")

    PORT analog3_DAC2_B0_pin = analog3_DAC2_B0, UCF_NET_STRING=("LOC=AE34", "IOSTANDARD = LVTTL")
    PORT analog3_DAC2_B1_pin = analog3_DAC2_B1, UCF_NET_STRING=("LOC=AC27", "IOSTANDARD = LVTTL")
    PORT analog3_DAC2_B2_pin = analog3_DAC2_B2, UCF_NET_STRING=("LOC=AB29", "IOSTANDARD = LVTTL")
    PORT analog3_DAC2_B3_pin = analog3_DAC2_B3, UCF_NET_STRING=("LOC=AF34", "IOSTANDARD = LVTTL")
    PORT analog3_DAC2_B4_pin = analog3_DAC2_B4, UCF_NET_STRING=("LOC=AK39", "IOSTANDARD = LVTTL")
    PORT analog3_DAC2_B5_pin = analog3_DAC2_B5, UCF_NET_STRING=("LOC=AD32", "IOSTANDARD = LVTTL")
    PORT analog3_DAC2_B6_pin = analog3_DAC2_B6, UCF_NET_STRING=("LOC=AF35", "IOSTANDARD = LVTTL")
    PORT analog3_DAC2_B7_pin = analog3_DAC2_B7, UCF_NET_STRING=("LOC=AC32", "IOSTANDARD = LVTTL")
    PORT analog3_DAC2_B8_pin = analog3_DAC2_B8, UCF_NET_STRING=("LOC=AC31", "IOSTANDARD = LVTTL")
    PORT analog3_DAC2_B9_pin = analog3_DAC2_B9, UCF_NET_STRING=("LOC=AB31", "IOSTANDARD = LVTTL")
    PORT analog3_DAC2_B10_pin = analog3_DAC2_B10, UCF_NET_STRING=("LOC=AE35", "IOSTANDARD = LVTTL")
    PORT analog3_DAC2_B11_pin = analog3_DAC2_B11, UCF_NET_STRING=("LOC=AG35", "IOSTANDARD = LVTTL")
    PORT analog3_DAC2_B12_pin = analog3_DAC2_B12, UCF_NET_STRING=("LOC=AC28", "IOSTANDARD = LVTTL")
    PORT analog3_DAC2_B13_pin = analog3_DAC2_B13, UCF_NET_STRING=("LOC=AD33", "IOSTANDARD = LVTTL")

    PORT analog3_DAC1_sleep_pin = analog3_DAC1_sleep, UCF_NET_STRING=("LOC=AD29", "IOSTANDARD = LVTTL")
    PORT analog3_DAC2_sleep_pin = analog3_DAC2_sleep, UCF_NET_STRING=("LOC=AM36", "IOSTANDARD = LVTTL")

    PORT analog3_ADC_A0_pin = analog3_ADC_A0, UCF_NET_STRING=("LOC=AA35", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog3_ADC_A1_pin = analog3_ADC_A1, UCF_NET_STRING=("LOC=AB32", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog3_ADC_A2_pin = analog3_ADC_A2, UCF_NET_STRING=("LOC=AB35", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog3_ADC_A3_pin = analog3_ADC_A3, UCF_NET_STRING=("LOC=AE39", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog3_ADC_A4_pin = analog3_ADC_A4, UCF_NET_STRING=("LOC=AB33", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog3_ADC_A5_pin = analog3_ADC_A5, UCF_NET_STRING=("LOC=AB36", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog3_ADC_A6_pin = analog3_ADC_A6, UCF_NET_STRING=("LOC=AE36", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog3_ADC_A7_pin = analog3_ADC_A7, UCF_NET_STRING=("LOC=AE38", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog3_ADC_A8_pin = analog3_ADC_A8, UCF_NET_STRING=("LOC=AC36", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog3_ADC_A9_pin = analog3_ADC_A9, UCF_NET_STRING=("LOC=AC35", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog3_ADC_A10_pin = analog3_ADC_A10, UCF_NET_STRING=("LOC=AG37", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog3_ADC_A11_pin = analog3_ADC_A11, UCF_NET_STRING=("LOC=AD34", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog3_ADC_A12_pin = analog3_ADC_A12, UCF_NET_STRING=("LOC=AL39", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog3_ADC_A13_pin = analog3_ADC_A13, UCF_NET_STRING=("LOC=AF37", "IOSTANDARD = LVTTL", "PULLDOWN")

    PORT analog3_ADC_B0_pin = analog3_ADC_B0, UCF_NET_STRING=("LOC=AA32", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog3_ADC_B1_pin = analog3_ADC_B1, UCF_NET_STRING=("LOC=AB39", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog3_ADC_B2_pin = analog3_ADC_B2, UCF_NET_STRING=("LOC=AA37", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog3_ADC_B3_pin = analog3_ADC_B3, UCF_NET_STRING=("LOC=AB38", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog3_ADC_B4_pin = analog3_ADC_B4, UCF_NET_STRING=("LOC=AC39", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog3_ADC_B5_pin = analog3_ADC_B5, UCF_NET_STRING=("LOC=AA36", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog3_ADC_B6_pin = analog3_ADC_B6, UCF_NET_STRING=("LOC=AB37", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog3_ADC_B7_pin = analog3_ADC_B7, UCF_NET_STRING=("LOC=AC38", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog3_ADC_B8_pin = analog3_ADC_B8, UCF_NET_STRING=("LOC=AD36", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog3_ADC_B9_pin = analog3_ADC_B9, UCF_NET_STRING=("LOC=AA33", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog3_ADC_B10_pin = analog3_ADC_B10, UCF_NET_STRING=("LOC=AA34", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog3_ADC_B11_pin = analog3_ADC_B11, UCF_NET_STRING=("LOC=AA31", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog3_ADC_B12_pin = analog3_ADC_B12, UCF_NET_STRING=("LOC=AD38", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog3_ADC_B13_pin = analog3_ADC_B13, UCF_NET_STRING=("LOC=AE37", "IOSTANDARD = LVTTL", "PULLDOWN")

    PORT analog3_ADC_DFS_pin = analog3_ADC_DFS, UCF_NET_STRING=("LOC=AF39", "IOSTANDARD = LVTTL")
    PORT analog3_ADC_DCS_pin = analog3_ADC_DCS, UCF_NET_STRING=("LOC=AB34", "IOSTANDARD = LVTTL")
    PORT analog3_ADC_pdwnA_pin = analog3_ADC_pdwnA, UCF_NET_STRING=("LOC=AC34", "IOSTANDARD = LVTTL")
    PORT analog3_ADC_pdwnB_pin = analog3_ADC_pdwnB, UCF_NET_STRING=("LOC=AA30", "IOSTANDARD = LVTTL")
    PORT analog3_ADC_otrA_pin = analog3_ADC_otrA, UCF_NET_STRING=("LOC=AK38", "IOSTANDARD = LVTTL")
    PORT analog3_ADC_otrB_pin = analog3_ADC_otrB, UCF_NET_STRING=("LOC=AF36", "IOSTANDARD = LVTTL")
    
    PORT analog3_LED0_pin = analog3_LED0, UCF_NET_STRING=("LOC=AT32", "IOSTANDARD = LVTTL")
    PORT analog3_LED1_pin = analog3_LED1, UCF_NET_STRING=("LOC=AU35", "IOSTANDARD = LVTTL")
    PORT analog3_LED2_pin = analog3_LED2, UCF_NET_STRING=("LOC=AJ21", "IOSTANDARD = LVTTL")
    
### Analog Bridge slot4 ###
    PORT analog4_clock_out_pin = analog4_clock_out, UCF_NET_STRING=("LOC=L33", "IOSTANDARD = LVTTL")

    PORT analog4_DAC1_A0_pin = analog4_DAC1_A0, UCF_NET_STRING=("LOC=R30", "IOSTANDARD = LVTTL")
    PORT analog4_DAC1_A1_pin = analog4_DAC1_A1, UCF_NET_STRING=("LOC=R33", "IOSTANDARD = LVTTL")
    PORT analog4_DAC1_A2_pin = analog4_DAC1_A2, UCF_NET_STRING=("LOC=Y36", "IOSTANDARD = LVTTL")
    PORT analog4_DAC1_A3_pin = analog4_DAC1_A3, UCF_NET_STRING=("LOC=P35", "IOSTANDARD = LVTTL")
    PORT analog4_DAC1_A4_pin = analog4_DAC1_A4, UCF_NET_STRING=("LOC=Y37", "IOSTANDARD = LVTTL")
    PORT analog4_DAC1_A5_pin = analog4_DAC1_A5, UCF_NET_STRING=("LOC=R28", "IOSTANDARD = LVTTL")
    PORT analog4_DAC1_A6_pin = analog4_DAC1_A6, UCF_NET_STRING=("LOC=V34", "IOSTANDARD = LVTTL")
    PORT analog4_DAC1_A7_pin = analog4_DAC1_A7, UCF_NET_STRING=("LOC=P31", "IOSTANDARD = LVTTL")
    PORT analog4_DAC1_A8_pin = analog4_DAC1_A8, UCF_NET_STRING=("LOC=V33", "IOSTANDARD = LVTTL")
    PORT analog4_DAC1_A9_pin = analog4_DAC1_A9, UCF_NET_STRING=("LOC=W37", "IOSTANDARD = LVTTL")
    PORT analog4_DAC1_A10_pin = analog4_DAC1_A10, UCF_NET_STRING=("LOC=U34", "IOSTANDARD = LVTTL")
    PORT analog4_DAC1_A11_pin = analog4_DAC1_A11, UCF_NET_STRING=("LOC=V35", "IOSTANDARD = LVTTL")
    PORT analog4_DAC1_A12_pin = analog4_DAC1_A12, UCF_NET_STRING=("LOC=T29", "IOSTANDARD = LVTTL")
    PORT analog4_DAC1_A13_pin = analog4_DAC1_A13, UCF_NET_STRING=("LOC=W35", "IOSTANDARD = LVTTL")

    PORT analog4_DAC1_B0_pin = analog4_DAC1_B0, UCF_NET_STRING=("LOC=T36", "IOSTANDARD = LVTTL")
    PORT analog4_DAC1_B1_pin = analog4_DAC1_B1, UCF_NET_STRING=("LOC=R29", "IOSTANDARD = LVTTL")
    PORT analog4_DAC1_B2_pin = analog4_DAC1_B2, UCF_NET_STRING=("LOC=R31", "IOSTANDARD = LVTTL")
    PORT analog4_DAC1_B3_pin = analog4_DAC1_B3, UCF_NET_STRING=("LOC=U39", "IOSTANDARD = LVTTL")
    PORT analog4_DAC1_B4_pin = analog4_DAC1_B4, UCF_NET_STRING=("LOC=T37", "IOSTANDARD = LVTTL")
    PORT analog4_DAC1_B5_pin = analog4_DAC1_B5, UCF_NET_STRING=("LOC=U35", "IOSTANDARD = LVTTL")
    PORT analog4_DAC1_B6_pin = analog4_DAC1_B6, UCF_NET_STRING=("LOC=U38", "IOSTANDARD = LVTTL")
    PORT analog4_DAC1_B7_pin = analog4_DAC1_B7, UCF_NET_STRING=("LOC=R34", "IOSTANDARD = LVTTL")
    PORT analog4_DAC1_B8_pin = analog4_DAC1_B8, UCF_NET_STRING=("LOC=R35", "IOSTANDARD = LVTTL")
    PORT analog4_DAC1_B9_pin = analog4_DAC1_B9, UCF_NET_STRING=("LOC=T38", "IOSTANDARD = LVTTL")
    PORT analog4_DAC1_B10_pin = analog4_DAC1_B10, UCF_NET_STRING=("LOC=R37", "IOSTANDARD = LVTTL")
    PORT analog4_DAC1_B11_pin = analog4_DAC1_B11, UCF_NET_STRING=("LOC=R36", "IOSTANDARD = LVTTL")
    PORT analog4_DAC1_B12_pin = analog4_DAC1_B12, UCF_NET_STRING=("LOC=R39", "IOSTANDARD = LVTTL")
    PORT analog4_DAC1_B13_pin = analog4_DAC1_B13, UCF_NET_STRING=("LOC=R38", "IOSTANDARD = LVTTL")

    PORT analog4_DAC2_A0_pin = analog4_DAC2_A0, UCF_NET_STRING=("LOC=V38", "IOSTANDARD = LVTTL")
    PORT analog4_DAC2_A1_pin = analog4_DAC2_A1, UCF_NET_STRING=("LOC=T33", "IOSTANDARD = LVTTL")
    PORT analog4_DAC2_A2_pin = analog4_DAC2_A2, UCF_NET_STRING=("LOC=V39", "IOSTANDARD = LVTTL")
    PORT analog4_DAC2_A3_pin = analog4_DAC2_A3, UCF_NET_STRING=("LOC=R32", "IOSTANDARD = LVTTL")
    PORT analog4_DAC2_A4_pin = analog4_DAC2_A4, UCF_NET_STRING=("LOC=T34", "IOSTANDARD = LVTTL")
    PORT analog4_DAC2_A5_pin = analog4_DAC2_A5, UCF_NET_STRING=("LOC=T30", "IOSTANDARD = LVTTL")
    PORT analog4_DAC2_A6_pin = analog4_DAC2_A6, UCF_NET_STRING=("LOC=U36", "IOSTANDARD = LVTTL")
    PORT analog4_DAC2_A7_pin = analog4_DAC2_A7, UCF_NET_STRING=("LOC=U30", "IOSTANDARD = LVTTL")
    PORT analog4_DAC2_A8_pin = analog4_DAC2_A8, UCF_NET_STRING=("LOC=V36", "IOSTANDARD = LVTTL")
    PORT analog4_DAC2_A9_pin = analog4_DAC2_A9, UCF_NET_STRING=("LOC=T32", "IOSTANDARD = LVTTL")
    PORT analog4_DAC2_A10_pin = analog4_DAC2_A10, UCF_NET_STRING=("LOC=V30", "IOSTANDARD = LVTTL")
    PORT analog4_DAC2_A11_pin = analog4_DAC2_A11, UCF_NET_STRING=("LOC=U31", "IOSTANDARD = LVTTL")
    PORT analog4_DAC2_A12_pin = analog4_DAC2_A12, UCF_NET_STRING=("LOC=V37", "IOSTANDARD = LVTTL")
    PORT analog4_DAC2_A13_pin = analog4_DAC2_A13, UCF_NET_STRING=("LOC=W36", "IOSTANDARD = LVTTL")

    PORT analog4_DAC2_B0_pin = analog4_DAC2_B0, UCF_NET_STRING=("LOC=N30", "IOSTANDARD = LVTTL")
    PORT analog4_DAC2_B1_pin = analog4_DAC2_B1, UCF_NET_STRING=("LOC=M36", "IOSTANDARD = LVTTL")
    PORT analog4_DAC2_B2_pin = analog4_DAC2_B2, UCF_NET_STRING=("LOC=L39", "IOSTANDARD = LVTTL")
    PORT analog4_DAC2_B3_pin = analog4_DAC2_B3, UCF_NET_STRING=("LOC=M34", "IOSTANDARD = LVTTL")
    PORT analog4_DAC2_B4_pin = analog4_DAC2_B4, UCF_NET_STRING=("LOC=M37", "IOSTANDARD = LVTTL")
    PORT analog4_DAC2_B5_pin = analog4_DAC2_B5, UCF_NET_STRING=("LOC=N33", "IOSTANDARD = LVTTL")
    PORT analog4_DAC2_B6_pin = analog4_DAC2_B6, UCF_NET_STRING=("LOC=L32", "IOSTANDARD = LVTTL")
    PORT analog4_DAC2_B7_pin = analog4_DAC2_B7, UCF_NET_STRING=("LOC=L31", "IOSTANDARD = LVTTL")
    PORT analog4_DAC2_B8_pin = analog4_DAC2_B8, UCF_NET_STRING=("LOC=M38", "IOSTANDARD = LVTTL")
    PORT analog4_DAC2_B9_pin = analog4_DAC2_B9, UCF_NET_STRING=("LOC=N34", "IOSTANDARD = LVTTL")
    PORT analog4_DAC2_B10_pin = analog4_DAC2_B10, UCF_NET_STRING=("LOC=N35", "IOSTANDARD = LVTTL")
    PORT analog4_DAC2_B11_pin = analog4_DAC2_B11, UCF_NET_STRING=("LOC=P33", "IOSTANDARD = LVTTL")
    PORT analog4_DAC2_B12_pin = analog4_DAC2_B12, UCF_NET_STRING=("LOC=N37", "IOSTANDARD = LVTTL")
    PORT analog4_DAC2_B13_pin = analog4_DAC2_B13, UCF_NET_STRING=("LOC=N38", "IOSTANDARD = LVTTL")

    PORT analog4_DAC1_sleep_pin = analog4_DAC1_sleep, UCF_NET_STRING=("LOC=V31", "IOSTANDARD = LVTTL")
    PORT analog4_DAC2_sleep_pin = analog4_DAC2_sleep, UCF_NET_STRING=("LOC=V32", "IOSTANDARD = LVTTL")

    PORT analog4_ADC_A0_pin = analog4_ADC_A0, UCF_NET_STRING=("LOC=K31", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog4_ADC_A1_pin = analog4_ADC_A1, UCF_NET_STRING=("LOC=J31", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog4_ADC_A2_pin = analog4_ADC_A2, UCF_NET_STRING=("LOC=H38", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog4_ADC_A3_pin = analog4_ADC_A3, UCF_NET_STRING=("LOC=J38", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog4_ADC_A4_pin = analog4_ADC_A4, UCF_NET_STRING=("LOC=J39", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog4_ADC_A5_pin = analog4_ADC_A5, UCF_NET_STRING=("LOC=H33", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog4_ADC_A6_pin = analog4_ADC_A6, UCF_NET_STRING=("LOC=C35", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog4_ADC_A7_pin = analog4_ADC_A7, UCF_NET_STRING=("LOC=D34", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog4_ADC_A8_pin = analog4_ADC_A8, UCF_NET_STRING=("LOC=H32", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog4_ADC_A9_pin = analog4_ADC_A9, UCF_NET_STRING=("LOC=D35", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog4_ADC_A10_pin = analog4_ADC_A10, UCF_NET_STRING=("LOC=P36", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog4_ADC_A11_pin = analog4_ADC_A11, UCF_NET_STRING=("LOC=P39", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog4_ADC_A12_pin = analog4_ADC_A12, UCF_NET_STRING=("LOC=P37", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog4_ADC_A13_pin = analog4_ADC_A13, UCF_NET_STRING=("LOC=E33", "IOSTANDARD = LVTTL", "PULLDOWN")

    PORT analog4_ADC_B0_pin = analog4_ADC_B0, UCF_NET_STRING=("LOC=K39", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog4_ADC_B1_pin = analog4_ADC_B1, UCF_NET_STRING=("LOC=J37", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog4_ADC_B2_pin = analog4_ADC_B2, UCF_NET_STRING=("LOC=M30", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog4_ADC_B3_pin = analog4_ADC_B3, UCF_NET_STRING=("LOC=K38", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog4_ADC_B4_pin = analog4_ADC_B4, UCF_NET_STRING=("LOC=K35", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog4_ADC_B5_pin = analog4_ADC_B5, UCF_NET_STRING=("LOC=K34", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog4_ADC_B6_pin = analog4_ADC_B6, UCF_NET_STRING=("LOC=K33", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog4_ADC_B7_pin = analog4_ADC_B7, UCF_NET_STRING=("LOC=J35", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog4_ADC_B8_pin = analog4_ADC_B8, UCF_NET_STRING=("LOC=D39", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog4_ADC_B9_pin = analog4_ADC_B9, UCF_NET_STRING=("LOC=F39", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog4_ADC_B10_pin = analog4_ADC_B10, UCF_NET_STRING=("LOC=J34", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog4_ADC_B11_pin = analog4_ADC_B11, UCF_NET_STRING=("LOC=K32", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog4_ADC_B12_pin = analog4_ADC_B12, UCF_NET_STRING=("LOC=J33", "IOSTANDARD = LVTTL", "PULLDOWN")
    PORT analog4_ADC_B13_pin = analog4_ADC_B13, UCF_NET_STRING=("LOC=G39", "IOSTANDARD = LVTTL", "PULLDOWN")

    PORT analog4_ADC_DFS_pin = analog4_ADC_DFS, UCF_NET_STRING=("LOC=E34", "IOSTANDARD = LVTTL")
    PORT analog4_ADC_DCS_pin = analog4_ADC_DCS, UCF_NET_STRING=("LOC=E38", "IOSTANDARD = LVTTL")
    PORT analog4_ADC_pdwnA_pin = analog4_ADC_pdwnA, UCF_NET_STRING=("LOC=P38", "IOSTANDARD = LVTTL")
    PORT analog4_ADC_pdwnB_pin = analog4_ADC_pdwnB, UCF_NET_STRING=("LOC=D38", "IOSTANDARD = LVTTL")
    PORT analog4_ADC_otrA_pin = analog4_ADC_otrA, UCF_NET_STRING=("LOC=N39", "IOSTANDARD = LVTTL")
    PORT analog4_ADC_otrB_pin = analog4_ADC_otrB, UCF_NET_STRING=("LOC=P34", "IOSTANDARD = LVTTL")
    
    PORT analog4_LED0_pin = analog4_LED0, UCF_NET_STRING=("LOC=W27", "IOSTANDARD = LVTTL")
    PORT analog4_LED1_pin = analog4_LED1, UCF_NET_STRING=("LOC=W28", "IOSTANDARD = LVTTL")
    PORT analog4_LED2_pin = analog4_LED2, UCF_NET_STRING=("LOC=L21", "IOSTANDARD = LVTTL")

### LED 7Seg0 ###
    PORT SEG_LED0 = CONN_0_SEG1, UCF_NET_STRING=("LOC=AJ26", "IOSTANDARD = LVTTL")
    PORT SEG_LED1 = CONN_0_SEG2, UCF_NET_STRING=("LOC=AH26", "IOSTANDARD = LVTTL")
    PORT SEG_LED2 = CONN_0_SEG3, UCF_NET_STRING=("LOC=AH24", "IOSTANDARD = LVTTL")
    PORT SEG_LED3 = CONN_0_SEG4, UCF_NET_STRING=("LOC=AH25", "IOSTANDARD = LVTTL")
    PORT SEG_LED4 = CONN_0_SEG5, UCF_NET_STRING=("LOC=AH23", "IOSTANDARD = LVTTL")
    PORT SEG_LED5 = CONN_0_SEG6, UCF_NET_STRING=("LOC=AG22", "IOSTANDARD = LVTTL")
    PORT SEG_LED6 = CONN_0_SEG7, UCF_NET_STRING=("LOC=AG23", "IOSTANDARD = LVTTL")

### LED 7Seg1 ###
    PORT SEG_1_LED0 = CONN_1_SEG1, UCF_NET_STRING=("LOC=AG19", "IOSTANDARD = LVTTL")
    PORT SEG_1_LED1 = CONN_1_SEG2, UCF_NET_STRING=("LOC=AG21", "IOSTANDARD = LVTTL")
    PORT SEG_1_LED2 = CONN_1_SEG3, UCF_NET_STRING=("LOC=AH19", "IOSTANDARD = LVTTL")
    PORT SEG_1_LED3 = CONN_1_SEG4, UCF_NET_STRING=("LOC=AJ19", "IOSTANDARD = LVTTL")
    PORT SEG_1_LED4 = CONN_1_SEG5, UCF_NET_STRING=("LOC=AP12", "IOSTANDARD = LVTTL")
    PORT SEG_1_LED5 = CONN_1_SEG6, UCF_NET_STRING=("LOC=AN13", "IOSTANDARD = LVTTL")
    PORT SEG_1_LED6 = CONN_1_SEG7, UCF_NET_STRING=("LOC=AL15", "IOSTANDARD = LVTTL")

### LED ###
    PORT LED0 = CONN_LEDs_LED0, UCF_NET_STRING=("LOC=AJ14", "IOSTANDARD = LVTTL")
    PORT LED1 = CONN_LEDs_LED1, UCF_NET_STRING=("LOC=AM13", "IOSTANDARD = LVTTL")
    PORT LED2 = CONN_LEDs_LED2, UCF_NET_STRING=("LOC=AR12", "IOSTANDARD = LVTTL")
    PORT LED3 = CONN_LEDs_LED3, UCF_NET_STRING=("LOC=AH13", "IOSTANDARD = LVTTL")

### PUSH BUTTONS ###
    PORT PUSHU = CONN_PUSHU, UCF_NET_STRING=("LOC=AJ22", "IOSTANDARD = LVTTL")
    PORT PUSHL = CONN_PUSHL, UCF_NET_STRING=("LOC=AJ15", "IOSTANDARD = LVTTL")
    PORT PUSHR = CONN_PUSHR, UCF_NET_STRING=("LOC=AG18", "IOSTANDARD = LVTTL")
    PORT PUSHC = CONN_PUSHC, UCF_NET_STRING=("LOC=AG17", "IOSTANDARD = LVTTL")

### UART ###
    PORT RXD = CONN_RXD, UCF_NET_STRING=("LOC=AA29", "IOSTANDARD = LVTTL")
    PORT TXD = CONN_TXD, UCF_NET_STRING=("LOC=AA28", "IOSTANDARD = LVTTL")

### SYSACE FLASH ###
    PORT SYSACE_CLK = sysace_clk, UCF_NET_STRING=("LOC=N20", "IOSTANDARD = LVTTL") # Input CLK
# PORT SYSACE_CLK_OE_N = sysace_clk_oe_n, UCF_NET_STRING=("LOC= ", "IOSTANDARD = LVTTL")
    PORT MPA00 = sysace_mpa_0, UCF_NET_STRING=("LOC=N18", "IOSTANDARD = LVTTL")
    PORT MPA01 = sysace_mpa_1, UCF_NET_STRING=("LOC=N17", "IOSTANDARD = LVTTL")
    PORT MPA02 = sysace_mpa_2, UCF_NET_STRING=("LOC=M14", "IOSTANDARD = LVTTL")
    PORT MPA03 = sysace_mpa_3, UCF_NET_STRING=("LOC=M16", "IOSTANDARD = LVTTL")
    PORT MPA04 = sysace_mpa_4, UCF_NET_STRING=("LOC=G11", "IOSTANDARD = LVTTL")
    PORT MPA05 = sysace_mpa_5, UCF_NET_STRING=("LOC=E11", "IOSTANDARD = LVTTL")
    PORT MPA06 = sysace_mpa_6, UCF_NET_STRING=("LOC=F11", "IOSTANDARD = LVTTL")
    PORT MPD00 = sysace_mpd_0, UCF_NET_STRING=("LOC=M17", "IOSTANDARD = LVTTL")
    PORT MPD01 = sysace_mpd_1, UCF_NET_STRING=("LOC=L13", "IOSTANDARD = LVTTL")
    PORT MPD02 = sysace_mpd_2, UCF_NET_STRING=("LOC=K14", "IOSTANDARD = LVTTL")
    PORT MPD03 = sysace_mpd_3, UCF_NET_STRING=("LOC=L12", "IOSTANDARD = LVTTL")
    PORT MPD04 = sysace_mpd_4, UCF_NET_STRING=("LOC=J14", "IOSTANDARD = LVTTL")
    PORT MPD05 = sysace_mpd_5, UCF_NET_STRING=("LOC=K10", "IOSTANDARD = LVTTL")
    PORT MPD06 = sysace_mpd_6, UCF_NET_STRING=("LOC=J10", "IOSTANDARD = LVTTL")
    PORT MPD07 = sysace_mpd_7, UCF_NET_STRING=("LOC=K12", "IOSTANDARD = LVTTL")
    PORT MPD08 = sysace_mpd_8, UCF_NET_STRING=("LOC=H10", "IOSTANDARD = LVTTL")
    PORT MPD09 = sysace_mpd_9, UCF_NET_STRING=("LOC=J12", "IOSTANDARD = LVTTL")
    PORT MPD10 = sysace_mpd_10, UCF_NET_STRING=("LOC=G10", "IOSTANDARD = LVTTL")
    PORT MPD11 = sysace_mpd_11, UCF_NET_STRING=("LOC=K11", "IOSTANDARD = LVTTL")
    PORT MPD12 = sysace_mpd_12, UCF_NET_STRING=("LOC=F10", "IOSTANDARD = LVTTL")
    PORT MPD13 = sysace_mpd_13, UCF_NET_STRING=("LOC=J11", "IOSTANDARD = LVTTL")
    PORT MPD14 = sysace_mpd_14, UCF_NET_STRING=("LOC=H11", "IOSTANDARD = LVTTL")
    PORT MPD15 = sysace_mpd_15, UCF_NET_STRING=("LOC=H12", "IOSTANDARD = LVTTL")
    PORT MPCE  = sysace_mpce, UCF_NET_STRING=("LOC=C10", "IOSTANDARD = LVTTL")
    PORT MPOE  = sysace_mpoe, UCF_NET_STRING=("LOC=M15", "IOSTANDARD = LVTTL")
    PORT MPWE  = sysace_mpwe, UCF_NET_STRING=("LOC=M13", "IOSTANDARD = LVTTL")
    PORT MPIRQ = sysace_mpirq, UCF_NET_STRING=("LOC=E10", "IOSTANDARD = LVTTL")


# FPGA BOARD EEPROM Serial Number and Memory interface
    PORT DQ0 = EEPROM_0_DQ0, UCF_NET_STRING=("LOC=AB28", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 8") 

# 10/100 Ethernet MAC
    PORT PHY_SLW0   = phy_slew0,     UCF_NET_STRING=("LOC=H20", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 8")
    PORT PHY_SLW1   = phy_slew1,     UCF_NET_STRING=("LOC=J22", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 8")
    PORT PHY_RESET  = phy_rst_n,     UCF_NET_STRING=("LOC=J27", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 8")
    PORT PHY_MDINT  = phy_mii_int_n, UCF_NET_STRING=("LOC=G27", "IOSTANDARD = LVTTL")
    PORT PHY_CRS    = phy_crs,       UCF_NET_STRING=("LOC=D29", "IOSTANDARD = LVTTL")
    PORT PHY_COL    = phy_col,       UCF_NET_STRING=("LOC=J26", "IOSTANDARD = LVTTL")
    PORT PHY_TXD3   = phy_tx_data_3, UCF_NET_STRING=("LOC=G26", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 8")
    PORT PHY_TXD2   = phy_tx_data_2, UCF_NET_STRING=("LOC=D26", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 8")
    PORT PHY_TXD1   = phy_tx_data_1, UCF_NET_STRING=("LOC=H23", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 8")
    PORT PHY_TXD0   = phy_tx_data_0, UCF_NET_STRING=("LOC=D22", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 8")
    PORT PHY_TX_EN  = phy_tx_en,     UCF_NET_STRING=("LOC=H22", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 8")
    PORT PHY_TX_CLK = phy_tx_clk,    UCF_NET_STRING=("LOC=F20", "IOSTANDARD = LVTTL")
    PORT PHY_TX_ER  = phy_tx_er,     UCF_NET_STRING=("LOC=H26", "IOSTANDARD = LVTTL")
    PORT PHY_RX_ER  = phy_rx_er,     UCF_NET_STRING=("LOC=F21", "IOSTANDARD = LVTTL")
    PORT PHY_RX_CLK = phy_rx_clk,    UCF_NET_STRING=("LOC=E24", "IOSTANDARD = LVTTL")
    PORT PHY_RX_DV  = phy_dv,        UCF_NET_STRING=("LOC=F22", "IOSTANDARD = LVTTL")
    PORT PHY_RXD0   = phy_rx_data_0, UCF_NET_STRING=("LOC=C22", "IOSTANDARD = LVTTL")
    PORT PHY_RXD1   = phy_rx_data_1, UCF_NET_STRING=("LOC=E21", "IOSTANDARD = LVTTL")
    PORT PHY_RXD2   = phy_rx_data_2, UCF_NET_STRING=("LOC=C21", "IOSTANDARD = LVTTL")
    PORT PHY_RXD3   = phy_rx_data_3, UCF_NET_STRING=("LOC=D23", "IOSTANDARD = LVTTL")
    PORT PHY_MDC    = phy_mii_clk,   UCF_NET_STRING=("LOC=J24", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 8")
    PORT PHY_MDIO   = phy_mii_data,  UCF_NET_STRING=("LOC=C23", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 8")

# 4 Dip Switchs
    PORT SW_0 = SW_0, UCF_NET_STRING=("LOC=Y27", "IOSTANDARD = LVTTL") 
    PORT SW_1 = SW_1, UCF_NET_STRING=("LOC=Y28", "IOSTANDARD = LVTTL") 
    PORT SW_2 = SW_2, UCF_NET_STRING=("LOC=AA27", "IOSTANDARD = LVTTL") 
    PORT SW_3 = SW_3, UCF_NET_STRING=("LOC=Y29", "IOSTANDARD = LVTTL") 

### SRAM0_256Kx32 ###
    PORT SRAM0_OEN = CONN_SRAM0_OEN, UCF_NET_STRING=("LOC=AP15", "IOSTANDARD = LVTTL", "SLEW = FAST", "DRIVE = 8")
    PORT SRAM0_ADV_LDN = CONN_SRAM0_ADV_LDN, UCF_NET_STRING=("LOC=AP14", "IOSTANDARD = LVTTL", "SLEW = FAST", "DRIVE = 8")
    PORT SRAM0_CLOCK = CONN_SRAM0_CLK, UCF_NET_STRING=("LOC=AR15", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 16")
    PORT SRAM0_CKEN = CONN_SRAM0_CKEN, UCF_NET_STRING=("LOC=AH14", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 8")
    PORT SRAM0_CE = CONN_SRAM0_CE, UCF_NET_STRING=("LOC=AP11", "IOSTANDARD = LVTTL")
    PORT SRAM0_BEN_0 = CONN_SRAM0_BEN0,  UCF_NET_STRING=("LOC=AP16", "IOSTANDARD = LVTTL", "SLEW = FAST", "DRIVE = 8")
    PORT SRAM0_BEN_1 = CONN_SRAM0_BEN1,  UCF_NET_STRING=("LOC=AR17", "IOSTANDARD = LVTTL", "SLEW = FAST", "DRIVE = 8")
    PORT SRAM0_BEN_2 = CONN_SRAM0_BEN2,  UCF_NET_STRING=("LOC=AN14", "IOSTANDARD = LVTTL", "SLEW = FAST", "DRIVE = 8")
    PORT SRAM0_BEN_3 = CONN_SRAM0_BEN3,  UCF_NET_STRING=("LOC=AT15", "IOSTANDARD = LVTTL", "SLEW = FAST", "DRIVE = 8")
    PORT SRAM0_WEN = CONN_SRAM0_WEN, UCF_NET_STRING=("LOC=AN15", "IOSTANDARD = LVTTL", "SLEW = FAST", "DRIVE = 8")

    PORT SRAM0_A0 = CONN_SRAM0_A0,   UCF_NET_STRING=("LOC=AL16", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM0_A1 = CONN_SRAM0_A1,   UCF_NET_STRING=("LOC=AH15", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM0_A2 = CONN_SRAM0_A2,   UCF_NET_STRING=("LOC=AL14", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM0_A3 = CONN_SRAM0_A3,   UCF_NET_STRING=("LOC=AM15", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM0_A4 = CONN_SRAM0_A4,   UCF_NET_STRING=("LOC=AM14", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM0_A5 = CONN_SRAM0_A5,   UCF_NET_STRING=("LOC=AT9", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM0_A6 = CONN_SRAM0_A6,   UCF_NET_STRING=("LOC=AU11", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM0_A7 = CONN_SRAM0_A7,   UCF_NET_STRING=("LOC=AN11", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM0_A8 = CONN_SRAM0_A8,   UCF_NET_STRING=("LOC=AN17", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM0_A9 = CONN_SRAM0_A9,   UCF_NET_STRING=("LOC=AH16", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM0_A10 = CONN_SRAM0_A10,   UCF_NET_STRING=("LOC=AR16", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM0_A11 = CONN_SRAM0_A11,   UCF_NET_STRING=("LOC=AU15", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM0_A12 = CONN_SRAM0_A12,   UCF_NET_STRING=("LOC=AP18", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM0_A13 = CONN_SRAM0_A13,   UCF_NET_STRING=("LOC=AJ18", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM0_A14 = CONN_SRAM0_A14,   UCF_NET_STRING=("LOC=AM17", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM0_A15 = CONN_SRAM0_A15,   UCF_NET_STRING=("LOC=AM18", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM0_A16 = CONN_SRAM0_A16,   UCF_NET_STRING=("LOC=AK16", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM0_A17 = CONN_SRAM0_A17,   UCF_NET_STRING=("LOC=AU14", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM0_A18 = CONN_SRAM0_A18,   UCF_NET_STRING=("LOC=AT13", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")

    PORT SRAM0_D0 = CONN_SRAM0_D0,   UCF_NET_STRING=("LOC=AU19", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM0_D1 = CONN_SRAM0_D1,   UCF_NET_STRING=("LOC=AH18", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM0_D2 = CONN_SRAM0_D2,   UCF_NET_STRING=("LOC=AP19", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM0_D3 = CONN_SRAM0_D3,   UCF_NET_STRING=("LOC=AT19", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM0_D4 = CONN_SRAM0_D4,   UCF_NET_STRING=("LOC=AN18", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM0_D5 = CONN_SRAM0_D5,   UCF_NET_STRING=("LOC=AR19", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM0_D6 = CONN_SRAM0_D6,   UCF_NET_STRING=("LOC=AJ17", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM0_D7 = CONN_SRAM0_D7,   UCF_NET_STRING=("LOC=AT18", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM0_D8 = CONN_SRAM0_D8,   UCF_NET_STRING=("LOC=AM19", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM0_D9 = CONN_SRAM0_D9,   UCF_NET_STRING=("LOC=AL19", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM0_D10 = CONN_SRAM0_D10,   UCF_NET_STRING=("LOC=AK18", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM0_D11 = CONN_SRAM0_D11,   UCF_NET_STRING=("LOC=AL18", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM0_D12 = CONN_SRAM0_D12,   UCF_NET_STRING=("LOC=AU17", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM0_D13 = CONN_SRAM0_D13,   UCF_NET_STRING=("LOC=AR18", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM0_D14 = CONN_SRAM0_D14,   UCF_NET_STRING=("LOC=AU18", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM0_D15 = CONN_SRAM0_D15,   UCF_NET_STRING=("LOC=AN19", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM0_D16 = CONN_SRAM0_D16,   UCF_NET_STRING=("LOC=AK12", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM0_D17 = CONN_SRAM0_D17,   UCF_NET_STRING=("LOC=AL12", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM0_D18 = CONN_SRAM0_D18,   UCF_NET_STRING=("LOC=AK14", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM0_D19 = CONN_SRAM0_D19,   UCF_NET_STRING=("LOC=AR14", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM0_D20 = CONN_SRAM0_D20,   UCF_NET_STRING=("LOC=AL11", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM0_D21 = CONN_SRAM0_D21,   UCF_NET_STRING=("LOC=AT11", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM0_D22 = CONN_SRAM0_D22,   UCF_NET_STRING=("LOC=AU10", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM0_D23 = CONN_SRAM0_D23,   UCF_NET_STRING=("LOC=AR11", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM0_D24 = CONN_SRAM0_D24,   UCF_NET_STRING=("LOC=AR13", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM0_D25 = CONN_SRAM0_D25,   UCF_NET_STRING=("LOC=AL13", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM0_D26 = CONN_SRAM0_D26,   UCF_NET_STRING=("LOC=AJ13", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM0_D27 = CONN_SRAM0_D27,   UCF_NET_STRING=("LOC=AM10", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM0_D28 = CONN_SRAM0_D28,   UCF_NET_STRING=("LOC=AJ12", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM0_D29 = CONN_SRAM0_D29,   UCF_NET_STRING=("LOC=AM11", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM0_D30 = CONN_SRAM0_D30,   UCF_NET_STRING=("LOC=AL10", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM0_D31 = CONN_SRAM0_D31,   UCF_NET_STRING=("LOC=AT10", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")


### SRAM1_256Kx32 ###

    PORT SRAM1_OEN = CONN_SRAM1_OEN, UCF_NET_STRING=("LOC=AP25", "IOSTANDARD = LVTTL", "SLEW = FAST", "DRIVE = 8")
    PORT SRAM1_ADV_LDN = CONN_SRAM1_ADV_LDN, UCF_NET_STRING=("LOC=AU26", "IOSTANDARD = LVTTL", "SLEW = FAST", "DRIVE = 8")
    PORT SRAM1_CLOCK = CONN_SRAM1_CLK, UCF_NET_STRING=("LOC=AP24", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 16")
    PORT SRAM1_CKEN = CONN_SRAM1_CKEN, UCF_NET_STRING=("LOC=AR25", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 8")
    PORT SRAM1_BEN_0 = CONN_SRAM1_BEN0,  UCF_NET_STRING=("LOC=AP26", "IOSTANDARD = LVTTL", "SLEW = FAST", "DRIVE = 8")
    PORT SRAM1_BEN_1 = CONN_SRAM1_BEN1,  UCF_NET_STRING=("LOC=AN29", "IOSTANDARD = LVTTL", "SLEW = FAST", "DRIVE = 8")
    PORT SRAM1_BEN_2 = CONN_SRAM1_BEN2,  UCF_NET_STRING=("LOC=AR23", "IOSTANDARD = LVTTL", "SLEW = FAST", "DRIVE = 8")
    PORT SRAM1_BEN_3 = CONN_SRAM1_BEN3,  UCF_NET_STRING=("LOC=AT25", "IOSTANDARD = LVTTL", "SLEW = FAST", "DRIVE = 8")
    PORT SRAM1_WEN = CONN_SRAM1_WEN, UCF_NET_STRING=("LOC=AM24", "IOSTANDARD = LVTTL", "SLEW = FAST", "DRIVE = 8")
    PORT SRAM1_CE = CONN_SRAM1_CE, UCF_NET_STRING=("LOC=AM23", "IOSTANDARD = LVTTL")

    PORT SRAM1_A0 = CONN_SRAM1_A0, UCF_NET_STRING=("LOC=AK25", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM1_A1 = CONN_SRAM1_A1, UCF_NET_STRING=("LOC=AK24", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM1_A2 = CONN_SRAM1_A2, UCF_NET_STRING=("LOC=AU25", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM1_A3 = CONN_SRAM1_A3, UCF_NET_STRING=("LOC=AR24", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM1_A4 = CONN_SRAM1_A4, UCF_NET_STRING=("LOC=AN23", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM1_A5 = CONN_SRAM1_A5, UCF_NET_STRING=("LOC=AH22", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM1_A6 = CONN_SRAM1_A6, UCF_NET_STRING=("LOC=AL23", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM1_A7 = CONN_SRAM1_A7, UCF_NET_STRING=("LOC=AN22", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM1_A8 = CONN_SRAM1_A8, UCF_NET_STRING=("LOC=AT28", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM1_A9 = CONN_SRAM1_A9, UCF_NET_STRING=("LOC=AR28", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM1_A10 = CONN_SRAM1_A10, UCF_NET_STRING=("LOC=AT26", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM1_A11 = CONN_SRAM1_A11, UCF_NET_STRING=("LOC=AL28", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM1_A12 = CONN_SRAM1_A12, UCF_NET_STRING=("LOC=AK29", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM1_A13 = CONN_SRAM1_A13, UCF_NET_STRING=("LOC=AR26", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM1_A14 = CONN_SRAM1_A14, UCF_NET_STRING=("LOC=AH27", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM1_A15 = CONN_SRAM1_A15, UCF_NET_STRING=("LOC=AU29", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM1_A16 = CONN_SRAM1_A16, UCF_NET_STRING=("LOC=AP29", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM1_A17 = CONN_SRAM1_A17, UCF_NET_STRING=("LOC=AJ23", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM1_A18 = CONN_SRAM1_A18, UCF_NET_STRING=("LOC=AP28", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")

    PORT SRAM1_D0 = CONN_SRAM1_D0, UCF_NET_STRING=("LOC=AT31", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM1_D1 = CONN_SRAM1_D1, UCF_NET_STRING=("LOC=AT30", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM1_D2 = CONN_SRAM1_D2, UCF_NET_STRING=("LOC=AL30", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM1_D3 = CONN_SRAM1_D3, UCF_NET_STRING=("LOC=AJ28", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM1_D4 = CONN_SRAM1_D4, UCF_NET_STRING=("LOC=AK28", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM1_D5 = CONN_SRAM1_D5, UCF_NET_STRING=("LOC=AM30", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM1_D6 = CONN_SRAM1_D6, UCF_NET_STRING=("LOC=AR29", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM1_D7 = CONN_SRAM1_D7, UCF_NET_STRING=("LOC=AL29", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM1_D8 = CONN_SRAM1_D8, UCF_NET_STRING=("LOC=AL27", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM1_D9 = CONN_SRAM1_D9, UCF_NET_STRING=("LOC=AM25", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM1_D10 = CONN_SRAM1_D10, UCF_NET_STRING=("LOC=AR31", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM1_D11 = CONN_SRAM1_D11, UCF_NET_STRING=("LOC=AM29", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM1_D12 = CONN_SRAM1_D12, UCF_NET_STRING=("LOC=AN30", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM1_D13 = CONN_SRAM1_D13, UCF_NET_STRING=("LOC=AL25", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM1_D14 = CONN_SRAM1_D14, UCF_NET_STRING=("LOC=AM28", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM1_D15 = CONN_SRAM1_D15, UCF_NET_STRING=("LOC=AU30", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM1_D16 = CONN_SRAM1_D16, UCF_NET_STRING=("LOC=AR22", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM1_D17 = CONN_SRAM1_D17, UCF_NET_STRING=("LOC=AM22", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM1_D18 = CONN_SRAM1_D18, UCF_NET_STRING=("LOC=AT23", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM1_D19 = CONN_SRAM1_D19, UCF_NET_STRING=("LOC=AU22", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM1_D20 = CONN_SRAM1_D20, UCF_NET_STRING=("LOC=AT22", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM1_D21 = CONN_SRAM1_D21, UCF_NET_STRING=("LOC=AL21", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM1_D22 = CONN_SRAM1_D22, UCF_NET_STRING=("LOC=AU21", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM1_D23 = CONN_SRAM1_D23, UCF_NET_STRING=("LOC=AP21", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM1_D24 = CONN_SRAM1_D24, UCF_NET_STRING=("LOC=AT21", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM1_D25 = CONN_SRAM1_D25, UCF_NET_STRING=("LOC=AN21", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM1_D26 = CONN_SRAM1_D26, UCF_NET_STRING=("LOC=AK22", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM1_D27 = CONN_SRAM1_D27, UCF_NET_STRING=("LOC=AP22", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM1_D28 = CONN_SRAM1_D28, UCF_NET_STRING=("LOC=AR21", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM1_D29 = CONN_SRAM1_D29, UCF_NET_STRING=("LOC=AM20", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM1_D30 = CONN_SRAM1_D30, UCF_NET_STRING=("LOC=AK21", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
    PORT SRAM1_D31 = CONN_SRAM1_D31, UCF_NET_STRING=("LOC=AP20", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")

    #USER I/O Board in Slot 1
    #LCD SPI interface
    PORT user_ioboard_slot1_sdi = user_ioboard_slot1_sdi, UCF_NET_STRING=("LOC=W4", "SLEW=SLOW", "IOSTANDARD=LVTTL")
    PORT userio_board_slot1_scl = userio_board_slot1_scl, UCF_NET_STRING=("LOC=V3", "SLEW=SLOW", "IOSTANDARD=LVTTL")
    PORT userio_board_slot1_resetlcd = userio_board_slot1_resetlcd, UCF_NET_STRING=("LOC=V5", "SLEW=SLOW", "IOSTANDARD=LVTTL")
    PORT userio_board_slot1_cs = userio_board_slot1_cs, UCF_NET_STRING=("LOC=V8", "SLEW=SLOW", "IOSTANDARD=LVTTL")

    #Buzzer output
    PORT userio_board_slot1_buzzer = userio_board_slot1_buzzer, UCF_NET_STRING=("LOC=P3", "SLEW=SLOW", "IOSTANDARD=LVTTL")

    #Trackball I/O
    PORT userio_board_slot1_trackball_yscn = userio_board_slot1_trackball_yscn, UCF_NET_STRING=("LOC=T3", "SLEW=SLOW", "IOSTANDARD=LVTTL")
    PORT userio_board_slot1_trackball_sel1 = userio_board_slot1_trackball_sel1, UCF_NET_STRING=("LOC=U4", "SLEW=SLOW", "IOSTANDARD=LVTTL")
    PORT userio_board_slot1_trackball_xscn = userio_board_slot1_trackball_xscn, UCF_NET_STRING=("LOC=V4", "SLEW=SLOW", "IOSTANDARD=LVTTL")
    PORT userio_board_slot1_trackball_sel2 = userio_board_slot1_trackball_sel2, UCF_NET_STRING=("LOC=V6", "SLEW=SLOW", "IOSTANDARD=LVTTL")
    PORT userio_board_slot1_trackball_oyn = userio_board_slot1_trackball_oyn, UCF_NET_STRING=("LOC=T11", "SLEW=SLOW", "IOSTANDARD=LVTTL")
    PORT userio_board_slot1_trackball_oy = userio_board_slot1_trackball_oy, UCF_NET_STRING=("LOC=U9", "SLEW=SLOW", "IOSTANDARD=LVTTL")
    PORT userio_board_slot1_trackball_oxn = userio_board_slot1_trackball_oxn, UCF_NET_STRING=("LOC=U10", "SLEW=SLOW", "IOSTANDARD=LVTTL")
    PORT userio_board_slot1_trackball_ox = userio_board_slot1_trackball_ox, UCF_NET_STRING=("LOC=V9", "SLEW=SLOW", "IOSTANDARD=LVTTL")

    #Eight LEDs
    PORT userio_board_slot1_leds_0 = userio_board_slot1_leds_0, UCF_NET_STRING=("LOC=P10", "SLEW=SLOW", "IOSTANDARD=LVTTL")
    PORT userio_board_slot1_leds_1 = userio_board_slot1_leds_1, UCF_NET_STRING=("LOC=P8", "SLEW=SLOW", "IOSTANDARD=LVTTL")
    PORT userio_board_slot1_leds_2 = userio_board_slot1_leds_2, UCF_NET_STRING=("LOC=P1", "SLEW=SLOW", "IOSTANDARD=LVTTL")
    PORT userio_board_slot1_leds_3 = userio_board_slot1_leds_3, UCF_NET_STRING=("LOC=P2", "SLEW=SLOW", "IOSTANDARD=LVTTL")
    PORT userio_board_slot1_leds_4 = userio_board_slot1_leds_4, UCF_NET_STRING=("LOC=N5", "SLEW=SLOW", "IOSTANDARD=LVTTL")
    PORT userio_board_slot1_leds_5 = userio_board_slot1_leds_5, UCF_NET_STRING=("LOC=M3", "SLEW=SLOW", "IOSTANDARD=LVTTL")
    PORT userio_board_slot1_leds_6 = userio_board_slot1_leds_6, UCF_NET_STRING=("LOC=N6", "SLEW=SLOW", "IOSTANDARD=LVTTL")
    PORT userio_board_slot1_leds_7 = userio_board_slot1_leds_7, UCF_NET_STRING=("LOC=L6", "SLEW=SLOW", "IOSTANDARD=LVTTL")

    #DIP switch
    PORT userio_board_slot1_dip_switch_0 = userio_board_slot1_dip_switch_0, UCF_NET_STRING=("LOC=K2", "SLEW=SLOW", "IOSTANDARD=LVTTL")
    PORT userio_board_slot1_dip_switch_1 = userio_board_slot1_dip_switch_1, UCF_NET_STRING=("LOC=K1", "SLEW=SLOW", "IOSTANDARD=LVTTL")
    PORT userio_board_slot1_dip_switch_2 = userio_board_slot1_dip_switch_2, UCF_NET_STRING=("LOC=P4", "SLEW=SLOW", "IOSTANDARD=LVTTL")
    PORT userio_board_slot1_dip_switch_3 = userio_board_slot1_dip_switch_3, UCF_NET_STRING=("LOC=N3", "SLEW=SLOW", "IOSTANDARD=LVTTL")

    #Six small push buttons
    PORT userio_board_slot1_buttons_small_0 = userio_board_slot1_buttons_small_0, UCF_NET_STRING=("LOC=M2", "SLEW=SLOW", "IOSTANDARD=LVTTL")
    PORT userio_board_slot1_buttons_small_1 = userio_board_slot1_buttons_small_1, UCF_NET_STRING=("LOC=R11", "SLEW=SLOW", "IOSTANDARD=LVTTL")
    PORT userio_board_slot1_buttons_small_2 = userio_board_slot1_buttons_small_2, UCF_NET_STRING=("LOC=N2", "SLEW=SLOW", "IOSTANDARD=LVTTL")
    PORT userio_board_slot1_buttons_small_3 = userio_board_slot1_buttons_small_3, UCF_NET_STRING=("LOC=M7", "SLEW=SLOW", "IOSTANDARD=LVTTL")
    PORT userio_board_slot1_buttons_small_4 = userio_board_slot1_buttons_small_4, UCF_NET_STRING=("LOC=L5", "SLEW=SLOW", "IOSTANDARD=LVTTL")
    PORT userio_board_slot1_buttons_small_5 = userio_board_slot1_buttons_small_5, UCF_NET_STRING=("LOC=L4", "SLEW=SLOW", "IOSTANDARD=LVTTL")

    #Two big push buttons
    PORT userio_board_slot1_buttons_big_0 = userio_board_slot1_buttons_big_0, UCF_NET_STRING=("LOC=R1", "SLEW=SLOW", "IOSTANDARD=LVTTL")
    PORT userio_board_slot1_buttons_big_1 = userio_board_slot1_buttons_big_1, UCF_NET_STRING=("LOC=R2", "SLEW=SLOW", "IOSTANDARD=LVTTL")

END