1 | /** @file w3_mac_phy_regs.h |
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2 | * @brief Platform abstraction header for CPU Low |
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3 | * |
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4 | * This contains code for configuring low-level parameters in the PHY and hardware. |
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5 | * |
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6 | * @copyright Copyright 2013-2019, Mango Communications. All rights reserved. |
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7 | * Distributed under the Mango Communications Reference Design License |
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8 | * See LICENSE.txt included in the design archive or |
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9 | * at http://mangocomm.com/802.11/license |
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10 | * |
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11 | * This file is part of the Mango 802.11 Reference Design (https://mangocomm.com/802.11) |
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12 | */ |
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13 | |
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14 | #ifndef W3_MAC_PHY_REGS_H_ |
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15 | #define W3_MAC_PHY_REGS_H_ |
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16 | |
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17 | /*********************************************************************** |
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18 | * Register renames |
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19 | * |
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20 | * The macros below rename the per-register macros defined in xparameters.h |
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21 | * for the System Generator cores in the 802.11 ref design. Each macro |
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22 | * below encodes the memory address (as seen by CPU Low) for each register |
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23 | * in the PHY Tx, PHY Rx and MAC Hw cores. The low-level MAC and PHY code |
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24 | * access these registers directly with Xil_In/Out32() in order to |
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25 | * minimize latency in time-sensitive polling/update loops in the MAC code. |
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26 | * |
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27 | ***********************************************************************/ |
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28 | |
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29 | /******************************************************************************** |
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30 | * Register definitions for wlan_phy_rx core |
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31 | ********************************************************************************/ |
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32 | #define WLAN_RX_REG_CTRL XPAR_WLAN_PHY_RX_MEMMAP_CONTROL |
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33 | #define WLAN_RX_REG_CFG XPAR_WLAN_PHY_RX_MEMMAP_CONFIG |
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34 | #define WLAN_RX_STATUS XPAR_WLAN_PHY_RX_MEMMAP_STATUS |
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35 | #define WLAN_RX_PKT_BUF_SEL XPAR_WLAN_PHY_RX_MEMMAP_PKT_BUF_SEL |
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36 | #define WLAN_RX_FEC_CFG XPAR_WLAN_PHY_RX_MEMMAP_FEC_CONFIG |
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37 | #define WLAN_RX_LTS_CFG XPAR_WLAN_PHY_RX_MEMMAP_LTS_CORR_CONFIG |
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38 | #define WLAN_RX_LTS_THRESH XPAR_WLAN_PHY_RX_MEMMAP_LTS_CORR_THRESH |
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39 | #define WLAN_RX_LTS_PEAKTYPE_THRESH XPAR_WLAN_PHY_RX_MEMMAP_LTS_CORR_PEAKTYPE_THRESH |
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40 | #define WLAN_RX_FFT_CFG XPAR_WLAN_PHY_RX_MEMMAP_FFT_CONFIG |
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41 | #define WLAN_RX_RSSI_THRESH XPAR_WLAN_PHY_RX_MEMMAP_RSSI_THRESH |
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42 | #define WLAN_RX_PKTDET_RSSI_CFG XPAR_WLAN_PHY_RX_MEMMAP_PKTDET_RSSI_CONFIG |
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43 | #define WLAN_RX_PHY_CCA_CFG XPAR_WLAN_PHY_RX_MEMMAP_PHY_CCA_CONFIG |
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44 | #define WLAN_RX_PKT_RSSI_AB XPAR_WLAN_PHY_RX_MEMMAP_RX_PKT_RSSI_AB |
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45 | #define WLAN_RX_PKT_RSSI_CD XPAR_WLAN_PHY_RX_MEMMAP_RX_PKT_RSSI_CD |
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46 | #define WLAN_RX_PKT_AGC_GAINS XPAR_WLAN_PHY_RX_MEMMAP_RX_PKT_AGC_GAINS |
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47 | #define WLAN_RX_DSSS_CFG XPAR_WLAN_PHY_RX_MEMMAP_DSSS_RX_CONFIG |
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48 | #define WLAN_RX_PKT_DET_OFDM_CFG XPAR_WLAN_PHY_RX_MEMMAP_PKTDET_AUTOCORR_CONFIG |
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49 | #define WLAN_RX_PKT_DET_DSSS_CFG XPAR_WLAN_PHY_RX_MEMMAP_PKTDET_DSSS_CONFIG |
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50 | #define WLAN_RX_PKT_BUF_MAXADDR XPAR_WLAN_PHY_RX_MEMMAP_PKTBUF_MAX_WRITE_ADDR |
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51 | #define WLAN_RX_CFO_EST_TIME_DOMAIN XPAR_WLAN_PHY_RX_MEMMAP_CFO_EST_TIME_DOMAIN |
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52 | #define WLAN_RX_CHAN_EST_SMOOTHING XPAR_WLAN_PHY_RX_MEMMAP_CHAN_EST_SMOOTHING |
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53 | #define WLAN_RX_DSSS_SYNC_WRADDR XPAR_WLAN_PHY_RX_MEMMAP_RAMS_ADDR_WREN |
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54 | #define WLAN_RX_DSSS_SYNC_MASK_DATA XPAR_WLAN_PHY_RX_MEMMAP_MASK_1_RAM_WR_DATA |
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55 | #define WLAN_RX_DSSS_SYNC_TRGT_DATA XPAR_WLAN_PHY_RX_MEMMAP_TARGET_RAM_WR_DATA |
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56 | #define WLAN_RX_PKT_DET_COUNT_OFDM XPAR_WLAN_PHY_RX_MEMMAP_PKT_DET_COUNT_OFDM |
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57 | #define WLAN_RX_PKT_DET_COUNT_DSSS XPAR_WLAN_PHY_RX_MEMMAP_PKT_DET_COUNT_DSSS |
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58 | |
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59 | //----------------------------------------------- |
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60 | // RX CONTROL |
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61 | // |
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62 | #define WLAN_RX_REG_CTRL_RESET 0x00000001 |
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63 | |
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64 | //----------------------------------------------- |
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65 | // RX CONFIG |
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66 | // |
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67 | #define WLAN_RX_REG_CFG_DSSS_RX_EN 0x00000001 // Enable DSSS Rx |
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68 | #define WLAN_RX_REG_CFG_USE_TX_SIG_BLOCK 0x00000002 // Force I/Q/RSSI signals to zero during Tx |
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69 | #define WLAN_RX_REG_CFG_PKT_BUF_WEN_SWAP 0x00000004 // Swap byte order at pkt buf interface |
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70 | #define WLAN_RX_REG_CFG_CHAN_EST_WEN_SWAP 0x00000008 // Swap the order of H est writes per u64 ([0,1] vs [1,0]) |
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71 | #define WLAN_RX_REG_CFG_DSSS_RX_REQ_PKT_DET 0x00000010 // Block DSSS Rx until DSSS pkt det asserts |
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72 | #define WLAN_RX_REG_CFG_CFO_EST_BYPASS 0x00000020 // Bypass time-domain CFO correction |
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73 | #define WLAN_RX_REG_CFG_RECORD_CHAN_EST 0x00000040 // Enable recording channel estimates to the Rx pkt buffer |
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74 | #define WLAN_RX_REG_CFG_SWITCHING_DIV_EN 0x00000080 // Enable switching diversity per-Rx |
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75 | #define WLAN_RX_REG_CFG_DISABLE_OFDM_RX 0x00000100 // Holds OFDM pipeline in reset, blocking all OFDM Rx |
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76 | #define WLAN_RX_REG_CFG_PKT_DET_EN_ANT_A 0x00000200 // Enable pkt detection on RF A |
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77 | #define WLAN_RX_REG_CFG_PKT_DET_EN_ANT_B 0x00000400 // Enable pkt detection on RF B |
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78 | #define WLAN_RX_REG_CFG_PKT_DET_EN_ANT_C 0x00000800 // Enable pkt detection on RF C |
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79 | #define WLAN_RX_REG_CFG_PKT_DET_EN_ANT_D 0x00001000 // Enable pkt detection on RF D |
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80 | #define WLAN_RX_REG_CFG_PKT_DET_EN_EXT 0x00002000 // Enable pkt detection via pkt_det_in port |
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81 | #define WLAN_RX_REG_CFG_PHY_CCA_MODE_SEL 0x00004000 // Selects any(0) or all(1) antenna requirement for PHY CCA BUSY |
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82 | #define WLAN_RX_REG_CFG_ANT_SEL_MASK 0x00018000 // Selects antenna for PHY input when sel div is disabled ([0,1,2,3] = RF[A,B,C,D]) |
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83 | #define WLAN_RX_REG_CFG_MAX_PKT_LEN_MASK 0x001E0000 // Sets max SIGNAL.LENGTH value in kB |
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84 | #define WLAN_RX_REG_CFG_REQ_BOTH_PKT_DET_OFDM 0x00200000 // Requires both auto_corr and RSSI pkt det assertion to start OFDM Rx |
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85 | #define WLAN_RX_REG_CFG_BUSY_HOLD_PKT_DET 0x00400000 // Valid SIGNAL holds pkt det for rate*lengh duration, even if unsupported |
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86 | #define WLAN_RX_REG_CFG_DSSS_ASSERTS_CCA 0x00800000 // DSSS active holds CCA busy |
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87 | #define WLAN_RX_REG_CFG_ENABLE_HTMF_DET 0x01000000 // Enables 11n Rx support; when disabled all Rx are processed as 11a waveforms |
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88 | #define WLAN_RX_REG_CFG_ENABLE_VHT_DET 0x02000000 // Enables VHT phy_mode detections; when disabled VHT waveforms are detected as NONHT |
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89 | #define WLAN_RX_REG_CFG_REQ_BOTH_PKT_DET_DSSS 0x04000000 // Requires both auto_corr and RSSI pkt det assertion to start OFDM Rx |
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90 | #define WLAN_RX_REG_CFG_RESET_PKT_DET_COUNTS 0x08000000 // Resets the pkt det counters |
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91 | #define WLAN_RX_REG_CFG_DSSS_SYNC_PKT_DET_DIS 0x10000000 // Disables pkt det after DSSS Rx finds SYNC without pkt det |
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92 | #define WLAN_RX_REG_CFG_OFDM_RX_REQ_PKT_DET 0x20000000 // Requires pkt det before OFDM Rx (0=Rx on LTF-only allowed) |
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93 | #define WLAN_RX_REG_CFG_ILA_SW_TRIG 0x80000000 // Connected to ChipScope ILA as trigger |
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94 | |
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95 | //----------------------------------------------- |
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96 | // RX STATUS |
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97 | // |
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98 | #define WLAN_RX_REG_STATUS_OFDM_FCS_GOOD 0x00000001 |
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99 | #define WLAN_RX_REG_STATUS_DSSS_FCS_GOOD 0x00000002 |
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100 | #define WLAN_RX_REG_STATUS_ACTIVE_ANT_MASK 0x0000000C // 2-bits: [0,1,2,3] = RF[A,B,C,D] |
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101 | #define WLAN_RX_REG_STATUS_OFDM_PKT_DET_STATUS_MASK 0x000003F0 // 6 bits: [LTF-only, ext, RF D/C/B/A] |
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102 | #define WLAN_RX_REG_STATUS_DSSS_PKT_DET_STATUS_MASK 0x00003C00 // 4 bits: [RF D/C/B/A] |
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103 | |
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104 | |
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105 | #define WLAN_RX_DSSS_SYNC_WREN_MASK_TARGET 0x01000000 |
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106 | #define WLAN_RX_DSSS_SYNC_WREN_MASK_MASK1 0x02000000 |
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107 | |
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108 | |
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109 | /******************************************************************************** |
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110 | * Register definitions for wlan_phy_tx core |
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111 | ********************************************************************************/ |
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112 | #define WLAN_TX_REG_STATUS XPAR_WLAN_PHY_TX_MEMMAP_STATUS |
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113 | #define WLAN_TX_REG_CFG XPAR_WLAN_PHY_TX_MEMMAP_CONFIG |
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114 | #define WLAN_TX_REG_PKT_BUF_SEL XPAR_WLAN_PHY_TX_MEMMAP_PKT_BUF_SEL |
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115 | #define WLAN_TX_REG_SCALING XPAR_WLAN_PHY_TX_MEMMAP_OUTPUT_SCALING |
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116 | #define WLAN_TX_REG_START XPAR_WLAN_PHY_TX_MEMMAP_TX_START |
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117 | #define WLAN_TX_REG_FFT_CFG XPAR_WLAN_PHY_TX_MEMMAP_FFT_CONFIG |
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118 | #define WLAN_TX_REG_TIMING XPAR_WLAN_PHY_TX_MEMMAP_TIMING |
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119 | |
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120 | //----------------------------------------------- |
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121 | // TX CONFIG |
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122 | // |
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123 | #define WLAN_TX_REG_CFG_SET_RC_RXEN 0x00000001 |
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124 | #define WLAN_TX_REG_CFG_RESET_SCRAMBLING_PER_PKT 0x00000002 |
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125 | #define WLAN_TX_REG_CFG_ANT_A_TXEN 0x00000004 |
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126 | #define WLAN_TX_REG_CFG_ANT_B_TXEN 0x00000008 |
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127 | #define WLAN_TX_REG_CFG_ANT_C_TXEN 0x00000010 |
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128 | #define WLAN_TX_REG_CFG_ANT_D_TXEN 0x00000020 |
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129 | #define WLAN_TX_REG_CFG_USE_MAC_ANT_MASKS 0x00000040 |
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130 | #define WLAN_TX_REG_CFG_DELAY_DBG_TX_RUNNING 0x00000080 |
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131 | #define WLAN_TX_REG_CFG_PHY_MODE_SW_TX 0x00007000 |
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132 | #define WLAN_TX_REG_CFG_RESET 0x80000000 |
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133 | |
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134 | //----------------------------------------------- |
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135 | // TX STATUS |
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136 | // |
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137 | #define WLAN_TX_REG_STATUS_TX_RUNNING 0x00000001 |
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138 | |
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139 | //----------------------------------------------- |
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140 | // TX START |
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141 | // |
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142 | #define WLAN_TX_REG_START_DIRECT 0x00000001 |
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143 | #define WLAN_TX_REG_START_VIA_RC 0x00000002 |
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144 | |
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145 | |
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146 | /******************************************************************************** |
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147 | * Register definitions for wlan_mac_hw core |
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148 | ********************************************************************************/ |
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149 | |
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150 | // RO: |
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151 | #define WLAN_MAC_REG_STATUS XPAR_WLAN_MAC_HW_MEMMAP_STATUS |
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152 | #define WLAN_MAC_REG_LATEST_RX_BYTE XPAR_WLAN_MAC_HW_MEMMAP_LATEST_RX_BYTE |
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153 | #define WLAN_MAC_REG_PHY_RX_PHY_HDR_PARAMS XPAR_WLAN_MAC_HW_MEMMAP_PHY_RX_PARAMS |
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154 | #define WLAN_MAC_REG_TX_A_BACKOFF_COUNTER XPAR_WLAN_MAC_HW_MEMMAP_TX_A_BACKOFF_COUNTER |
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155 | #define WLAN_MAC_REG_TX_CD_BACKOFF_COUNTERS XPAR_WLAN_MAC_HW_MEMMAP_TX_CD_BACKOFF_COUNTERS |
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156 | #define WLAN_MAC_REG_RX_TIMESTAMP_LSB XPAR_WLAN_MAC_HW_MEMMAP_RX_START_TIMESTAMP_LSB |
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157 | #define WLAN_MAC_REG_RX_TIMESTAMP_MSB XPAR_WLAN_MAC_HW_MEMMAP_RX_START_TIMESTAMP_MSB |
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158 | #define WLAN_MAC_REG_TX_TIMESTAMP_LSB XPAR_WLAN_MAC_HW_MEMMAP_TX_START_TIMESTAMP_LSB |
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159 | #define WLAN_MAC_REG_TX_TIMESTAMP_MSB XPAR_WLAN_MAC_HW_MEMMAP_TX_START_TIMESTAMP_MSB |
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160 | #define WLAN_MAC_REG_TXRX_TIMESTAMPS_FRAC XPAR_WLAN_MAC_HW_MEMMAP_TXRX_START_TIMESTAMPS_FRAC |
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161 | #define WLAN_MAC_REG_NAV_VALUE XPAR_WLAN_MAC_HW_MEMMAP_NAV_VALUE |
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162 | #define WLAN_MAC_REG_TX_CTRL_STATUS XPAR_WLAN_MAC_HW_MEMMAP_TX_CTRL_STATUS |
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163 | |
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164 | // RW: |
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165 | #define WLAN_MAC_REG_TX_START XPAR_WLAN_MAC_HW_MEMMAP_TX_START |
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166 | #define WLAN_MAC_REG_CALIB_TIMES XPAR_WLAN_MAC_HW_MEMMAP_CALIB_TIMES |
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167 | #define WLAN_MAC_REG_IFS_1 XPAR_WLAN_MAC_HW_MEMMAP_IFS_INTERVALS1 |
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168 | #define WLAN_MAC_REG_IFS_2 XPAR_WLAN_MAC_HW_MEMMAP_IFS_INTERVALS2 |
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169 | #define WLAN_MAC_REG_CONTROL XPAR_WLAN_MAC_HW_MEMMAP_CONTROL |
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170 | #define WLAN_MAC_REG_SW_BACKOFF_CTRL XPAR_WLAN_MAC_HW_MEMMAP_BACKOFF_CTRL |
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171 | #define WLAN_MAC_REG_TX_CTRL_A_PARAMS XPAR_WLAN_MAC_HW_MEMMAP_TX_CTRL_A_PARAMS |
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172 | #define WLAN_MAC_REG_TX_CTRL_A_GAINS XPAR_WLAN_MAC_HW_MEMMAP_TX_CTRL_A_GAINS |
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173 | #define WLAN_MAC_REG_TX_CTRL_B_PARAMS XPAR_WLAN_MAC_HW_MEMMAP_TX_CTRL_B_PARAMS |
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174 | #define WLAN_MAC_REG_TX_CTRL_B_GAINS XPAR_WLAN_MAC_HW_MEMMAP_TX_CTRL_B_GAINS |
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175 | #define WLAN_MAC_REG_TX_CTRL_C_PARAMS XPAR_WLAN_MAC_HW_MEMMAP_TX_CTRL_C_PARAMS |
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176 | #define WLAN_MAC_REG_TX_CTRL_C_GAINS XPAR_WLAN_MAC_HW_MEMMAP_TX_CTRL_C_GAINS |
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177 | #define WLAN_MAC_REG_TX_CTRL_D_PARAMS XPAR_WLAN_MAC_HW_MEMMAP_TX_CTRL_D_PARAMS |
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178 | #define WLAN_MAC_REG_TX_CTRL_D_GAINS XPAR_WLAN_MAC_HW_MEMMAP_TX_CTRL_D_GAINS |
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179 | #define WLAN_MAC_REG_POST_TX_TIMERS XPAR_WLAN_MAC_HW_MEMMAP_POST_TX_TIMERS |
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180 | #define WLAN_MAC_REG_POST_RX_TIMERS XPAR_WLAN_MAC_HW_MEMMAP_POST_RX_TIMERS |
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181 | #define WLAN_MAC_REG_NAV_CHECK_ADDR_1 XPAR_WLAN_MAC_HW_MEMMAP_NAV_MATCH_ADDR_1 |
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182 | #define WLAN_MAC_REG_NAV_CHECK_ADDR_2 XPAR_WLAN_MAC_HW_MEMMAP_NAV_MATCH_ADDR_2 |
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183 | #define WLAN_MAC_REG_TU_TARGET_LSB XPAR_WLAN_MAC_HW_MEMMAP_TU_TARGET_LSB |
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184 | #define WLAN_MAC_REG_TU_TARGET_MSB XPAR_WLAN_MAC_HW_MEMMAP_TU_TARGET_MSB |
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185 | |
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186 | //----------------------------------------------- |
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187 | // WLAN MAC HW - Tx/Rx timer bit masks / macros |
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188 | // |
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189 | #define WLAN_MAC_POST_TX_TIMERS_MASK_TIMER1_COUNTTO 0x00007FFF |
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190 | #define WLAN_MAC_POST_TX_TIMERS_MASK_TIMER1_EN 0x00008000 |
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191 | #define WLAN_MAC_POST_TX_TIMERS_MASK_TIMER2_COUNTTO 0x7FFF0000 |
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192 | #define WLAN_MAC_POST_TX_TIMERS_MASK_TIMER2_EN 0x80000000 |
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193 | |
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194 | #define WLAN_MAC_POST_RX_TIMERS_MASK_TIMER1_COUNTTO 0x00007FFF |
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195 | #define WLAN_MAC_POST_RX_TIMERS_MASK_TIMER1_EN 0x00008000 |
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196 | #define WLAN_MAC_POST_RX_TIMERS_MASK_TIMER2_COUNTTO 0x7FFF0000 |
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197 | #define WLAN_MAC_POST_RX_TIMERS_MASK_TIMER2_EN 0x80000000 |
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198 | |
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199 | |
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200 | // WLAN MAC HW - TX_CTRL_STATUS register bit masks |
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201 | #define WLAN_MAC_TXCTRL_STATUS_MASK_TX_A_PENDING 0x00000001 // b[0] |
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202 | #define WLAN_MAC_TXCTRL_STATUS_MASK_TX_A_DONE 0x00000002 // b[1] |
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203 | #define WLAN_MAC_TXCTRL_STATUS_MASK_TX_A_RESULT 0x0000000C // b[3:2] |
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204 | #define WLAN_MAC_TXCTRL_STATUS_MASK_TX_A_STATE 0x00000070 // b[6:4] |
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205 | #define WLAN_MAC_TXCTRL_STATUS_MASK_TX_B_PENDING 0x00000080 // b[7] |
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206 | #define WLAN_MAC_TXCTRL_STATUS_MASK_TX_B_DONE 0x00000100 // b[8] |
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207 | #define WLAN_MAC_TXCTRL_STATUS_MASK_TX_B_RESULT 0x00000600 // b[10:9] |
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208 | #define WLAN_MAC_TXCTRL_STATUS_MASK_TX_B_STATE 0x00003800 // b[13:11] |
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209 | #define WLAN_MAC_TXCTRL_STATUS_MASK_TX_C_PENDING 0x00004000 // b[14] |
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210 | #define WLAN_MAC_TXCTRL_STATUS_MASK_TX_C_DONE 0x00008000 // b[15] |
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211 | #define WLAN_MAC_TXCTRL_STATUS_MASK_TX_C_STATE 0x00070000 // b[18:16] |
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212 | #define WLAN_MAC_TXCTRL_STATUS_MASK_TX_D_PENDING 0x00080000 // b[19] |
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213 | #define WLAN_MAC_TXCTRL_STATUS_MASK_TX_D_DONE 0x00100000 // b[20] |
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214 | #define WLAN_MAC_TXCTRL_STATUS_MASK_TX_D_STATE 0x00E00000 // b[23:21] |
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215 | #define WLAN_MAC_TXCTRL_STATUS_MASK_POSTTX_TIMER2_RUNNING 0x01000000 // b[24] |
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216 | #define WLAN_MAC_TXCTRL_STATUS_MASK_POSTTX_TIMER1_RUNNING 0x02000000 // b[25] |
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217 | #define WLAN_MAC_TXCTRL_STATUS_MASK_POSTRX_TIMER2_RUNNING 0x04000000 // b[26] |
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218 | #define WLAN_MAC_TXCTRL_STATUS_MASK_POSTRX_TIMER1_RUNNING 0x08000000 // b[27] |
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219 | |
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220 | #define WLAN_MAC_TXCTRL_STATUS_TX_A_RESULT_NONE (0 << 2) // FSM idle or still running |
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221 | #define WLAN_MAC_TXCTRL_STATUS_TX_A_RESULT_TIMEOUT (1 << 2) // FSM completed with postTx timer expiration |
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222 | #define WLAN_MAC_TXCTRL_STATUS_TX_A_RESULT_RX_STARTED (2 << 2) // FSM completed with PHY Rx starting |
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223 | |
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224 | #define WLAN_MAC_TXCTRL_STATUS_TX_A_STATE_IDLE (0 << 4) |
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225 | #define WLAN_MAC_TXCTRL_STATUS_TX_A_STATE_PRE_TX_WAIT (1 << 4) |
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226 | #define WLAN_MAC_TXCTRL_STATUS_TX_A_STATE_START_BO (2 << 4) |
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227 | #define WLAN_MAC_TXCTRL_STATUS_TX_A_STATE_DEFER (3 << 4) |
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228 | #define WLAN_MAC_TXCTRL_STATUS_TX_A_STATE_DO_TX (4 << 4) |
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229 | #define WLAN_MAC_TXCTRL_STATUS_TX_A_STATE_POST_TX (5 << 4) |
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230 | #define WLAN_MAC_TXCTRL_STATUS_TX_A_STATE_POST_TX_WAIT (6 << 4) |
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231 | #define WLAN_MAC_TXCTRL_STATUS_TX_A_STATE_DONE (7 << 4) |
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232 | |
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233 | #define WLAN_MAC_TXCTRL_STATUS_TX_B_RESULT_NONE (0 << 9) // FSM idle or still running |
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234 | #define WLAN_MAC_TXCTRL_STATUS_TX_B_RESULT_DID_TX (1 << 9) // FSM completed with PHY Tx |
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235 | #define WLAN_MAC_TXCTRL_STATUS_TX_B_RESULT_NO_TX (2 << 9) // FSM completed, skipped PHY Tx |
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236 | |
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237 | #define WLAN_MAC_TXCTRL_STATUS_TX_B_STATE_IDLE (0 << 11) |
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238 | #define WLAN_MAC_TXCTRL_STATUS_TX_B_STATE_PRE_TX_WAIT (1 << 11) |
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239 | #define WLAN_MAC_TXCTRL_STATUS_TX_B_STATE_CHECK_NAV (2 << 11) |
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240 | #define WLAN_MAC_TXCTRL_STATUS_TX_B_STATE_DO_TX (3 << 11) |
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241 | #define WLAN_MAC_TXCTRL_STATUS_TX_B_STATE_DONE (4 << 11) |
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242 | |
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243 | #define WLAN_MAC_TXCTRL_STATUS_TX_C_STATE_IDLE (0 << 16) |
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244 | #define WLAN_MAC_TXCTRL_STATUS_TX_C_STATE_START_BO (1 << 16) //Starting backoff counter - 1 cycle |
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245 | #define WLAN_MAC_TXCTRL_STATUS_TX_C_STATE_DEFER (2 << 16) //Waiting for zero backoff - unbounded time |
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246 | #define WLAN_MAC_TXCTRL_STATUS_TX_C_STATE_DO_TX (3 << 16) //PHY Tx started, waiting on TX_DONE - TX_TIME |
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247 | #define WLAN_MAC_TXCTRL_STATUS_TX_C_STATE_DONE (4 << 16) //TX_DONE occurred - 1 cycle |
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248 | |
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249 | #define WLAN_MAC_TXCTRL_STATUS_TX_D_STATE_IDLE (0 << 21) |
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250 | #define WLAN_MAC_TXCTRL_STATUS_TX_D_STATE_START_BO (1 << 21) //Starting backoff counter - 1 cycle |
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251 | #define WLAN_MAC_TXCTRL_STATUS_TX_D_STATE_DEFER (2 << 21) //Waiting for zero backoff - unbounded time |
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252 | #define WLAN_MAC_TXCTRL_STATUS_TX_D_STATE_DO_TX (3 << 21) //PHY Tx started, waiting on TX_DONE - TX_TIME |
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253 | #define WLAN_MAC_TXCTRL_STATUS_TX_D_STATE_DONE (4 << 21) //TX_DONE occurred - 1 cycle |
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254 | |
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255 | #define wlan_mac_get_tx_ctrl_status() (Xil_In32(WLAN_MAC_REG_TX_CTRL_STATUS)) |
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256 | |
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257 | // WLAN MAC HW - STATUS register bit masks |
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258 | #define WLAN_MAC_STATUS_MASK_TX_A_PENDING 0x00000001 // b[0] |
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259 | #define WLAN_MAC_STATUS_MASK_TX_A_DONE 0x00000002 // b[1] |
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260 | #define WLAN_MAC_STATUS_MASK_TX_B_PENDING 0x00000004 // b[2] |
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261 | #define WLAN_MAC_STATUS_MASK_TX_B_DONE 0x00000008 // b[3] |
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262 | #define WLAN_MAC_STATUS_MASK_TX_C_PENDING 0x00000010 // b[4] |
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263 | #define WLAN_MAC_STATUS_MASK_TX_C_DONE 0x00000020 // b[5] |
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264 | #define WLAN_MAC_STATUS_MASK_TX_D_PENDING 0x00000040 // b[6] |
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265 | #define WLAN_MAC_STATUS_MASK_TX_D_DONE 0x00000080 // b[7] |
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266 | |
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267 | #define WLAN_MAC_STATUS_MASK_TX_PHY_ACTIVE 0x00000100 // b[8] |
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268 | #define WLAN_MAC_STATUS_MASK_RX_PHY_ACTIVE 0x00000200 // b[9] |
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269 | #define WLAN_MAC_STATUS_MASK_RX_PHY_STARTED 0x00000400 // b[10] |
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270 | #define WLAN_MAC_STATUS_MASK_RX_FCS_GOOD 0x00000800 // b[11] |
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271 | #define WLAN_MAC_STATUS_MASK_RX_END_ERROR 0x00007000 // b[14:12] |
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272 | #define WLAN_MAC_STATUS_MASK_NAV_ADDR_MATCHED 0x00008000 // b[15] |
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273 | #define WLAN_MAC_STATUS_MASK_NAV_BUSY 0x00010000 // b[16] |
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274 | #define WLAN_MAC_STATUS_MASK_CCA_BUSY 0x00020000 // b[17] |
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275 | #define WLAN_MAC_STATUS_MASK_TU_LATCH 0x00040000 // b[18] |
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276 | #define WLAN_MAC_STATUS_MASK_RX_PHY_WRITING_PAYLOAD 0x00080000 // b[19] |
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277 | #define WLAN_MAC_STATUS_MASK_AUX_STATUS0 0x00100000 // b[20] |
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278 | #define WLAN_MAC_STATUS_MASK_AUX_STATUS1 0x00200000 // b[21] |
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279 | #define WLAN_MAC_STATUS_MASK_AUX_STATUS2 0x00400000 // b[22] |
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280 | #define WLAN_MAC_STATUS_MASK_AUX_STATUS3 0x00800000 // b[23] |
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281 | |
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282 | #define wlan_mac_get_status() (Xil_In32(WLAN_MAC_REG_STATUS)) |
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283 | #define wlan_mac_check_tu_latch() ((wlan_mac_get_status() & WLAN_MAC_STATUS_MASK_TU_LATCH) >> 16) |
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284 | |
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285 | //----------------------------------------------- |
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286 | // WLAN MAC HW - RX_PHY_HDR_PARAMS bit masks |
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287 | // |
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288 | #define WLAN_MAC_PHY_RX_PHY_HDR_MASK_LENGTH 0x0000FFFF // b[15:0] |
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289 | #define WLAN_MAC_PHY_RX_PHY_HDR_MASK_MCS 0x007F0000 // b[22:16] |
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290 | #define WLAN_MAC_PHY_RX_PHY_HDR_MASK_UNSUPPORTED 0x00800000 // b[23] |
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291 | #define WLAN_MAC_PHY_RX_PHY_HDR_MASK_PHY_MODE 0x07000000 // b[26:24] |
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292 | #define WLAN_MAC_PHY_RX_PHY_HDR_READY 0x08000000 // b[27] |
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293 | #define WLAN_MAC_PHY_RX_PHY_HDR_MASK_PHY_SEL 0x10000000 // b[28] |
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294 | #define WLAN_MAC_PHY_RX_PHY_HDR_MASK_RX_ERROR 0xE0000000 // b[31:29] |
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295 | |
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296 | #define WLAN_MAC_PHY_RX_PHY_HDR_PHY_SEL_DSSS 0x00000000 |
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297 | #define WLAN_MAC_PHY_RX_PHY_HDR_PHY_SEL_OFDM 0x10000000 |
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298 | |
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299 | #define WLAN_MAC_PHY_RX_PHY_HDR_PHY_MODE_11AG 0x1 |
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300 | #define WLAN_MAC_PHY_RX_PHY_HDR_PHY_MODE_11N 0x2 |
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301 | #define WLAN_MAC_PHY_RX_PHY_HDR_PHY_MODE_11AC 0x8 |
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302 | |
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303 | |
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304 | //----------------------------------------------- |
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305 | // WLAN MAC HW - CONTROL bit masks / macros |
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306 | // |
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307 | #define WLAN_MAC_CTRL_MASK_RESET 0x00000001 |
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308 | #define WLAN_MAC_CTRL_MASK_DISABLE_NAV 0x00000002 |
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309 | #define WLAN_MAC_CTRL_MASK_RESET_NAV 0x00000004 |
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310 | #define WLAN_MAC_CTRL_MASK_BLOCK_RX_ON_TX 0x00000008 |
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311 | #define WLAN_MAC_CTRL_MASK_RESET_TU_LATCH 0x00000010 |
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312 | #define WLAN_MAC_CTRL_MASK_CCA_IGNORE_PHY_CS 0x00000020 |
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313 | #define WLAN_MAC_CTRL_MASK_CCA_IGNORE_TX_BUSY 0x00000040 |
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314 | #define WLAN_MAC_CTRL_MASK_CCA_IGNORE_NAV 0x00000080 |
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315 | #define WLAN_MAC_CTRL_MASK_FORCE_CCA_BUSY 0x00000100 |
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316 | #define WLAN_MAC_CTRL_MASK_RESET_RX_STARTED_LATCH 0x00000400 |
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317 | #define WLAN_MAC_CTRL_MASK_RESET_TX_CTRL_A 0x00000800 |
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318 | #define WLAN_MAC_CTRL_MASK_RESET_TX_CTRL_B 0x00001000 |
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319 | #define WLAN_MAC_CTRL_MASK_RESET_TX_CTRL_C 0x00002000 |
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320 | #define WLAN_MAC_CTRL_MASK_RESET_TX_CTRL_D 0x00004000 |
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321 | #define WLAN_MAC_CTRL_MASK_RESET_A_BACKOFF 0x00008000 |
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322 | #define WLAN_MAC_CTRL_MASK_RESET_C_BACKOFF 0x00010000 |
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323 | #define WLAN_MAC_CTRL_MASK_RESET_D_BACKOFF 0x00020000 |
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324 | #define WLAN_MAC_CTRL_MASK_PAUSE_TX_A 0x00040000 |
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325 | #define WLAN_MAC_CTRL_MASK_PAUSE_TX_C 0x00080000 |
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326 | #define WLAN_MAC_CTRL_MASK_PAUSE_TX_D 0x00100000 |
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327 | #define WLAN_MAC_CTRL_MASK_EN_EXT_CCABUSY 0x00200000 |
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328 | #define WLAN_MAC_CTRL_MASK_EN_EXT_POSTRXTIMER1_START 0x00400000 |
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329 | #define WLAN_MAC_CTRL_MASK_RESET_RX_PHY_ACTIVE_LATCHES 0x00800000 |
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330 | #define WLAN_MAC_CTRL_MASK_RESET_TX_PHY_ACTIVE_LATCHES 0x01000000 |
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331 | |
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332 | //----------------------------------------------- |
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333 | // WLAN MAC HW - START bit masks / macros |
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334 | // |
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335 | #define WLAN_MAC_START_REG_MASK_START_TX_A 0x1 |
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336 | #define WLAN_MAC_START_REG_MASK_START_TX_B 0x2 |
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337 | #define WLAN_MAC_START_REG_MASK_START_TX_C 0x4 |
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338 | #define WLAN_MAC_START_REG_MASK_START_TX_D 0x8 |
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339 | |
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340 | // TXRX_TIMESTAMPS_FRAC register |
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341 | // b[15:8]: Fractional part of RX_START microsecond timestamp |
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342 | // b[ 7:0]: Fractional part of TX_START microsecond timestamp |
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343 | #define wlan_mac_low_get_rx_start_timestamp_frac() ((Xil_In32(WLAN_MAC_REG_TXRX_TIMESTAMPS_FRAC) & 0xFF00) >> 8) |
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344 | #define wlan_mac_low_get_tx_start_timestamp_frac() (Xil_In32(WLAN_MAC_REG_TXRX_TIMESTAMPS_FRAC) & 0x00FF) |
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345 | |
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346 | |
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347 | #endif /* W3_MAC_PHY_REGS_H_ */ |
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