1 | ############################################################## |
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2 | # |
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3 | # Xilinx Core Generator version 14.4 |
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4 | # Date: Fri Sep 01 15:57:33 2017 |
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5 | # |
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6 | ############################################################## |
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7 | # |
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8 | # This file contains the customisation parameters for a |
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9 | # Xilinx CORE Generator IP GUI. It is strongly recommended |
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10 | # that you do not manually alter this file as it may cause |
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11 | # unexpected and unsupported behavior. |
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12 | # |
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13 | ############################################################## |
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14 | # |
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15 | # Generated from component: xilinx.com:ip:blk_mem_gen:7.3 |
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16 | # |
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17 | ############################################################## |
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18 | # |
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19 | # BEGIN Project Options |
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20 | SET addpads = false |
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21 | SET asysymbol = true |
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22 | SET busformat = BusFormatAngleBracketNotRipped |
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23 | SET createndf = false |
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24 | SET designentry = Verilog |
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25 | SET device = xc6vlx240t |
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26 | SET devicefamily = virtex6 |
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27 | SET flowvendor = Foundation_ISE |
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28 | SET formalverification = false |
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29 | SET foundationsym = false |
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30 | SET implementationfiletype = Ngc |
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31 | SET package = ff1156 |
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32 | SET removerpms = false |
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33 | SET simulationfiles = Behavioral |
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34 | SET speedgrade = -2 |
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35 | SET verilogsim = true |
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36 | SET vhdlsim = false |
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37 | # END Project Options |
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38 | # BEGIN Select |
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39 | SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:7.3 |
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40 | # END Select |
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41 | # BEGIN Parameters |
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42 | CSET additional_inputs_for_power_estimation=false |
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43 | CSET algorithm=Minimum_Area |
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44 | CSET assume_synchronous_clk=true |
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45 | CSET axi_id_width=4 |
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46 | CSET axi_slave_type=Memory_Slave |
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47 | CSET axi_type=AXI4_Full |
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48 | CSET byte_size=9 |
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49 | CSET coe_file=no_coe_file_loaded |
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50 | CSET collision_warnings=ALL |
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51 | CSET component_name=bit_match_ram_blkmemgen |
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52 | CSET disable_collision_warnings=false |
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53 | CSET disable_out_of_range_warnings=false |
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54 | CSET ecc=false |
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55 | CSET ecctype=No_ECC |
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56 | CSET enable_32bit_address=false |
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57 | CSET enable_a=Always_Enabled |
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58 | CSET enable_b=Always_Enabled |
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59 | CSET error_injection_type=Single_Bit_Error_Injection |
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60 | CSET fill_remaining_memory_locations=false |
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61 | CSET interface_type=Native |
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62 | CSET load_init_file=false |
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63 | CSET mem_file=no_Mem_file_loaded |
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64 | CSET memory_type=True_Dual_Port_RAM |
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65 | CSET operating_mode_a=WRITE_FIRST |
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66 | CSET operating_mode_b=WRITE_FIRST |
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67 | CSET output_reset_value_a=0 |
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68 | CSET output_reset_value_b=0 |
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69 | CSET pipeline_stages=0 |
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70 | CSET port_a_clock=100 |
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71 | CSET port_a_enable_rate=100 |
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72 | CSET port_a_write_rate=50 |
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73 | CSET port_b_clock=100 |
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74 | CSET port_b_enable_rate=100 |
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75 | CSET port_b_write_rate=50 |
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76 | CSET primitive=8kx2 |
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77 | CSET read_width_a=32 |
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78 | CSET read_width_b=32 |
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79 | CSET register_porta_input_of_softecc=false |
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80 | CSET register_porta_output_of_memory_core=false |
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81 | CSET register_porta_output_of_memory_primitives=false |
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82 | CSET register_portb_output_of_memory_core=false |
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83 | CSET register_portb_output_of_memory_primitives=false |
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84 | CSET register_portb_output_of_softecc=false |
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85 | CSET remaining_memory_locations=0 |
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86 | CSET reset_memory_latch_a=false |
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87 | CSET reset_memory_latch_b=false |
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88 | CSET reset_priority_a=CE |
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89 | CSET reset_priority_b=CE |
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90 | CSET reset_type=SYNC |
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91 | CSET softecc=false |
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92 | CSET use_axi_id=false |
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93 | CSET use_bram_block=Stand_Alone |
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94 | CSET use_byte_write_enable=false |
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95 | CSET use_error_injection_pins=false |
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96 | CSET use_regcea_pin=false |
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97 | CSET use_regceb_pin=false |
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98 | CSET use_rsta_pin=false |
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99 | CSET use_rstb_pin=false |
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100 | CSET write_depth_a=32768 |
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101 | CSET write_width_a=1 |
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102 | CSET write_width_b=1 |
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103 | # END Parameters |
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104 | # BEGIN Extra information |
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105 | MISC pkg_timestamp=2012-11-19T16:22:25Z |
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106 | # END Extra information |
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107 | GENERATE |
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108 | # CRC: 31db000 |
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