1 | //******************************************************************************************** |
---|
2 | // File: fec_decoder |
---|
3 | // Author: Yang Sun (ysun@rice.edu) |
---|
4 | // Birth: $ 4/26/07 |
---|
5 | // Des: This module integreated a Viterbi decoder |
---|
6 | // History: $ 04/26/07: Init coding for QPSK CC coding |
---|
7 | // $ 11/25/07: Updated for uncodede system |
---|
8 | // $ 04/16/08: Added 16-QAM support |
---|
9 | // $ 09/27/08: Added dec-puncture |
---|
10 | // $ 09/27/08: Added dec-puncture |
---|
11 | // $ 10/11/08, Added uncodeded and BPSK |
---|
12 | // $ 10/10/10, OFDM reference design v15.0 |
---|
13 | //******************************************************************************************** |
---|
14 | module fec_decoder ( |
---|
15 | clk , // I, clock |
---|
16 | ce , // I, clock enable |
---|
17 | nrst , // I, n reset |
---|
18 | fec_reg , // I, controll register |
---|
19 | start , // I, packet start pulse |
---|
20 | vin , // I, data valid input |
---|
21 | xk_index , // I, FFT index |
---|
22 | mod_level , // I, 0=Invalid, 1=BPSK, 2=QPSK, 4=16-QAM |
---|
23 | rx_i , // I, RX I |
---|
24 | rx_q , // I, RX Q |
---|
25 | rx_we , // O, buffer write enable |
---|
26 | rx_addr , // O, buffer write address |
---|
27 | rx_data , // O, buffer write data |
---|
28 | rx_done , // O, RX done pulse |
---|
29 | rx_we_2 , // O, buffer write enable in clk/2 domain |
---|
30 | rx_addr_2 , // O, buffer write address in clk/2 domain |
---|
31 | rx_data_2 , // O, buffer write data in clk/2 domain |
---|
32 | rx_done_2 // O, RX done pulse in clk/2 domain |
---|
33 | ) ; |
---|
34 | |
---|
35 | input clk ; |
---|
36 | input ce ; |
---|
37 | input nrst ; |
---|
38 | input [31:0] fec_reg ; |
---|
39 | input start ; |
---|
40 | input vin ; |
---|
41 | input [5:0] xk_index ; |
---|
42 | input [3:0] mod_level ; |
---|
43 | input [15:0] rx_i ; |
---|
44 | input [15:0] rx_q ; |
---|
45 | output rx_we ; |
---|
46 | output [13:0] rx_addr ; |
---|
47 | output [7:0] rx_data ; |
---|
48 | output rx_done ; |
---|
49 | output rx_we_2 ; |
---|
50 | output [13:0] rx_addr_2 ; |
---|
51 | output [7:0] rx_data_2 ; |
---|
52 | output rx_done_2 ; |
---|
53 | |
---|
54 | //============================== |
---|
55 | //Internal signal |
---|
56 | //============================== |
---|
57 | wire sym_start ; |
---|
58 | wire [3:0] llr_a ; |
---|
59 | wire [3:0] llr_b ; |
---|
60 | wire dec_vout ; |
---|
61 | |
---|
62 | wire [7:0] dec_dout ; |
---|
63 | |
---|
64 | wire [13:0] nbyte ; |
---|
65 | wire [13:0] byte_cnt ; |
---|
66 | wire rx_packet_done ; |
---|
67 | reg rx_packet_done_s0 ; |
---|
68 | reg rx_packet_done_s1 ; |
---|
69 | |
---|
70 | wire demapper_vld ; |
---|
71 | wire coding_en ; |
---|
72 | wire zero_tail ; |
---|
73 | wire soft_decoding ; |
---|
74 | wire [3:0] scale_qpsk ; |
---|
75 | wire [4:0] scale_16qam ; |
---|
76 | |
---|
77 | wire depunct_dav ; |
---|
78 | wire [7:0] iq_data ; |
---|
79 | wire [7:0] iq_data_buf ; |
---|
80 | wire llr_buf_empty ; |
---|
81 | wire buf_full ; |
---|
82 | wire [3:0] llr_i_depunc ; |
---|
83 | wire [3:0] llr_q_depunc ; |
---|
84 | wire llr_valid ; |
---|
85 | wire llr_buf_rd ; |
---|
86 | |
---|
87 | wire ack_pkt ; |
---|
88 | |
---|
89 | wire [1:0] cc_rate ; |
---|
90 | |
---|
91 | reg [23:0] timeout_reg ; |
---|
92 | reg in_dec ; |
---|
93 | wire timeout ; |
---|
94 | reg timeout_s1 ; |
---|
95 | wire timeout_pls ; |
---|
96 | wire depunt_buf_rd ; |
---|
97 | wire in_fullrate ; |
---|
98 | wire unc_buf_rd ; |
---|
99 | wire data_coded ; |
---|
100 | wire [3:0] hdr_mod_level ; |
---|
101 | |
---|
102 | wire we_1x ; |
---|
103 | wire [7:0] data_1x ; |
---|
104 | |
---|
105 | wire we_down2 ; |
---|
106 | wire [7:0] data_down2 ; |
---|
107 | wire [13:0] addr_down2 ; |
---|
108 | reg rx_done_d ; |
---|
109 | wire rx_done_i ; |
---|
110 | reg [15:0] rx_done_dly ; |
---|
111 | |
---|
112 | //========================================= |
---|
113 | // Main body of code |
---|
114 | //========================================= |
---|
115 | assign rx_done = (rx_packet_done_s0 & ~rx_packet_done_s1) | timeout_pls ; |
---|
116 | assign rx_addr = byte_cnt ; |
---|
117 | assign rx_data = dec_dout ; |
---|
118 | assign rx_we = dec_vout & ~rx_packet_done ; |
---|
119 | |
---|
120 | assign rx_addr_2 = addr_down2 ; |
---|
121 | assign rx_we_2 = we_down2 ; |
---|
122 | assign rx_data_2 = data_down2 ; |
---|
123 | assign rx_done_2 = rx_done_dly[15] ; |
---|
124 | |
---|
125 | |
---|
126 | assign we_1x = dec_vout & ~rx_packet_done ; |
---|
127 | assign data_1x = dec_dout ; |
---|
128 | |
---|
129 | assign coding_en = fec_reg [0] ; |
---|
130 | assign soft_decoding = fec_reg [1] ; |
---|
131 | assign zero_tail = fec_reg [2] ; |
---|
132 | assign scale_qpsk = fec_reg [7:4] ; |
---|
133 | assign scale_16qam = fec_reg [12:8] ; |
---|
134 | |
---|
135 | |
---|
136 | always @(posedge clk or negedge nrst) |
---|
137 | if(~nrst) |
---|
138 | rx_done_d <= 1'b0 ; |
---|
139 | else |
---|
140 | rx_done_d <= rx_done ; |
---|
141 | |
---|
142 | assign rx_done_i = rx_done | rx_done_d ; |
---|
143 | |
---|
144 | always @(posedge clk or negedge nrst) |
---|
145 | if(~nrst) |
---|
146 | rx_done_dly <= 0 ; |
---|
147 | else |
---|
148 | rx_done_dly <= {rx_done_dly[14:0], rx_done_i} ; |
---|
149 | |
---|
150 | //============================== |
---|
151 | // soft_demapper |
---|
152 | //============================== |
---|
153 | soft_demapper soft_demapper ( |
---|
154 | .clk (clk ), |
---|
155 | .nrst (nrst ), |
---|
156 | .start (start ), |
---|
157 | .coding_en (coding_en ), |
---|
158 | .vin (vin ), |
---|
159 | .xk_index (xk_index ), |
---|
160 | .mod_level (mod_level ), |
---|
161 | .rx_i (rx_i ), |
---|
162 | .rx_q (rx_q ), |
---|
163 | .scale_qpsk (scale_qpsk ), |
---|
164 | .scale_16qam (scale_16qam ), |
---|
165 | .in_fullrate (in_fullrate ), |
---|
166 | .sym_start (sym_start ), |
---|
167 | .hdr_mod_level (hdr_mod_level ), |
---|
168 | .vout (demapper_vld ), |
---|
169 | .soft_decoding (soft_decoding ), |
---|
170 | .llr_a (llr_a ), |
---|
171 | .llr_b (llr_b ) |
---|
172 | ) ; |
---|
173 | |
---|
174 | assign iq_data = {llr_a, llr_b} ; |
---|
175 | assign llr_buf_rd = (in_fullrate & ~data_coded) ? unc_buf_rd : depunt_buf_rd ; |
---|
176 | |
---|
177 | //============================== |
---|
178 | // LLR buffer |
---|
179 | //============================== |
---|
180 | llr_buffer llr_buffer ( |
---|
181 | .clk (clk ), |
---|
182 | .nrst (nrst ), |
---|
183 | .reset (start ), |
---|
184 | .din (iq_data ), |
---|
185 | .dout (iq_data_buf ), |
---|
186 | .wr (demapper_vld ), |
---|
187 | .rd (llr_buf_rd ), |
---|
188 | .empty (llr_buf_empty ), |
---|
189 | .full (buf_full ) |
---|
190 | ) ; |
---|
191 | |
---|
192 | assign depunct_dav = ~llr_buf_empty ; |
---|
193 | //============================== |
---|
194 | // depuncture |
---|
195 | //============================== |
---|
196 | depunc depunc ( |
---|
197 | .clk (clk ), |
---|
198 | .nrst (nrst ), |
---|
199 | .start (start ), |
---|
200 | .dav (depunct_dav ), |
---|
201 | .rate (cc_rate ), |
---|
202 | .din (iq_data_buf ), |
---|
203 | .vout (llr_valid ), |
---|
204 | .dout_a (llr_i_depunc ), |
---|
205 | .dout_b (llr_q_depunc ), |
---|
206 | .buf_rd (depunt_buf_rd ) |
---|
207 | ) ; |
---|
208 | |
---|
209 | //============================== |
---|
210 | // decoder_system |
---|
211 | //============================== |
---|
212 | decoder_system decoder_system ( |
---|
213 | .clk (clk ), // I, clock |
---|
214 | .nrst (nrst ), // I, n reset |
---|
215 | .start (start ), // I, start pulse |
---|
216 | .in_dec (in_dec ), |
---|
217 | .coding_en (coding_en ), |
---|
218 | .zero_tail (zero_tail ), |
---|
219 | .sym_start (sym_start ), // I, sym start |
---|
220 | .hdr_mod_level (hdr_mod_level ), |
---|
221 | .unc_buf_rd (unc_buf_rd ), // I, LLR buffer read by unc |
---|
222 | .vin (llr_valid ), // I, data valid input |
---|
223 | .llr_buf_empty (llr_buf_empty ), // I, LLR buffer empty |
---|
224 | .llr_a (llr_i_depunc ), // I, LLR I channel |
---|
225 | .llr_b (llr_q_depunc ), // I, LLR Q channel |
---|
226 | .vout (dec_vout ), // O, data valid output |
---|
227 | .dout (dec_dout ), // O, byte data output |
---|
228 | .nbyte (nbyte ), // O, num of bytes |
---|
229 | .byte_cnt (byte_cnt ), // O, byte cnt |
---|
230 | .cc_rate (cc_rate ), // O, code rate |
---|
231 | .data_coded (data_coded ), // O, coded system |
---|
232 | .in_fullrate (in_fullrate ) // O, in full rate |
---|
233 | ) ; |
---|
234 | |
---|
235 | out_ctrl out_ctrl ( |
---|
236 | .clk (clk ), |
---|
237 | .nrst (nrst ), |
---|
238 | .start (start ), |
---|
239 | .vin (we_1x ), |
---|
240 | .din (data_1x ), |
---|
241 | .vout (we_down2 ), |
---|
242 | .dout (data_down2 ), |
---|
243 | .idx_out (addr_down2 ) |
---|
244 | ) ; |
---|
245 | |
---|
246 | |
---|
247 | |
---|
248 | assign rx_packet_done = byte_cnt >= nbyte ; |
---|
249 | always @ (posedge clk or negedge nrst) |
---|
250 | if (~nrst) |
---|
251 | begin |
---|
252 | rx_packet_done_s0 <= 1'b0 ; |
---|
253 | rx_packet_done_s1 <= 1'b0 ; |
---|
254 | end |
---|
255 | else |
---|
256 | begin |
---|
257 | rx_packet_done_s0 <= rx_packet_done ; |
---|
258 | rx_packet_done_s1 <= rx_packet_done_s0 ; |
---|
259 | end |
---|
260 | |
---|
261 | |
---|
262 | assign ack_pkt = (nbyte == 24) ; |
---|
263 | |
---|
264 | always @(posedge clk or negedge nrst) |
---|
265 | if (~nrst) |
---|
266 | in_dec <= 1'b0 ; |
---|
267 | else if (start) |
---|
268 | in_dec <= 1'b1 ; |
---|
269 | else if (rx_done) |
---|
270 | in_dec <= 1'b0 ; |
---|
271 | |
---|
272 | assign timeout = timeout_reg == 24'h40000 ; |
---|
273 | always @(posedge clk or negedge nrst) |
---|
274 | if (~nrst) |
---|
275 | timeout_reg <= 0 ; |
---|
276 | else if (start) |
---|
277 | timeout_reg <= 0 ; |
---|
278 | else if (in_dec) |
---|
279 | begin |
---|
280 | if (~timeout) |
---|
281 | timeout_reg <= timeout_reg +1 ; |
---|
282 | end |
---|
283 | |
---|
284 | assign timeout_pls = ~timeout_s1 & timeout ; |
---|
285 | always @(posedge clk or negedge nrst) |
---|
286 | if (~nrst) |
---|
287 | timeout_s1 <= 1'b0 ; |
---|
288 | else |
---|
289 | timeout_s1 <= timeout ; |
---|
290 | |
---|
291 | endmodule |
---|
292 | |
---|
293 | //******************************************************************************** |
---|
294 | // File: decoder_system.v |
---|
295 | // Author: Yang Sun (ysun@rice.edu) |
---|
296 | // Birth: $ 11/25/07 |
---|
297 | // Des: decoder system |
---|
298 | // History: $ 11/25/07, Uncoded decoder |
---|
299 | // $ 12/1/07, Added Viterbi decoder (VBD) |
---|
300 | // $ 09/27/08: Added dec-puncture |
---|
301 | //******************************************************************************** |
---|
302 | module decoder_system ( |
---|
303 | clk , // I, clock |
---|
304 | nrst , // I, n reset |
---|
305 | start , // I, start pulse |
---|
306 | in_dec , |
---|
307 | coding_en , |
---|
308 | zero_tail , |
---|
309 | sym_start , // I, sym start |
---|
310 | hdr_mod_level , // I, header modulation level |
---|
311 | vin , // I, data valid input |
---|
312 | llr_a , // I, LLR bit a |
---|
313 | llr_b , // I, LLR bit b |
---|
314 | llr_buf_empty , // I, LLR buffer empty |
---|
315 | unc_buf_rd , // O, LLR buffer read by unc |
---|
316 | vout , // O, data valid output |
---|
317 | dout , // O, byte data output |
---|
318 | nbyte , // O, num of bytes |
---|
319 | byte_cnt , // O, byte cnt |
---|
320 | cc_rate , // O, code rate |
---|
321 | data_coded , // O, coded system |
---|
322 | in_fullrate // O, in full rate |
---|
323 | ) ; |
---|
324 | |
---|
325 | input clk ; |
---|
326 | input start ; |
---|
327 | input in_dec ; |
---|
328 | input coding_en ; |
---|
329 | input zero_tail ; |
---|
330 | input sym_start ; |
---|
331 | input [3:0] hdr_mod_level ; |
---|
332 | input nrst ; |
---|
333 | input vin ; |
---|
334 | input [3:0] llr_a ; |
---|
335 | input [3:0] llr_b ; |
---|
336 | input llr_buf_empty ; |
---|
337 | |
---|
338 | output unc_buf_rd ; |
---|
339 | output vout ; |
---|
340 | output [7:0] dout ; |
---|
341 | |
---|
342 | output [13:0] nbyte ; |
---|
343 | output reg [13:0] byte_cnt ; |
---|
344 | output [1:0] cc_rate ; |
---|
345 | output data_coded ; |
---|
346 | output in_fullrate ; |
---|
347 | |
---|
348 | //============================== |
---|
349 | //Internal signal |
---|
350 | //============================== |
---|
351 | wire hd_a ; |
---|
352 | wire hd_b ; |
---|
353 | wire unc_vout ; |
---|
354 | wire [7:0] unc_byte_out ; |
---|
355 | wire unc_vin ; |
---|
356 | |
---|
357 | wire ld_mod_type ; |
---|
358 | wire ld_payload_lsb ; |
---|
359 | wire ld_payload_msb ; |
---|
360 | reg ld_payload ; |
---|
361 | wire ld_rate ; |
---|
362 | reg update_mod_type ; |
---|
363 | |
---|
364 | wire [13:0] num_payload_i ; |
---|
365 | reg [13:0] num_payload ; |
---|
366 | reg [7:0] num_payload_low ; |
---|
367 | reg [7:0] num_payload_high ; |
---|
368 | |
---|
369 | reg [16:0] bit_cnt ; |
---|
370 | wire input_done ; |
---|
371 | reg input_done_s0 ; |
---|
372 | wire pkt_end ; |
---|
373 | |
---|
374 | wire [3:0] vb_b1 ; |
---|
375 | wire [3:0] vb_b0 ; |
---|
376 | wire vb_vin ; |
---|
377 | wire vb_vout ; |
---|
378 | wire [7:0] vb_dout ; |
---|
379 | wire vb_done ; |
---|
380 | |
---|
381 | wire [7:0] dec_byte ; |
---|
382 | wire dec_val ; |
---|
383 | |
---|
384 | wire [4:0] descramb_addr ; |
---|
385 | wire [7:0] descramb_data ; |
---|
386 | |
---|
387 | reg [3:0] mod_type_i ; |
---|
388 | wire [13:0] input_byte_cnt ; |
---|
389 | |
---|
390 | reg [3:0] sym_cnt ; |
---|
391 | |
---|
392 | wire vb_start ; |
---|
393 | wire vb_end ; |
---|
394 | |
---|
395 | reg [1:0] cc_rate_i ; |
---|
396 | reg in_baserate ; |
---|
397 | reg data_coded_i ; |
---|
398 | wire dout_sel ; |
---|
399 | |
---|
400 | //============================== |
---|
401 | // Main body of code |
---|
402 | //============================== |
---|
403 | assign nbyte = num_payload ; |
---|
404 | assign vout = dec_val ; |
---|
405 | assign dout = dec_byte ; |
---|
406 | |
---|
407 | assign data_coded = data_coded_i ; |
---|
408 | |
---|
409 | assign hd_a = llr_a [3] ; |
---|
410 | assign hd_b = llr_b [3] ; |
---|
411 | |
---|
412 | always @ (posedge clk or negedge nrst) |
---|
413 | if (~nrst) |
---|
414 | sym_cnt <= 0 ; |
---|
415 | else if (start) |
---|
416 | sym_cnt <= 0 ; |
---|
417 | else if (sym_start) |
---|
418 | sym_cnt <= (sym_cnt == 9 ? sym_cnt : sym_cnt +1) ; |
---|
419 | |
---|
420 | //?? assign unc_vin = in_fullrate & ~llr_buf_empty & ~data_coded ; |
---|
421 | |
---|
422 | assign unc_vin = coding_en ? (in_fullrate & ~llr_buf_empty & ~data_coded) : (in_dec & ~llr_buf_empty) ; |
---|
423 | assign unc_buf_rd = coding_en ? (unc_vin & ~data_coded) : unc_vin ; |
---|
424 | //===================================== |
---|
425 | // uncodede decoder |
---|
426 | //===================================== |
---|
427 | unc_decoder unc_decoder ( |
---|
428 | .clk (clk ), // clock |
---|
429 | .nrst (nrst ), // n reset |
---|
430 | .hd_a (hd_a ), // hard decision of I |
---|
431 | .hd_b (hd_b ), // hard decision of Q |
---|
432 | .start (start ), // start decoding pulse |
---|
433 | .vin (unc_vin ), // valid input |
---|
434 | .vout (unc_vout ), // valid output |
---|
435 | .dout (unc_byte_out ) // byte out |
---|
436 | ) ; |
---|
437 | |
---|
438 | always @ (posedge clk or negedge nrst) |
---|
439 | if (~nrst) |
---|
440 | bit_cnt <= 0 ; |
---|
441 | else if (start) |
---|
442 | bit_cnt <= 0 ; |
---|
443 | else if (vin) |
---|
444 | bit_cnt <= bit_cnt +2 ; |
---|
445 | |
---|
446 | assign input_byte_cnt = bit_cnt [16:3] ; |
---|
447 | assign input_done = (bit_cnt [16:4] == (data_coded_i ? num_payload : 24)) ; |
---|
448 | always @ (posedge clk) |
---|
449 | input_done_s0 <= input_done ; |
---|
450 | assign pkt_end = input_done & ~input_done_s0 ; |
---|
451 | |
---|
452 | assign vb_vin = vin ; |
---|
453 | assign vb_b1 = llr_a ; |
---|
454 | assign vb_b0 = llr_b ; |
---|
455 | |
---|
456 | //====================================================== |
---|
457 | // Viter decoder system |
---|
458 | //====================================================== |
---|
459 | vb_decoder_top vb_decoder_top ( |
---|
460 | .clk (clk ), //I |
---|
461 | .nrst (nrst ), //I |
---|
462 | .packet_start (vb_start ), //I |
---|
463 | .zero_tail (zero_tail ), |
---|
464 | .packet_end (vb_end ), //I |
---|
465 | .vin (vb_vin ), //I |
---|
466 | .llr_b1 (vb_b1 ), //I |
---|
467 | .llr_b0 (vb_b0 ), //I |
---|
468 | .vout (vb_vout ), //O |
---|
469 | .done (vb_done ), //O |
---|
470 | .dout_in_byte (vb_dout ) //O |
---|
471 | ) ; |
---|
472 | |
---|
473 | |
---|
474 | // Select |
---|
475 | assign dout_sel = (in_baserate | data_coded) & coding_en ; |
---|
476 | |
---|
477 | assign dec_byte = dout_sel ? vb_dout : unc_byte_out ; |
---|
478 | assign dec_val = dout_sel ? vb_vout : unc_vout ; |
---|
479 | |
---|
480 | assign descramb_addr = byte_cnt [4:0] ; |
---|
481 | //=================================== |
---|
482 | // de-scrambler |
---|
483 | //=================================== |
---|
484 | scrambler descrambler ( |
---|
485 | .addr (descramb_addr ), // address 32 |
---|
486 | .din (dec_byte ), // byte in |
---|
487 | .dout (descramb_data ) // byte out |
---|
488 | ) ; |
---|
489 | |
---|
490 | always @ (posedge clk or negedge nrst) |
---|
491 | if (~nrst) |
---|
492 | byte_cnt <= 0 ; |
---|
493 | else if (start) |
---|
494 | byte_cnt <= 0 ; |
---|
495 | else if (dec_val) |
---|
496 | byte_cnt <= byte_cnt +1 ; |
---|
497 | |
---|
498 | assign ld_mod_type = dec_val & (byte_cnt == 0) ; |
---|
499 | assign ld_payload_msb = byte_cnt == 2 ; |
---|
500 | assign ld_payload_lsb = byte_cnt == 3 ; |
---|
501 | assign ld_rate = byte_cnt == 1 ; |
---|
502 | |
---|
503 | always @* |
---|
504 | begin |
---|
505 | update_mod_type = 1'b0 ; |
---|
506 | if(sym_start) |
---|
507 | begin |
---|
508 | if(coding_en) |
---|
509 | case(hdr_mod_level) |
---|
510 | 4'd1: update_mod_type = (sym_cnt == 8) ; |
---|
511 | 4'd2: update_mod_type = (sym_cnt == 4) ; |
---|
512 | 4'd4: update_mod_type = (sym_cnt == 2) ; |
---|
513 | endcase |
---|
514 | else |
---|
515 | case(hdr_mod_level) |
---|
516 | 4'd1: update_mod_type = (sym_cnt == 4) ; |
---|
517 | 4'd2: update_mod_type = (sym_cnt == 2) ; |
---|
518 | 4'd4: update_mod_type = (sym_cnt == 1) ; |
---|
519 | endcase |
---|
520 | end |
---|
521 | end |
---|
522 | |
---|
523 | // Header is always not punctured |
---|
524 | assign cc_rate = coding_en ? (in_baserate ? 2'd0 : cc_rate_i) : 2'd0 ; |
---|
525 | |
---|
526 | always @ (posedge clk or negedge nrst) |
---|
527 | if (~nrst) |
---|
528 | begin |
---|
529 | num_payload_low <= 64 ; |
---|
530 | num_payload_high <= 0 ; |
---|
531 | cc_rate_i <= 0 ; |
---|
532 | data_coded_i <= 1'b1 ; |
---|
533 | end |
---|
534 | else if (start) |
---|
535 | begin |
---|
536 | num_payload_low <= 64 ; |
---|
537 | num_payload_high <= 0 ; |
---|
538 | cc_rate_i <= 0 ; |
---|
539 | data_coded_i <= 1'b1 ; |
---|
540 | end |
---|
541 | else if (dec_val) |
---|
542 | begin |
---|
543 | if (ld_payload_lsb) |
---|
544 | num_payload_low <= descramb_data ; |
---|
545 | if (ld_payload_msb) |
---|
546 | num_payload_high <= descramb_data ; |
---|
547 | if (ld_rate) |
---|
548 | begin |
---|
549 | cc_rate_i <= descramb_data[1:0] ; |
---|
550 | data_coded_i <= (descramb_data[1:0] != 2'b11) ; |
---|
551 | end |
---|
552 | end |
---|
553 | |
---|
554 | always @ (posedge clk) |
---|
555 | ld_payload <= ld_payload_lsb ; |
---|
556 | |
---|
557 | assign num_payload_i = {num_payload_high [5:0], num_payload_low} ; |
---|
558 | always @ (posedge clk or negedge nrst) |
---|
559 | if (~nrst) |
---|
560 | num_payload <= 64 ; |
---|
561 | else if (start) |
---|
562 | num_payload <= 64 ; |
---|
563 | else if (ld_payload) |
---|
564 | num_payload <= num_payload_i ; |
---|
565 | |
---|
566 | always @ (posedge clk or negedge nrst) |
---|
567 | if (~nrst) |
---|
568 | mod_type_i <= 2 ; |
---|
569 | else if (start) |
---|
570 | mod_type_i <= 2 ; |
---|
571 | else if (ld_mod_type) |
---|
572 | mod_type_i <= descramb_data [3:0] ; |
---|
573 | |
---|
574 | assign in_fullrate = ~in_baserate ; |
---|
575 | always @ (posedge clk or negedge nrst) |
---|
576 | if (~nrst) |
---|
577 | in_baserate <= 1'b1 ; |
---|
578 | else if (start) |
---|
579 | in_baserate <= 1'b1 ; |
---|
580 | else if (update_mod_type) |
---|
581 | in_baserate <= 1'b0 ; |
---|
582 | |
---|
583 | assign vb_start = start ; |
---|
584 | assign vb_end = pkt_end ; |
---|
585 | |
---|
586 | endmodule |
---|
587 | |
---|
588 | //************************************************************** |
---|
589 | // File: depunc.v |
---|
590 | // Author: Yang Sun (ysun@rice.edu) |
---|
591 | // Created: $ 2/4/07 |
---|
592 | // Des: viterbi decoder system |
---|
593 | // History: $ 02/04/07, Support puncture 2/3, 3/4 |
---|
594 | // $ 09/27/08: updated |
---|
595 | //************************************************************** |
---|
596 | module depunc ( |
---|
597 | clk , |
---|
598 | nrst , |
---|
599 | start , |
---|
600 | dav , // I, data available |
---|
601 | din , |
---|
602 | vout , |
---|
603 | dout_a , |
---|
604 | dout_b , |
---|
605 | buf_rd , |
---|
606 | rate // 0 = 1/2, 1 = 2/3, 2 = 3/4 |
---|
607 | ) ; |
---|
608 | |
---|
609 | parameter SW = 4 ; // soft input precision |
---|
610 | |
---|
611 | input clk ; |
---|
612 | input nrst ; |
---|
613 | input start ; |
---|
614 | input dav ; |
---|
615 | input [SW*2 -1:0] din ; |
---|
616 | input [1:0] rate ; |
---|
617 | output vout ; |
---|
618 | output [SW -1:0] dout_a ; |
---|
619 | output [SW -1:0] dout_b ; |
---|
620 | output buf_rd ; |
---|
621 | |
---|
622 | //================================================= |
---|
623 | //Internal signal |
---|
624 | //================================================= |
---|
625 | reg [1:0] cnt ; |
---|
626 | |
---|
627 | wire rd ; |
---|
628 | wire rd_r12 ; |
---|
629 | wire rd_r34 ; |
---|
630 | wire rd_r23 ; |
---|
631 | wire r23_ext ; |
---|
632 | reg r23_ext_s0 ; |
---|
633 | wire r34_ext ; |
---|
634 | |
---|
635 | reg [SW -1:0] app_i_r34 ; |
---|
636 | reg [SW -1:0] app_q_r34 ; |
---|
637 | reg [SW -1:0] app_i_r23 ; |
---|
638 | reg [SW -1:0] app_q_r23 ; |
---|
639 | wire [SW -1:0] app_i_r12 ; |
---|
640 | wire [SW -1:0] app_q_r12 ; |
---|
641 | wire [SW -1:0] app_i_mux ; |
---|
642 | wire [SW -1:0] app_q_mux ; |
---|
643 | wire app_valid ; |
---|
644 | wire [SW*2 -1:0] iq_data_buf ; |
---|
645 | reg [SW*2 -1:0] iq_data_buf_lat ; |
---|
646 | |
---|
647 | //================================================= |
---|
648 | // Main RTL |
---|
649 | //================================================= |
---|
650 | assign buf_rd = rd ; |
---|
651 | assign dout_a = app_i_mux ; |
---|
652 | assign dout_b = app_q_mux ; |
---|
653 | assign vout = app_valid ; |
---|
654 | |
---|
655 | always @ (posedge clk or negedge nrst) |
---|
656 | if (~nrst) |
---|
657 | cnt <= 0 ; |
---|
658 | else if (start) |
---|
659 | cnt <= 0 ; |
---|
660 | else if (dav) |
---|
661 | begin |
---|
662 | if (rate == 1) |
---|
663 | cnt <= cnt + 1 ; |
---|
664 | else if (rate ==2) |
---|
665 | cnt <= (cnt == 2 ? 0 : cnt +1) ; |
---|
666 | end |
---|
667 | |
---|
668 | // for rate = 1/2 |
---|
669 | assign rd_r12 = dav ; |
---|
670 | |
---|
671 | // for rate = 2/3 |
---|
672 | assign r23_ext = cnt == 3 ; |
---|
673 | always @ (posedge clk) |
---|
674 | r23_ext_s0 <= r23_ext ; |
---|
675 | |
---|
676 | assign r23_ext_p = ~r23_ext_s0 & r23_ext ; |
---|
677 | assign rd_r23 = dav & ~r23_ext ; |
---|
678 | |
---|
679 | // for rate = 3/4 |
---|
680 | assign rd_r34 = dav & (cnt != 2) ; |
---|
681 | assign r34_ext = dav & (cnt == 2) ; |
---|
682 | |
---|
683 | // mux |
---|
684 | assign rd = rate == 0 ? rd_r12 : rate == 1 ? rd_r23 : rd_r34 ; |
---|
685 | |
---|
686 | assign iq_data_buf = din ; |
---|
687 | always @ (posedge clk) |
---|
688 | if (rd) |
---|
689 | iq_data_buf_lat <= iq_data_buf ; |
---|
690 | |
---|
691 | // rate = 2/3 |
---|
692 | always @* |
---|
693 | begin |
---|
694 | app_i_r23 = 0 ; |
---|
695 | app_q_r23 = 0 ; |
---|
696 | case (cnt) |
---|
697 | 0: begin |
---|
698 | app_i_r23 = iq_data_buf [SW*2 -1 : SW] ; |
---|
699 | app_q_r23 = iq_data_buf [SW -1: 0] ; |
---|
700 | end |
---|
701 | 1: begin |
---|
702 | app_i_r23 = iq_data_buf [SW*2 -1 : SW] ; |
---|
703 | app_q_r23 = 0 ; |
---|
704 | end |
---|
705 | 2: begin |
---|
706 | app_i_r23 = iq_data_buf_lat [SW -1: 0] ; |
---|
707 | app_q_r23 = iq_data_buf [SW*2 -1 : SW] ; |
---|
708 | end |
---|
709 | 3: begin |
---|
710 | app_i_r23 = iq_data_buf_lat [SW -1: 0] ; |
---|
711 | app_q_r23 = 0 ; |
---|
712 | end |
---|
713 | endcase |
---|
714 | end |
---|
715 | |
---|
716 | // rate = 3/4 |
---|
717 | always @* |
---|
718 | begin |
---|
719 | app_i_r34 = 0 ; |
---|
720 | app_q_r34 = 0 ; |
---|
721 | case (cnt) |
---|
722 | 0: begin |
---|
723 | app_i_r34 = iq_data_buf [SW*2 -1 : SW] ; |
---|
724 | app_q_r34 = iq_data_buf [SW -1: 0] ; |
---|
725 | end |
---|
726 | 1: begin |
---|
727 | app_i_r34 = iq_data_buf [SW*2 -1 : SW] ; |
---|
728 | app_q_r34 = 0 ; |
---|
729 | end |
---|
730 | 2: begin |
---|
731 | app_i_r34 = 0 ; |
---|
732 | app_q_r34 = iq_data_buf_lat [SW -1: 0] ; |
---|
733 | end |
---|
734 | default: begin |
---|
735 | app_i_r34 = 0 ; |
---|
736 | app_q_r34 = 0 ; |
---|
737 | end |
---|
738 | endcase |
---|
739 | end |
---|
740 | |
---|
741 | // rate = 1/2 |
---|
742 | assign app_i_r12 = iq_data_buf [SW*2 -1 : SW] ; |
---|
743 | assign app_q_r12 = iq_data_buf [SW -1: 0] ; |
---|
744 | |
---|
745 | assign app_i_mux = rate == 0 ? app_i_r12 : rate == 1 ? app_i_r23 : app_i_r34 ; |
---|
746 | assign app_q_mux = rate == 0 ? app_q_r12 : rate == 1 ? app_q_r23 : app_q_r34 ; |
---|
747 | |
---|
748 | assign app_valid = rate == 0 ? rd_r12 : rate == 1 ? (rd_r23 | r23_ext_p) : (rd_r34 | r34_ext) ; |
---|
749 | |
---|
750 | endmodule |
---|
751 | |
---|
752 | |
---|
753 | |
---|
754 | //********************************************************* |
---|
755 | // File: fifo_16x8.v |
---|
756 | // Author: Y. Sun |
---|
757 | // Des: 16x8 FIFO |
---|
758 | //********************************************************* |
---|
759 | module fifo_16x8 ( |
---|
760 | clk , // I, clock |
---|
761 | nrst , // I, async reset |
---|
762 | reset , // I, sync reset |
---|
763 | wdata , // I, write data |
---|
764 | wr , // I, write enable |
---|
765 | rd , // I, read enable |
---|
766 | rdata , // O, read data |
---|
767 | empty , // O, empty |
---|
768 | full // O, full |
---|
769 | ) ; |
---|
770 | |
---|
771 | parameter WIDTH = 8 ; |
---|
772 | parameter DEPTH = 16 ; |
---|
773 | parameter ADDR_BITS = 4 ; |
---|
774 | |
---|
775 | input clk ; |
---|
776 | input nrst ; |
---|
777 | input reset ; |
---|
778 | input [WIDTH-1:0] wdata ; |
---|
779 | input wr ; |
---|
780 | input rd ; |
---|
781 | output [WIDTH-1:0] rdata ; |
---|
782 | output empty ; |
---|
783 | output full ; |
---|
784 | |
---|
785 | |
---|
786 | //============================ |
---|
787 | // Internal signals |
---|
788 | //============================ |
---|
789 | reg [WIDTH-1:0] mem [DEPTH-1:0] ; |
---|
790 | reg [ADDR_BITS:0] cnt ; |
---|
791 | reg [ADDR_BITS-1:0] waddr ; |
---|
792 | reg [ADDR_BITS-1:0] raddr ; |
---|
793 | |
---|
794 | //============================ |
---|
795 | // Main RTL Code |
---|
796 | //============================ |
---|
797 | assign empty = cnt == 0 ; |
---|
798 | assign full = cnt == DEPTH ; |
---|
799 | |
---|
800 | |
---|
801 | always @ (posedge clk or negedge nrst) |
---|
802 | if(~nrst) |
---|
803 | cnt <= 0 ; |
---|
804 | else |
---|
805 | begin |
---|
806 | if (reset) |
---|
807 | cnt <= 0 ; |
---|
808 | else if (wr & ~rd) |
---|
809 | cnt <= cnt +1 ; |
---|
810 | else if (rd & ~wr) |
---|
811 | cnt <= cnt -1 ; |
---|
812 | end |
---|
813 | |
---|
814 | always @ (posedge clk or negedge nrst) |
---|
815 | if(~nrst) |
---|
816 | waddr <= 0 ; |
---|
817 | else |
---|
818 | begin |
---|
819 | if (reset) |
---|
820 | waddr <= 0 ; |
---|
821 | else if (wr) |
---|
822 | waddr <= waddr == DEPTH -1 ? 0 : waddr +1 ; |
---|
823 | end |
---|
824 | |
---|
825 | always @ (posedge clk or negedge nrst) |
---|
826 | if(~nrst) |
---|
827 | raddr <= 0 ; |
---|
828 | else |
---|
829 | begin |
---|
830 | if (reset) |
---|
831 | raddr <= 0 ; |
---|
832 | else if (rd) |
---|
833 | raddr <= raddr == DEPTH -1 ? 0 : raddr +1 ; |
---|
834 | end |
---|
835 | |
---|
836 | always @ (posedge clk) |
---|
837 | if (wr) |
---|
838 | mem [waddr] <= wdata ; |
---|
839 | |
---|
840 | assign rdata = mem [raddr] ; |
---|
841 | |
---|
842 | endmodule |
---|
843 | |
---|
844 | //************************************************************** |
---|
845 | // File: llr_buffer.v |
---|
846 | // Author: Yang Sun (ysun@rice.edu) |
---|
847 | // Created: $ 2/4/07 |
---|
848 | // Des: Buffer IQ data for viterbi decoder |
---|
849 | // History: $ 09/27/07 :updated |
---|
850 | //************************************************************** |
---|
851 | module llr_buffer ( |
---|
852 | clk , |
---|
853 | nrst , |
---|
854 | reset , |
---|
855 | din , |
---|
856 | dout , |
---|
857 | wr , |
---|
858 | rd , |
---|
859 | empty , |
---|
860 | full |
---|
861 | ) ; |
---|
862 | |
---|
863 | parameter DEPTH = 256 ; // 128 slots |
---|
864 | parameter ADDRW = 8 ; |
---|
865 | parameter SW = 4 ; |
---|
866 | |
---|
867 | input clk ; // system clock |
---|
868 | input nrst ; |
---|
869 | input reset ; |
---|
870 | input [SW*2 -1:0] din ; |
---|
871 | input wr ; |
---|
872 | input rd ; |
---|
873 | output [SW*2 -1:0] dout ; |
---|
874 | output empty ; |
---|
875 | output full ; |
---|
876 | |
---|
877 | //============================================== |
---|
878 | // Internal signal |
---|
879 | //============================================== |
---|
880 | reg [SW*2 -1:0] mem [DEPTH -1:0] ; |
---|
881 | wire [SW*2 -1:0] data ; |
---|
882 | |
---|
883 | reg [ADDRW :0] waddr ; |
---|
884 | reg [ADDRW :0] raddr ; |
---|
885 | wire [ADDRW -1:0] waddr_i ; |
---|
886 | wire [ADDRW -1:0] raddr_i ; |
---|
887 | |
---|
888 | //============================================== |
---|
889 | // Main RTL |
---|
890 | //============================================== |
---|
891 | assign dout = data ; |
---|
892 | assign waddr_i = waddr [ADDRW -1 : 0] ; |
---|
893 | assign raddr_i = raddr [ADDRW -1 : 0] ; |
---|
894 | assign empty = (waddr [ADDRW] ~^ raddr [ADDRW]) & (waddr_i == raddr_i) ; |
---|
895 | assign full = (waddr [ADDRW] ^ raddr [ADDRW]) & (waddr_i == raddr_i) ; |
---|
896 | |
---|
897 | always @ (posedge clk or negedge nrst) |
---|
898 | if (~nrst) |
---|
899 | waddr <= 0 ; |
---|
900 | else if (reset) |
---|
901 | waddr <= 0 ; |
---|
902 | else if (wr) |
---|
903 | waddr <= waddr + 1 ; |
---|
904 | |
---|
905 | always @ (posedge clk or negedge nrst) |
---|
906 | if (~nrst) |
---|
907 | raddr <= 0 ; |
---|
908 | else if (reset) |
---|
909 | raddr <= 0 ; |
---|
910 | else if (rd) |
---|
911 | raddr <= raddr + 1 ; |
---|
912 | |
---|
913 | always @ (posedge clk) |
---|
914 | if (wr) |
---|
915 | mem [waddr_i] <= din ; |
---|
916 | |
---|
917 | assign data = mem [raddr_i] ; |
---|
918 | |
---|
919 | |
---|
920 | endmodule |
---|
921 | |
---|
922 | //************************************************************** |
---|
923 | // File: max_metric_logic.v |
---|
924 | // Author: Yang Sun (ysun@rice.edu) |
---|
925 | // Birth: $ 1/14/07 |
---|
926 | // Des: The top level of viterbi decoder |
---|
927 | // Take 5 bit soft value is [-16 : +15] |
---|
928 | // K = 7. g0 = 133, g1 = 171 |
---|
929 | // History: $ 1/14/07, Init coding |
---|
930 | // $ 1/22/07, K = 5, Zero latency |
---|
931 | // $ 12/1/07: Updated |
---|
932 | //************************************************************** |
---|
933 | module max_metric_logic ( |
---|
934 | a , // I, metric a |
---|
935 | b , // I, metric b |
---|
936 | c , // I, metric c |
---|
937 | d , // I, metric d |
---|
938 | sa , // I, state a |
---|
939 | sb , // I, state b |
---|
940 | sc , // I, state c |
---|
941 | sd , // I, state d |
---|
942 | state , // O, state |
---|
943 | max // O, max metric |
---|
944 | ) ; |
---|
945 | |
---|
946 | parameter M = 7 ; |
---|
947 | parameter K = 7 ; |
---|
948 | |
---|
949 | input [M -1:0] a ; |
---|
950 | input [M -1:0] b ; |
---|
951 | input [M -1:0] c ; |
---|
952 | input [M -1:0] d ; |
---|
953 | |
---|
954 | input [K -2:0] sa ; |
---|
955 | input [K -2:0] sb ; |
---|
956 | input [K -2:0] sc ; |
---|
957 | input [K -2:0] sd ; |
---|
958 | |
---|
959 | output [K -2:0] state ; |
---|
960 | output [M -1:0] max ; |
---|
961 | |
---|
962 | //================================== |
---|
963 | //Internal signal |
---|
964 | //================================== |
---|
965 | |
---|
966 | reg [K -2:0] pos0 ; |
---|
967 | reg [K -2:0] pos1 ; |
---|
968 | reg [M -1:0] max0 ; |
---|
969 | reg [M -1:0] max1 ; |
---|
970 | reg [M -1:0] tmp ; |
---|
971 | reg [K -2:0] state_i ; |
---|
972 | reg [M -1:0] max_i ; |
---|
973 | |
---|
974 | //================================== |
---|
975 | // Main body of code |
---|
976 | //================================== |
---|
977 | assign state = state_i ; |
---|
978 | assign max = max_i ; |
---|
979 | |
---|
980 | always @* |
---|
981 | begin |
---|
982 | tmp = a-b ; |
---|
983 | if(~tmp[M -1]) |
---|
984 | begin |
---|
985 | max0 = a ; |
---|
986 | pos0 = sa ; |
---|
987 | end |
---|
988 | else |
---|
989 | begin |
---|
990 | max0 = b ; |
---|
991 | pos0 = sb ; |
---|
992 | end |
---|
993 | |
---|
994 | tmp = c-d ; |
---|
995 | if(~tmp[M-1]) |
---|
996 | begin |
---|
997 | max1 = c ; |
---|
998 | pos1 = sc ; |
---|
999 | end |
---|
1000 | else |
---|
1001 | begin |
---|
1002 | max1 = d ; |
---|
1003 | pos1 = sd ; |
---|
1004 | end |
---|
1005 | |
---|
1006 | tmp = max0 - max1 ; |
---|
1007 | if (~tmp[M-1]) |
---|
1008 | begin |
---|
1009 | max_i = max0 ; |
---|
1010 | state_i = pos0 ; |
---|
1011 | end |
---|
1012 | else |
---|
1013 | begin |
---|
1014 | state_i = pos1 ; |
---|
1015 | max_i = max1 ; |
---|
1016 | end |
---|
1017 | end |
---|
1018 | |
---|
1019 | endmodule |
---|
1020 | |
---|
1021 | //************************************************************** |
---|
1022 | // File: max_metric |
---|
1023 | // Author: Yang Sun (ysun@rice.edu) |
---|
1024 | // Birth: $ 1/14/07 |
---|
1025 | // Des: Find max metric |
---|
1026 | // K = 7. g0 = 133, g1 = 171 |
---|
1027 | // History: $ 1/14/07, Init coding |
---|
1028 | // $ 1/22/07, K = 5 |
---|
1029 | // $ 2/23/07, 1 pipeline |
---|
1030 | // $ 12/1/07: updated |
---|
1031 | //************************************************************** |
---|
1032 | module max_metric ( |
---|
1033 | clk , // I, clock |
---|
1034 | a , // I, metric a |
---|
1035 | b , // I, metric b |
---|
1036 | c , // I, metric c |
---|
1037 | d , // I, metric d |
---|
1038 | sa , // I, state a |
---|
1039 | sb , // I, state b |
---|
1040 | sc , // I, state c |
---|
1041 | sd , // I, state d |
---|
1042 | state , // O, state |
---|
1043 | max // O, max metric |
---|
1044 | ) ; |
---|
1045 | |
---|
1046 | parameter M = 7 ; |
---|
1047 | parameter K = 7 ; |
---|
1048 | |
---|
1049 | input clk ; |
---|
1050 | input [M -1:0] a ; |
---|
1051 | input [M -1:0] b ; |
---|
1052 | input [M -1:0] c ; |
---|
1053 | input [M -1:0] d ; |
---|
1054 | |
---|
1055 | input [K -2:0] sa ; |
---|
1056 | input [K -2:0] sb ; |
---|
1057 | input [K -2:0] sc ; |
---|
1058 | input [K -2:0] sd ; |
---|
1059 | |
---|
1060 | output [K -2:0] state ; |
---|
1061 | output [M -1:0] max ; |
---|
1062 | |
---|
1063 | //===================================== |
---|
1064 | //Internal signal |
---|
1065 | //===================================== |
---|
1066 | reg [K -2:0] pos0 ; |
---|
1067 | reg [K -2:0] pos1 ; |
---|
1068 | reg [M -1:0] max0 ; |
---|
1069 | reg [M -1:0] max1 ; |
---|
1070 | reg [M -1:0] tmp ; |
---|
1071 | reg [K -2:0] state_i ; |
---|
1072 | reg [M -1:0] max_i ; |
---|
1073 | reg [K -2:0] state_reg ; |
---|
1074 | reg [M -1:0] max_reg ; |
---|
1075 | |
---|
1076 | //===================================== |
---|
1077 | // Main RTL code |
---|
1078 | //===================================== |
---|
1079 | assign state = state_reg ; |
---|
1080 | assign max = max_reg ; |
---|
1081 | |
---|
1082 | always @ (posedge clk) |
---|
1083 | begin |
---|
1084 | state_reg <= state_i ; |
---|
1085 | max_reg <= max_i ; |
---|
1086 | end |
---|
1087 | |
---|
1088 | always @* |
---|
1089 | begin |
---|
1090 | tmp = a-b ; |
---|
1091 | if(~tmp[M -1]) |
---|
1092 | begin |
---|
1093 | max0 = a ; |
---|
1094 | pos0 = sa ; |
---|
1095 | end |
---|
1096 | else |
---|
1097 | begin |
---|
1098 | max0 = b ; |
---|
1099 | pos0 = sb ; |
---|
1100 | end |
---|
1101 | |
---|
1102 | tmp = c-d ; |
---|
1103 | if(~tmp[M-1]) |
---|
1104 | begin |
---|
1105 | max1 = c ; |
---|
1106 | pos1 = sc ; |
---|
1107 | end |
---|
1108 | else |
---|
1109 | begin |
---|
1110 | max1 = d ; |
---|
1111 | pos1 = sd ; |
---|
1112 | end |
---|
1113 | |
---|
1114 | tmp = max0 - max1 ; |
---|
1115 | if (~tmp[M-1]) |
---|
1116 | begin |
---|
1117 | max_i = max0 ; |
---|
1118 | state_i = pos0 ; |
---|
1119 | end |
---|
1120 | else |
---|
1121 | begin |
---|
1122 | state_i = pos1 ; |
---|
1123 | max_i = max1 ; |
---|
1124 | end |
---|
1125 | end |
---|
1126 | |
---|
1127 | endmodule |
---|
1128 | |
---|
1129 | //********************************************************* |
---|
1130 | // File: out_ctrl |
---|
1131 | // Author: Y. Sun |
---|
1132 | // Des: Convert the outputs into clk/2 domain |
---|
1133 | // I have to convert the output into clk/2 domain |
---|
1134 | // coz the downstream block takes clk/2 signals |
---|
1135 | //********************************************************* |
---|
1136 | module out_ctrl ( |
---|
1137 | clk , // I, clock |
---|
1138 | nrst , // I, async reset |
---|
1139 | start , // I, start |
---|
1140 | vin , // I, write enable |
---|
1141 | din , // I, write data |
---|
1142 | vout , // O, read enable |
---|
1143 | dout , // O, read data |
---|
1144 | idx_out // O, out index |
---|
1145 | ) ; |
---|
1146 | |
---|
1147 | input clk ; |
---|
1148 | input nrst ; |
---|
1149 | input start ; |
---|
1150 | input vin ; |
---|
1151 | input [7:0] din ; |
---|
1152 | output vout ; |
---|
1153 | output [7:0] dout ; |
---|
1154 | output [13:0] idx_out ; |
---|
1155 | |
---|
1156 | reg en ; |
---|
1157 | wire ff_empty ; |
---|
1158 | wire ff_rd ; |
---|
1159 | wire [7:0] ff_rdata ; |
---|
1160 | reg [7:0] data_lat ; |
---|
1161 | reg ff_rd_d ; |
---|
1162 | reg ff_rd_dd ; |
---|
1163 | reg [13:0] cnt ; |
---|
1164 | |
---|
1165 | //============================ |
---|
1166 | // Main RTL Code |
---|
1167 | //============================ |
---|
1168 | assign vout = ff_rd_d | ff_rd_dd ; |
---|
1169 | assign dout = data_lat ; |
---|
1170 | assign idx_out = cnt ; |
---|
1171 | |
---|
1172 | always @(posedge clk or negedge nrst) |
---|
1173 | if(~nrst) |
---|
1174 | en <= 1'b1 ; |
---|
1175 | else if (start) |
---|
1176 | en <= 1'b1 ; |
---|
1177 | else |
---|
1178 | en <= ~en ; |
---|
1179 | |
---|
1180 | assign ff_rd = ~ff_empty & en ; |
---|
1181 | |
---|
1182 | fifo_16x8 fifo_16x8 ( |
---|
1183 | .clk (clk ), |
---|
1184 | .nrst (nrst ), |
---|
1185 | .reset (start ), |
---|
1186 | .wr (vin ), |
---|
1187 | .wdata (din ), |
---|
1188 | .rd (ff_rd ), |
---|
1189 | .rdata (ff_rdata ), |
---|
1190 | .empty (ff_empty ), |
---|
1191 | .full ( ) |
---|
1192 | ) ; |
---|
1193 | |
---|
1194 | always @(posedge clk or negedge nrst) |
---|
1195 | if(~nrst) |
---|
1196 | data_lat <= 0 ; |
---|
1197 | else if (ff_rd) |
---|
1198 | data_lat <= ff_rdata ; |
---|
1199 | |
---|
1200 | always @(posedge clk or negedge nrst) |
---|
1201 | if(~nrst) |
---|
1202 | begin |
---|
1203 | ff_rd_d <= 1'b0 ; |
---|
1204 | ff_rd_dd <= 1'b0 ; |
---|
1205 | end |
---|
1206 | else if (start) |
---|
1207 | begin |
---|
1208 | ff_rd_dd <= 1'b0 ; |
---|
1209 | ff_rd_d <= 1'b0 ; |
---|
1210 | end |
---|
1211 | else |
---|
1212 | begin |
---|
1213 | ff_rd_dd <= ff_rd_d ; |
---|
1214 | ff_rd_d <= ff_rd ; |
---|
1215 | end |
---|
1216 | |
---|
1217 | always @(posedge clk or negedge nrst) |
---|
1218 | if(~nrst) |
---|
1219 | cnt <= 0 ; |
---|
1220 | else if (start) |
---|
1221 | cnt <= 0 ; |
---|
1222 | else if (ff_rd_dd) |
---|
1223 | cnt <= cnt +1 ; |
---|
1224 | |
---|
1225 | |
---|
1226 | endmodule |
---|
1227 | |
---|
1228 | |
---|
1229 | //******************************************************************************** |
---|
1230 | // Module: round_data.v |
---|
1231 | // Author: Yang Sun (ysun@rice.edu) |
---|
1232 | // Birth: $ 4/29/07 |
---|
1233 | // Des: Round with 1 latency |
---|
1234 | // History: $ 4/29/07, Init coding |
---|
1235 | // $ 05/04/08: Fixed a bug |
---|
1236 | //******************************************************************************** |
---|
1237 | module round_data ( |
---|
1238 | clk, din, dout |
---|
1239 | ) ; |
---|
1240 | |
---|
1241 | input clk ; |
---|
1242 | input [12:0] din ; |
---|
1243 | output reg [3:0] dout ; |
---|
1244 | |
---|
1245 | //===================================== |
---|
1246 | //Internal signal |
---|
1247 | //===================================== |
---|
1248 | reg [3:0] tmp ; |
---|
1249 | |
---|
1250 | //===================================== |
---|
1251 | // Main body of code |
---|
1252 | //===================================== |
---|
1253 | |
---|
1254 | always @ (posedge clk) |
---|
1255 | dout <= tmp ; |
---|
1256 | |
---|
1257 | always @* |
---|
1258 | begin |
---|
1259 | if ((~din[12]) && (din[11:10] != 2'b00)) |
---|
1260 | tmp = 4'b0111 ; |
---|
1261 | else if (din[12] && (din[11:10] != 2'b11)) |
---|
1262 | tmp = 4'b1000 ; |
---|
1263 | else if (din[12:10] == 3'b000) // positive |
---|
1264 | begin |
---|
1265 | if ((din[9:7] != 3'b111) & din[6]) |
---|
1266 | tmp = din[10:7] +1 ; |
---|
1267 | else |
---|
1268 | tmp = din[10:7] ; |
---|
1269 | end |
---|
1270 | else // negtive |
---|
1271 | begin |
---|
1272 | if ((din[9:7] != 3'b000) & din[6]) |
---|
1273 | tmp = din[10:7] +1 ; |
---|
1274 | else |
---|
1275 | tmp = din[10:7] ; |
---|
1276 | end |
---|
1277 | end |
---|
1278 | |
---|
1279 | endmodule |
---|
1280 | //******************************************************************************** |
---|
1281 | // File: scrambler.v |
---|
1282 | // Author: Yang Sun (ysun@rice.edu) |
---|
1283 | // Des: byte scrambler |
---|
1284 | // History: $ 12/1/07, Created |
---|
1285 | //******************************************************************************** |
---|
1286 | `ifndef INCLUDE_SCRAMBLER |
---|
1287 | `define INCLUDE_SCRAMBLER |
---|
1288 | module scrambler ( |
---|
1289 | addr , // address 32 |
---|
1290 | din , // byte in |
---|
1291 | dout // byte out |
---|
1292 | ) ; |
---|
1293 | |
---|
1294 | input [4:0] addr ; |
---|
1295 | input [7:0] din ; |
---|
1296 | output [7:0] dout ; |
---|
1297 | |
---|
1298 | //============================== |
---|
1299 | //Internal signal |
---|
1300 | //============================== |
---|
1301 | reg [7:0] scram_mask ; |
---|
1302 | |
---|
1303 | //============================== |
---|
1304 | // Main RTL code |
---|
1305 | //============================== |
---|
1306 | assign dout = din ^ scram_mask ; |
---|
1307 | |
---|
1308 | always @* |
---|
1309 | begin |
---|
1310 | case (addr[4:0]) |
---|
1311 | 0: scram_mask = 40 ; |
---|
1312 | 1: scram_mask = 198 ; |
---|
1313 | 2: scram_mask = 78 ; |
---|
1314 | 3: scram_mask = 63 ; |
---|
1315 | 4: scram_mask = 82 ; |
---|
1316 | 5: scram_mask = 173 ; |
---|
1317 | 6: scram_mask = 102 ; |
---|
1318 | 7: scram_mask = 245 ; |
---|
1319 | 8: scram_mask = 48 ; |
---|
1320 | 9: scram_mask = 111 ; |
---|
1321 | 10: scram_mask = 172 ; |
---|
1322 | 11: scram_mask = 115 ; |
---|
1323 | 12: scram_mask = 147 ; |
---|
1324 | 13: scram_mask = 230 ; |
---|
1325 | 14: scram_mask = 216 ; |
---|
1326 | 15: scram_mask = 93 ; |
---|
1327 | 16: scram_mask = 72 ; |
---|
1328 | 17: scram_mask = 65 ; |
---|
1329 | 18: scram_mask = 62 ; |
---|
1330 | 19: scram_mask = 2 ; |
---|
1331 | 20: scram_mask = 205 ; |
---|
1332 | 21: scram_mask = 242 ; |
---|
1333 | 22: scram_mask = 122 ; |
---|
1334 | 23: scram_mask = 90 ; |
---|
1335 | 24: scram_mask = 128 ; |
---|
1336 | 25: scram_mask = 83 ; |
---|
1337 | 26: scram_mask = 105 ; |
---|
1338 | 27: scram_mask = 97 ; |
---|
1339 | 28: scram_mask = 73 ; |
---|
1340 | 29: scram_mask = 10 ; |
---|
1341 | 30: scram_mask = 5 ; |
---|
1342 | 31: scram_mask = 252 ; |
---|
1343 | default: scram_mask = 40 ; |
---|
1344 | endcase |
---|
1345 | end |
---|
1346 | |
---|
1347 | endmodule |
---|
1348 | `endif |
---|
1349 | |
---|
1350 | //******************************************************************************** |
---|
1351 | // Module: Multiplier |
---|
1352 | // Author: Yang Sun (ysun@rice.edu) |
---|
1353 | // Birth: $ 4/29/07 |
---|
1354 | // Description: Mult with 1 latency |
---|
1355 | // History: $ 4/29/07, Init coding |
---|
1356 | //******************************************************************************** |
---|
1357 | module smult ( |
---|
1358 | clk, a_in, b_in, p_out |
---|
1359 | ) ; |
---|
1360 | |
---|
1361 | parameter AWID = 8 ; |
---|
1362 | parameter BWID = 5 ; |
---|
1363 | parameter PWID = AWID + BWID ; |
---|
1364 | |
---|
1365 | input clk ; |
---|
1366 | input [AWID -1:0] a_in ; |
---|
1367 | input [BWID -1:0] b_in ; |
---|
1368 | output [PWID -1:0] p_out ; |
---|
1369 | |
---|
1370 | //*********************************************** |
---|
1371 | //Internal signal |
---|
1372 | //*********************************************** |
---|
1373 | wire [AWID -1:0] a_tmp ; |
---|
1374 | wire a_sgn ; |
---|
1375 | reg a_sgn_pipe ; |
---|
1376 | reg [PWID -1:0] p_tmp ; |
---|
1377 | wire [PWID -1:0] p_tmp2 ; |
---|
1378 | //*********************************************** |
---|
1379 | // Main body of code |
---|
1380 | //*********************************************** |
---|
1381 | assign p_out = p_tmp2 ; |
---|
1382 | assign a_tmp = a_sgn ? ~a_in +1 : a_in ; |
---|
1383 | assign a_sgn = a_in [AWID -1] ; |
---|
1384 | |
---|
1385 | always @ (posedge clk) |
---|
1386 | p_tmp <= a_tmp * b_in ; |
---|
1387 | |
---|
1388 | always @ (posedge clk) |
---|
1389 | a_sgn_pipe <= a_sgn ; |
---|
1390 | |
---|
1391 | |
---|
1392 | assign p_tmp2 = a_sgn_pipe ? ~p_tmp +1 : p_tmp ; |
---|
1393 | |
---|
1394 | endmodule |
---|
1395 | |
---|
1396 | //******************************************************************************** |
---|
1397 | // File: soft_demapper.v |
---|
1398 | // Author: Yang Sun (ysun@rice.edu) |
---|
1399 | // Birth: $ 4/29/07 |
---|
1400 | // Des: Produce soft LLR for I/Q |
---|
1401 | // History: $ 4/29/07: Init coding |
---|
1402 | // $ 4/17/08: Added 16-QAM support |
---|
1403 | //******************************************************************************** |
---|
1404 | module soft_demapper ( |
---|
1405 | clk , |
---|
1406 | nrst , |
---|
1407 | start , |
---|
1408 | coding_en , |
---|
1409 | mod_level , |
---|
1410 | vin , |
---|
1411 | xk_index , |
---|
1412 | rx_i , |
---|
1413 | rx_q , |
---|
1414 | scale_qpsk , |
---|
1415 | scale_16qam , |
---|
1416 | soft_decoding , |
---|
1417 | in_fullrate , |
---|
1418 | sym_start , |
---|
1419 | hdr_mod_level , |
---|
1420 | vout , |
---|
1421 | llr_a , |
---|
1422 | llr_b |
---|
1423 | ) ; |
---|
1424 | |
---|
1425 | input clk ; |
---|
1426 | input nrst ; |
---|
1427 | input start ; |
---|
1428 | input coding_en ; |
---|
1429 | input [3:0] mod_level ; // 0=Invalid, 1=BPSK, 2=QPSK, 4=16-QAM |
---|
1430 | input vin ; // valid input |
---|
1431 | input [5:0] xk_index ; // FFT index |
---|
1432 | input [15:0] rx_i ; // FIX_16_15 |
---|
1433 | input [15:0] rx_q ; // FIX_16_15 |
---|
1434 | input [3:0] scale_qpsk ; // 0~15 sclae factor |
---|
1435 | input [4:0] scale_16qam ; // 0~31 sclae factor |
---|
1436 | input soft_decoding ; |
---|
1437 | input in_fullrate ; |
---|
1438 | |
---|
1439 | output sym_start ; |
---|
1440 | output [3:0] hdr_mod_level ; |
---|
1441 | output vout ; |
---|
1442 | output [3:0] llr_a ; |
---|
1443 | output [3:0] llr_b ; |
---|
1444 | |
---|
1445 | |
---|
1446 | //================================================ |
---|
1447 | //Internal signal |
---|
1448 | //================================================ |
---|
1449 | wire mod_vld ; |
---|
1450 | reg mod_vld_d ; |
---|
1451 | reg mod_vld_dd ; |
---|
1452 | reg mod_vld_ddd ; |
---|
1453 | wire llr_vld ; |
---|
1454 | wire [7:0] recv_fix_8_7 ; |
---|
1455 | wire [12:0] soft_a_mult ; |
---|
1456 | wire [12:0] soft_b_mult ; |
---|
1457 | wire [3:0] soft_a_round ; |
---|
1458 | wire [3:0] soft_b_round ; |
---|
1459 | |
---|
1460 | reg [7:0] rx_q_d ; |
---|
1461 | reg [7:0] rx_i_d ; |
---|
1462 | |
---|
1463 | wire [7:0] soft_a ; |
---|
1464 | reg [7:0] soft_b ; |
---|
1465 | |
---|
1466 | reg [3:0] hard_a ; |
---|
1467 | reg [3:0] hard_b ; |
---|
1468 | |
---|
1469 | reg [3:0] hard_a_s0 ; |
---|
1470 | reg [3:0] hard_b_s0 ; |
---|
1471 | wire [8:0] abs_tmp ; |
---|
1472 | wire [7:0] abs_tmp_sat ; |
---|
1473 | |
---|
1474 | wire [4:0] llr_scale ; |
---|
1475 | |
---|
1476 | reg [7:0] input_cnt ; |
---|
1477 | reg bpsk_sel ; |
---|
1478 | wire mod_ld ; |
---|
1479 | reg [3:0] mod_level_lat ; |
---|
1480 | wire [3:0] mod_type ; |
---|
1481 | wire bpsk ; |
---|
1482 | wire qpsk ; |
---|
1483 | wire qam16 ; |
---|
1484 | reg first_sym ; |
---|
1485 | reg first_sym_d ; |
---|
1486 | reg first_sym_dd ; |
---|
1487 | reg [3:0] hdr_mod_level_lat ; |
---|
1488 | |
---|
1489 | //================================================ |
---|
1490 | // Main body of code |
---|
1491 | //================================================ |
---|
1492 | assign llr_a = (soft_decoding & coding_en) ? soft_a_round : hard_a_s0 ; |
---|
1493 | assign llr_b = (soft_decoding & coding_en) ? soft_b_round : hard_b_s0 ; |
---|
1494 | assign vout = llr_vld ; |
---|
1495 | assign sym_start = vin & (xk_index == 0) ; |
---|
1496 | |
---|
1497 | |
---|
1498 | assign hdr_mod_level = hdr_mod_level_lat ; |
---|
1499 | |
---|
1500 | // 16-QAM |
---|
1501 | always @ (posedge clk or negedge nrst) |
---|
1502 | if(~nrst) |
---|
1503 | rx_q_d <= 0 ; |
---|
1504 | else if (vin) |
---|
1505 | rx_q_d <= rx_q [15:8] ; |
---|
1506 | |
---|
1507 | // BPSK |
---|
1508 | always @ (posedge clk or negedge nrst) |
---|
1509 | if(~nrst) |
---|
1510 | rx_i_d <= 0 ; |
---|
1511 | else if (mod_vld_d) |
---|
1512 | rx_i_d <= rx_i [15:8] ; |
---|
1513 | |
---|
1514 | assign mod_ld = vin & (xk_index == 1) ; |
---|
1515 | always @ (posedge clk or negedge nrst) |
---|
1516 | if(~nrst) |
---|
1517 | mod_level_lat <= 2 ; |
---|
1518 | else if (mod_ld) |
---|
1519 | mod_level_lat <= mod_level ; |
---|
1520 | |
---|
1521 | assign mod_type = mod_ld ? mod_level : mod_level_lat ; |
---|
1522 | |
---|
1523 | always @ (posedge clk or negedge nrst) |
---|
1524 | if(~nrst) |
---|
1525 | first_sym <= 1'b0 ; |
---|
1526 | else if (start) |
---|
1527 | first_sym <= 1'b1 ; |
---|
1528 | else if (sym_start) |
---|
1529 | first_sym <= 1'b0 ; |
---|
1530 | |
---|
1531 | always @ (posedge clk or negedge nrst) |
---|
1532 | if(~nrst) |
---|
1533 | {first_sym_dd, first_sym_d} <= 2'd0 ; |
---|
1534 | else |
---|
1535 | {first_sym_dd, first_sym_d} <= {first_sym_d, first_sym} ; |
---|
1536 | |
---|
1537 | |
---|
1538 | always @ (posedge clk or negedge nrst) |
---|
1539 | if(~nrst) |
---|
1540 | hdr_mod_level_lat <= 2 ; |
---|
1541 | else if (first_sym_dd & (mod_ld)) |
---|
1542 | hdr_mod_level_lat <= mod_level ; |
---|
1543 | |
---|
1544 | // Trancate 16_15 to 8_7 |
---|
1545 | //assign recv_fix_8_7 = in_fullrate ? (mod_type == 1 ? rx_i_s0 : (vin ? rx_i [15:8] : rx_q_s0)) : rx_i[15:8] ; |
---|
1546 | |
---|
1547 | assign bpsk = (mod_type == 1) ; |
---|
1548 | assign qpsk = (mod_type == 2) ; |
---|
1549 | assign qam16 =(mod_type == 4) ; |
---|
1550 | |
---|
1551 | assign recv_fix_8_7 = bpsk ? rx_i_d : (vin ? rx_i[15:8] : rx_q_d) ; |
---|
1552 | |
---|
1553 | //assign abs_tmp = recv_fix_8_7 [7] ? -recv_fix_8_7 : recv_fix_8_7 ; |
---|
1554 | assign abs_tmp = (recv_fix_8_7 ^{8{recv_fix_8_7[7]}}) + recv_fix_8_7[7] ; |
---|
1555 | assign abs_tmp_sat = abs_tmp[8] ? 8'hff : abs_tmp[7:0] ; |
---|
1556 | |
---|
1557 | assign soft_a = recv_fix_8_7 ; |
---|
1558 | assign llr_scale = (bpsk | qpsk) ? scale_qpsk : scale_16qam ; |
---|
1559 | |
---|
1560 | always @* |
---|
1561 | begin |
---|
1562 | if (bpsk) // BPSK |
---|
1563 | soft_b = rx_i[15:8] ; |
---|
1564 | else if (qpsk) // QPSK |
---|
1565 | soft_b = rx_q[15:8] ; |
---|
1566 | else // 16-QAM |
---|
1567 | soft_b = 8'b0100_0000 - abs_tmp_sat ; // 0.5 - |Y| |
---|
1568 | end |
---|
1569 | |
---|
1570 | always @ (posedge clk or negedge nrst) |
---|
1571 | if(~nrst) |
---|
1572 | begin |
---|
1573 | hard_a <= 1'b0 ; |
---|
1574 | hard_b <= 1'b0 ; |
---|
1575 | end |
---|
1576 | else |
---|
1577 | begin |
---|
1578 | hard_a <= soft_a [7] ? 4'hf : 4'h1 ; |
---|
1579 | hard_b <= soft_b [7] ? 4'hf : 4'h1 ; |
---|
1580 | end |
---|
1581 | |
---|
1582 | always @ (posedge clk or negedge nrst) |
---|
1583 | if(~nrst) |
---|
1584 | begin |
---|
1585 | hard_a_s0 <= 1'b0 ; |
---|
1586 | hard_b_s0 <= 1'b0 ; |
---|
1587 | end |
---|
1588 | else |
---|
1589 | begin |
---|
1590 | hard_a_s0 <= hard_a ; |
---|
1591 | hard_b_s0 <= hard_b ; |
---|
1592 | end |
---|
1593 | |
---|
1594 | //================================ |
---|
1595 | // signed MULT |
---|
1596 | //================================ |
---|
1597 | smult smult_a ( |
---|
1598 | .clk (clk ), //I |
---|
1599 | .a_in (soft_a ), //I |
---|
1600 | .b_in (llr_scale ), //I |
---|
1601 | .p_out (soft_a_mult) //O |
---|
1602 | ) ; |
---|
1603 | |
---|
1604 | //================================ |
---|
1605 | // signed MULT |
---|
1606 | //================================ |
---|
1607 | smult smult_b ( |
---|
1608 | .clk (clk ), //I |
---|
1609 | .a_in (soft_b ), //I |
---|
1610 | .b_in (llr_scale ), //I |
---|
1611 | .p_out (soft_b_mult) //O |
---|
1612 | ) ; |
---|
1613 | |
---|
1614 | //================================ |
---|
1615 | // Round |
---|
1616 | //================================ |
---|
1617 | round_data data_i ( |
---|
1618 | .clk (clk ), //I |
---|
1619 | .din (soft_a_mult ), //I |
---|
1620 | .dout (soft_a_round ) //O |
---|
1621 | ) ; |
---|
1622 | |
---|
1623 | //================================ |
---|
1624 | // Round |
---|
1625 | //================================ |
---|
1626 | round_data data_q ( |
---|
1627 | .clk (clk ), //I |
---|
1628 | .din (soft_b_mult ), //I |
---|
1629 | .dout (soft_b_round ) //O |
---|
1630 | ) ; |
---|
1631 | |
---|
1632 | //assign mod_pipe = in_fullrate ? (mod_type == 1 ? (mod_s0 & bpsk_sel) : (mod_type == 2 ? mod_s0 : (mod_s0 | mod_s1))) : mod_s0 ; |
---|
1633 | assign llr_vld = bpsk ? (mod_vld_dd & bpsk_sel) : (qpsk ? mod_vld_dd : (mod_vld_dd | mod_vld_ddd)) ; |
---|
1634 | |
---|
1635 | assign mod_vld = vin & (mod_level != 0) ; |
---|
1636 | always @ (posedge clk ) |
---|
1637 | {mod_vld_ddd, mod_vld_dd,mod_vld_d} <= {mod_vld_dd, mod_vld_d,mod_vld} ; |
---|
1638 | |
---|
1639 | always @ (posedge clk or negedge nrst) |
---|
1640 | if (~nrst) |
---|
1641 | input_cnt <= 0 ; |
---|
1642 | else if (start) |
---|
1643 | input_cnt <= 0 ; |
---|
1644 | else if (llr_vld) |
---|
1645 | begin |
---|
1646 | if (input_cnt != 192) |
---|
1647 | input_cnt <= input_cnt +1 ; |
---|
1648 | end |
---|
1649 | |
---|
1650 | always @ (posedge clk or negedge nrst) |
---|
1651 | if (~nrst) |
---|
1652 | bpsk_sel <= 1'b0 ; |
---|
1653 | else if (start) |
---|
1654 | bpsk_sel <= 1'b0 ; |
---|
1655 | else if (mod_vld_dd) |
---|
1656 | bpsk_sel <= ~bpsk_sel ; |
---|
1657 | |
---|
1658 | endmodule |
---|
1659 | |
---|
1660 | |
---|
1661 | //******************************************************************************** |
---|
1662 | // File: unc_decoder.v |
---|
1663 | // Author: Yang Sun (ysun@rice.edu) |
---|
1664 | // Birth: $ 12/1/07 |
---|
1665 | // Des: decoder system |
---|
1666 | // History: $ 12/1/07, Uncoded decoder |
---|
1667 | // $ 10/11/08, added BPSK |
---|
1668 | //******************************************************************************** |
---|
1669 | module unc_decoder ( |
---|
1670 | clk , // clock |
---|
1671 | nrst , // n reset |
---|
1672 | hd_a , // hard decision of a |
---|
1673 | hd_b , // hard decision of b |
---|
1674 | start , // start decoding pulse |
---|
1675 | vin , // valid input |
---|
1676 | vout , // valid output |
---|
1677 | dout // byte out |
---|
1678 | ) ; |
---|
1679 | |
---|
1680 | input clk ; |
---|
1681 | input nrst ; |
---|
1682 | input hd_a ; |
---|
1683 | input hd_b ; |
---|
1684 | input start ; |
---|
1685 | input vin ; |
---|
1686 | output vout ; |
---|
1687 | output [7:0] dout ; |
---|
1688 | |
---|
1689 | //============================== |
---|
1690 | //Internal signal |
---|
1691 | //============================== |
---|
1692 | reg [7:2] tmpd ; |
---|
1693 | reg [1:0] cnt ; |
---|
1694 | wire [1:0] data_2b ; |
---|
1695 | |
---|
1696 | //============================== |
---|
1697 | // Main RTL code |
---|
1698 | //============================== |
---|
1699 | assign data_2b = {hd_a, hd_b} ; |
---|
1700 | always @ (posedge clk or negedge nrst) |
---|
1701 | if (~nrst) |
---|
1702 | tmpd <= 0 ; |
---|
1703 | else if (start) |
---|
1704 | tmpd <= 0 ; |
---|
1705 | else if (vin) |
---|
1706 | begin |
---|
1707 | case (cnt) |
---|
1708 | 3'd0: tmpd [7:6] <= data_2b ; |
---|
1709 | 3'd1: tmpd [5:4] <= data_2b ; |
---|
1710 | 3'd2: tmpd [3:2] <= data_2b ; |
---|
1711 | default: tmpd <= tmpd ; |
---|
1712 | endcase |
---|
1713 | end |
---|
1714 | |
---|
1715 | always @ (posedge clk or negedge nrst) |
---|
1716 | if (~nrst) |
---|
1717 | cnt <= 0 ; |
---|
1718 | else if (start) |
---|
1719 | cnt <= 0 ; |
---|
1720 | else if (vin) |
---|
1721 | cnt <= cnt +1 ; |
---|
1722 | |
---|
1723 | assign vout = vin & (cnt == 3) ; |
---|
1724 | assign dout = {tmpd, data_2b} ; |
---|
1725 | |
---|
1726 | endmodule |
---|
1727 | |
---|
1728 | //************************************************************** |
---|
1729 | // File: unpack_m2n.v |
---|
1730 | // Author: Yang Sun (ysun@rice.edu) |
---|
1731 | // Birth: $ 1/15/07 |
---|
1732 | // Des: unpack from M bit to N bit, M > N |
---|
1733 | // History: $ 1/15/07, Init coding |
---|
1734 | // $ 1/21/07, K = 7 |
---|
1735 | // $ 3/23, Fixed a naming problem for sysgen |
---|
1736 | // Can not use VHDL reserved key world |
---|
1737 | // $ 12/1/07: Updated |
---|
1738 | //************************************************************** |
---|
1739 | |
---|
1740 | module unpack_m2n ( |
---|
1741 | clk , // I, clock |
---|
1742 | nrst , // I, n reset |
---|
1743 | start , // I, start pulse |
---|
1744 | din , // I, data input |
---|
1745 | vin , // I, valid input |
---|
1746 | dout , // O, data output |
---|
1747 | vout , // O, valid output |
---|
1748 | remain , // I, remain |
---|
1749 | last , // I, last data |
---|
1750 | done // O, done |
---|
1751 | ) ; |
---|
1752 | |
---|
1753 | parameter BITM = 40 ; |
---|
1754 | parameter BITN = 8 ; |
---|
1755 | parameter LW = 6 ; |
---|
1756 | |
---|
1757 | input clk ; |
---|
1758 | input nrst ; |
---|
1759 | input start ; |
---|
1760 | input [BITM-1 :0] din ; |
---|
1761 | input vin ; |
---|
1762 | input [LW -1:0] remain ; |
---|
1763 | input last ; |
---|
1764 | |
---|
1765 | output [BITN-1 :0] dout ; |
---|
1766 | output vout ; |
---|
1767 | output done ; |
---|
1768 | |
---|
1769 | //================================================ |
---|
1770 | //Internal signal |
---|
1771 | //================================================ |
---|
1772 | reg [BITM + BITN -1 :0] sreg ; |
---|
1773 | wire [BITM + BITN -1 :0] sreg_next ; |
---|
1774 | reg [LW -1 : 0] cnt ; |
---|
1775 | wire rd ; |
---|
1776 | wire [BITN-1 :0] data ; |
---|
1777 | wire [BITM + BITN -1 :0] tmp ; |
---|
1778 | wire [BITM + BITN -1 :0] tmp2 ; |
---|
1779 | wire [LW -1 : 0] shift ; |
---|
1780 | reg last_i ; |
---|
1781 | reg last_byte_s0 ; |
---|
1782 | wire last_byte ; |
---|
1783 | |
---|
1784 | //================================================ |
---|
1785 | // Main RTL code |
---|
1786 | //================================================ |
---|
1787 | assign dout = data ; |
---|
1788 | assign vout = rd ; |
---|
1789 | |
---|
1790 | always @ (posedge clk or negedge nrst) |
---|
1791 | if (~nrst) |
---|
1792 | cnt <= 0 ; |
---|
1793 | else if (start) |
---|
1794 | cnt <= 0 ; |
---|
1795 | else if (vin) |
---|
1796 | begin |
---|
1797 | if (~last) |
---|
1798 | cnt <= cnt + BITM ; |
---|
1799 | else |
---|
1800 | cnt <= cnt + remain ; |
---|
1801 | end |
---|
1802 | else if (rd) |
---|
1803 | cnt <= cnt - BITN ; |
---|
1804 | |
---|
1805 | assign rd = cnt >= BITN ; |
---|
1806 | assign data = sreg [BITM + BITN -1 : BITM] ; |
---|
1807 | assign tmp = {{BITM{1'b0}}, din} ; |
---|
1808 | assign shift = BITN - cnt ; |
---|
1809 | assign tmp2 = (tmp << shift) | sreg ; |
---|
1810 | assign sreg_next = vin ? tmp2 : rd ? {sreg[BITM -1 : 0], {BITN{1'b0}}} : sreg ; |
---|
1811 | |
---|
1812 | always @ (posedge clk or negedge nrst) |
---|
1813 | if (~nrst) |
---|
1814 | sreg <= 0 ; |
---|
1815 | else if (start) |
---|
1816 | sreg <= 0 ; |
---|
1817 | else |
---|
1818 | sreg <= sreg_next ; |
---|
1819 | |
---|
1820 | always @ (posedge clk or negedge nrst) |
---|
1821 | if (~nrst) |
---|
1822 | last_i <= 1'b0 ; |
---|
1823 | else if (start) |
---|
1824 | last_i <= 1'b0 ; |
---|
1825 | else if (vin & last) |
---|
1826 | last_i <= 1'b1 ; |
---|
1827 | |
---|
1828 | assign last_byte = last_i && cnt < BITN ; |
---|
1829 | always @ (posedge clk) |
---|
1830 | last_byte_s0 <= last_byte ; |
---|
1831 | |
---|
1832 | assign done = ~last_byte_s0 & last_byte ; |
---|
1833 | |
---|
1834 | endmodule |
---|
1835 | //***************************************************************** |
---|
1836 | // File: vb_decoder_top.v |
---|
1837 | // Author: Yang Sun (ysun@rice.edu) |
---|
1838 | // Birth: $ 1/15/07 |
---|
1839 | // Des: viterbi decoder top level |
---|
1840 | // Take 5 bit soft value is [-16 : +15] |
---|
1841 | // K = 3. g0 =7, g1 = 5 |
---|
1842 | // K = 7. g0 = 133, g1 = 171 |
---|
1843 | // History: $ 1/15/07, Init coding |
---|
1844 | // $ 1/21/07, K = 7 |
---|
1845 | // $ 1/27/07, Change to LLR domain |
---|
1846 | // $ 2/4/07, Support puncture 2/3, 3/4 |
---|
1847 | // $ 3/22/07, Remove puncture and iq buffer for WARP |
---|
1848 | // $ 3/23/07, Fixed a naming problem for sysgen |
---|
1849 | // Can not use VHDL reserved key world |
---|
1850 | // $ 4/20/07, K = 7 |
---|
1851 | // $ 4/22/07, Change quantilization to -4 ~ 4 9-level |
---|
1852 | // $ 12/1/07: Modified for OFDM V7 |
---|
1853 | //***************************************************************** |
---|
1854 | module vb_decoder_top ( |
---|
1855 | clk , // I, clock |
---|
1856 | nrst , // I, n reset |
---|
1857 | packet_start, // I, packet start pulse |
---|
1858 | packet_end , // I, packet end pulse |
---|
1859 | zero_tail , // I, the code is zero terminated |
---|
1860 | vin , // I, valid input |
---|
1861 | llr_b1 , // I, 1st LLR |
---|
1862 | llr_b0 , // I, 2nd LLR |
---|
1863 | vout , // O, valid output |
---|
1864 | dout_in_byte, // O, decoded output in byte |
---|
1865 | done // O, decoding done |
---|
1866 | ) ; |
---|
1867 | |
---|
1868 | parameter SW = 4 ; // soft input precision |
---|
1869 | parameter M = 7 ; // Metric precision |
---|
1870 | parameter R = 48 ; // reliable trace |
---|
1871 | parameter C = 40 ; // unreliable trace |
---|
1872 | parameter L = 88 ; // total trace depth |
---|
1873 | parameter LW = 7 ; // L width |
---|
1874 | parameter K = 7 ; // constraint length |
---|
1875 | parameter N = 64 ; // number of states |
---|
1876 | parameter TR = 128 ; // trace buffer depth |
---|
1877 | parameter TRW = 7 ; // trace buffer address width |
---|
1878 | |
---|
1879 | input clk ; // system clock |
---|
1880 | input nrst ; // active low reset |
---|
1881 | input packet_start ; // start of packet pulse |
---|
1882 | input zero_tail ; // 1 = the code is terminated with 0, 0 = no termination |
---|
1883 | input packet_end ; // end of packet pulse |
---|
1884 | input vin ; // data valid input |
---|
1885 | input [SW -1:0] llr_b1 ; // soft value for bit1 |
---|
1886 | input [SW -1:0] llr_b0 ; // soft value for bit0 |
---|
1887 | |
---|
1888 | output done ; |
---|
1889 | output vout ; |
---|
1890 | output [7:0] dout_in_byte ; |
---|
1891 | |
---|
1892 | //============================================= |
---|
1893 | //Internal signal |
---|
1894 | //============================================= |
---|
1895 | wire [LW -1:0] remain ; |
---|
1896 | wire dec_vout ; |
---|
1897 | wire [R-1:0] dec_dout ; |
---|
1898 | wire dec_done ; |
---|
1899 | |
---|
1900 | //============================================= |
---|
1901 | // Main RTL code |
---|
1902 | //============================================= |
---|
1903 | |
---|
1904 | //================================================================ |
---|
1905 | // Viterbi decoder core logic |
---|
1906 | //================================================================ |
---|
1907 | viterbi_core #(SW, M, R, C, L, LW, K, N, TR, TRW) viterbi_core ( |
---|
1908 | .clk (clk ), //IN |
---|
1909 | .nrst (nrst ), //IN |
---|
1910 | .packet_start (packet_start ), //IN |
---|
1911 | .packet_end (packet_end ), //IN |
---|
1912 | .zero_tail (zero_tail ), |
---|
1913 | `ifdef INT_PUNC //Internal puncture |
---|
1914 | .dv_in (llr_valid ), //IN |
---|
1915 | .llr1 (llr1_depunc ), //IN[SW-1:0] |
---|
1916 | .llr0 (llr0_depunc ), //IN[SW-1:0] |
---|
1917 | `else |
---|
1918 | .dv_in (vin ), //IN |
---|
1919 | .llr1 (llr_b1 ), //IN[SW-1:0] |
---|
1920 | .llr0 (llr_b0 ), //IN[SW-1:0] |
---|
1921 | `endif |
---|
1922 | .remain (remain ), //OUT[LW -1:0] |
---|
1923 | .done (dec_done ), //OUT |
---|
1924 | .dv_out (dec_vout ), //OUT |
---|
1925 | .dout (dec_dout ) //OUT[R -1:0] |
---|
1926 | ) ; |
---|
1927 | |
---|
1928 | //============================================= |
---|
1929 | // x to 8bit unpacking |
---|
1930 | //============================================= |
---|
1931 | unpack_m2n #(R, 8, LW) unpack_Rto8 ( |
---|
1932 | .clk (clk ), //IN |
---|
1933 | .nrst (nrst ), //IN |
---|
1934 | .start (packet_start ), //IN |
---|
1935 | .din (dec_dout ), //IN[R -1:0] |
---|
1936 | .vin (dec_vout ), //IN |
---|
1937 | .last (dec_done ), //IN |
---|
1938 | .remain (remain ), //IN[LW -1:0] |
---|
1939 | .dout (dout_in_byte ), //OUT |
---|
1940 | .vout (vout ), //OUT |
---|
1941 | .done (done ) //OUT |
---|
1942 | ) ; |
---|
1943 | |
---|
1944 | endmodule |
---|
1945 | |
---|
1946 | //************************************************************** |
---|
1947 | // File: viterbi_core |
---|
1948 | // Author: Yang Sun (ysun@rice.edu) |
---|
1949 | // Birth: $ 1/14/07 |
---|
1950 | // Des: The top level of viterbi decoder |
---|
1951 | // Take 4 bit soft value is [-8 : +7] |
---|
1952 | // K = 3. g0 = 7, g1 = 5 |
---|
1953 | // K = 5, g0 (A) = 1 + x + x^2 + x^4, g1 (B) = 1 + x^3 + x^4 |
---|
1954 | // K = 7, g0 (A) = 1 + x^2 + x^3 + x^4 + x^5 |
---|
1955 | // g1 (B) = 1 + x + x^2 + x^3 + x^6 |
---|
1956 | // History: $ 1/14/07, Init coding, K = 3 |
---|
1957 | // $ 1/22/07, K = 5 |
---|
1958 | // $ 1/26/07, Updated |
---|
1959 | // $ 1/27/07, Change to LLR domain |
---|
1960 | // $ 2/18/07, Supported K = 7 |
---|
1961 | // $ 2/23/07, Added pipeline to max_metric |
---|
1962 | // $ 12/1/07, Updated |
---|
1963 | //************************************************************** |
---|
1964 | //`define ZERO_TERM |
---|
1965 | |
---|
1966 | module viterbi_core ( |
---|
1967 | clk , // I, clock |
---|
1968 | nrst , // I, n reset |
---|
1969 | packet_start, // I, packet start pulse |
---|
1970 | zero_tail , // I, the code is zero terminated |
---|
1971 | dv_in , // I, data valid input |
---|
1972 | llr0 , // I, LLR 2nd |
---|
1973 | llr1 , // I, LLR 1st |
---|
1974 | packet_end , // I, packet end pulse |
---|
1975 | dv_out , // O, data valid out |
---|
1976 | dout , // O, data out |
---|
1977 | done , // O, done pulse |
---|
1978 | remain // O, remain data cnt |
---|
1979 | ) ; |
---|
1980 | |
---|
1981 | parameter SW = 4 ; // soft input precision |
---|
1982 | parameter M = 7 ; // metric width |
---|
1983 | |
---|
1984 | parameter R = 48 ; // reliable trace |
---|
1985 | parameter C = 40 ; // unreliable trace |
---|
1986 | parameter L = 88 ; // total trace depth |
---|
1987 | parameter LW = 7 ; // L width |
---|
1988 | |
---|
1989 | parameter K = 7 ; // constraint length |
---|
1990 | parameter N = 64 ; // number of states = 2^(K-1) |
---|
1991 | parameter TR = 128 ; // trace buffer |
---|
1992 | parameter TRW = 7 ; // trace |
---|
1993 | |
---|
1994 | input clk ; // system clock |
---|
1995 | input nrst ; // active low reset |
---|
1996 | input packet_start ; // start of packet pulse |
---|
1997 | input zero_tail ; // 1 = the code is terminated with 0, 0 = no termination |
---|
1998 | input packet_end ; // end of packet pulse |
---|
1999 | input dv_in ; // data valid input |
---|
2000 | input [SW -1:0] llr1 ; // LLR soft value for bit1, LLR = log(Pr(ci=0/ri)/Pr(ci=1/ri)) |
---|
2001 | input [SW -1:0] llr0 ; // LLR soft value for bit0, LLR = log(Pr(ci=0/ri)/Pr(ci=1/ri)) |
---|
2002 | |
---|
2003 | output done ; |
---|
2004 | output [LW -1:0] remain ; |
---|
2005 | output dv_out ; |
---|
2006 | output [R-1:0] dout ; |
---|
2007 | |
---|
2008 | //====================================== |
---|
2009 | //Internal signal |
---|
2010 | //====================================== |
---|
2011 | wire [SW:0] branch_00 ; |
---|
2012 | wire [SW:0] branch_01 ; |
---|
2013 | wire [SW:0] branch_10 ; |
---|
2014 | wire [SW:0] branch_11 ; |
---|
2015 | |
---|
2016 | wire [SW:0] branch_A_0 ; |
---|
2017 | wire [SW:0] branch_B_0 ; |
---|
2018 | wire [SW:0] branch_A_1 ; |
---|
2019 | wire [SW:0] branch_B_1 ; |
---|
2020 | wire [SW:0] branch_A_2 ; |
---|
2021 | wire [SW:0] branch_B_2 ; |
---|
2022 | wire [SW:0] branch_A_3 ; |
---|
2023 | wire [SW:0] branch_B_3 ; |
---|
2024 | wire [SW:0] branch_A_4 ; |
---|
2025 | wire [SW:0] branch_B_4 ; |
---|
2026 | wire [SW:0] branch_A_5 ; |
---|
2027 | wire [SW:0] branch_B_5 ; |
---|
2028 | wire [SW:0] branch_A_6 ; |
---|
2029 | wire [SW:0] branch_B_6 ; |
---|
2030 | wire [SW:0] branch_A_7 ; |
---|
2031 | wire [SW:0] branch_B_7 ; |
---|
2032 | wire [SW:0] branch_A_8 ; |
---|
2033 | wire [SW:0] branch_B_8 ; |
---|
2034 | wire [SW:0] branch_A_9 ; |
---|
2035 | wire [SW:0] branch_B_9 ; |
---|
2036 | wire [SW:0] branch_A_10 ; |
---|
2037 | wire [SW:0] branch_B_10 ; |
---|
2038 | wire [SW:0] branch_A_11 ; |
---|
2039 | wire [SW:0] branch_B_11 ; |
---|
2040 | wire [SW:0] branch_A_12 ; |
---|
2041 | wire [SW:0] branch_B_12 ; |
---|
2042 | wire [SW:0] branch_A_13 ; |
---|
2043 | wire [SW:0] branch_B_13 ; |
---|
2044 | wire [SW:0] branch_A_14 ; |
---|
2045 | wire [SW:0] branch_B_14 ; |
---|
2046 | wire [SW:0] branch_A_15 ; |
---|
2047 | wire [SW:0] branch_B_15 ; |
---|
2048 | wire [SW:0] branch_A_16 ; |
---|
2049 | wire [SW:0] branch_B_16 ; |
---|
2050 | wire [SW:0] branch_A_17; |
---|
2051 | wire [SW:0] branch_B_17; |
---|
2052 | wire [SW:0] branch_A_18; |
---|
2053 | wire [SW:0] branch_B_18; |
---|
2054 | wire [SW:0] branch_A_19; |
---|
2055 | wire [SW:0] branch_B_19; |
---|
2056 | wire [SW:0] branch_A_20; |
---|
2057 | wire [SW:0] branch_B_20; |
---|
2058 | wire [SW:0] branch_A_21; |
---|
2059 | wire [SW:0] branch_B_21; |
---|
2060 | wire [SW:0] branch_A_22; |
---|
2061 | wire [SW:0] branch_B_22; |
---|
2062 | wire [SW:0] branch_A_23; |
---|
2063 | wire [SW:0] branch_B_23; |
---|
2064 | wire [SW:0] branch_A_24; |
---|
2065 | wire [SW:0] branch_B_24; |
---|
2066 | wire [SW:0] branch_A_25; |
---|
2067 | wire [SW:0] branch_B_25; |
---|
2068 | wire [SW:0] branch_A_26 ; |
---|
2069 | wire [SW:0] branch_B_26 ; |
---|
2070 | wire [SW:0] branch_A_27 ; |
---|
2071 | wire [SW:0] branch_B_27 ; |
---|
2072 | wire [SW:0] branch_A_28 ; |
---|
2073 | wire [SW:0] branch_B_28 ; |
---|
2074 | wire [SW:0] branch_A_29 ; |
---|
2075 | wire [SW:0] branch_B_29 ; |
---|
2076 | wire [SW:0] branch_A_30 ; |
---|
2077 | wire [SW:0] branch_B_30 ; |
---|
2078 | wire [SW:0] branch_A_31 ; |
---|
2079 | wire [SW:0] branch_B_31 ; |
---|
2080 | wire [SW:0] branch_A_32; |
---|
2081 | wire [SW:0] branch_B_32; |
---|
2082 | wire [SW:0] branch_A_33; |
---|
2083 | wire [SW:0] branch_B_33; |
---|
2084 | wire [SW:0] branch_A_34; |
---|
2085 | wire [SW:0] branch_B_34; |
---|
2086 | wire [SW:0] branch_A_35; |
---|
2087 | wire [SW:0] branch_B_35; |
---|
2088 | wire [SW:0] branch_A_36; |
---|
2089 | wire [SW:0] branch_B_36; |
---|
2090 | wire [SW:0] branch_A_37; |
---|
2091 | wire [SW:0] branch_B_37; |
---|
2092 | wire [SW:0] branch_A_38; |
---|
2093 | wire [SW:0] branch_B_38; |
---|
2094 | wire [SW:0] branch_A_39; |
---|
2095 | wire [SW:0] branch_B_39; |
---|
2096 | wire [SW:0] branch_A_40; |
---|
2097 | wire [SW:0] branch_B_40; |
---|
2098 | wire [SW:0] branch_A_41; |
---|
2099 | wire [SW:0] branch_B_41; |
---|
2100 | wire [SW:0] branch_A_42 ; |
---|
2101 | wire [SW:0] branch_B_42 ; |
---|
2102 | wire [SW:0] branch_A_43 ; |
---|
2103 | wire [SW:0] branch_B_43 ; |
---|
2104 | wire [SW:0] branch_A_44 ; |
---|
2105 | wire [SW:0] branch_B_44 ; |
---|
2106 | wire [SW:0] branch_A_45 ; |
---|
2107 | wire [SW:0] branch_B_45 ; |
---|
2108 | wire [SW:0] branch_A_46 ; |
---|
2109 | wire [SW:0] branch_B_46 ; |
---|
2110 | wire [SW:0] branch_A_47 ; |
---|
2111 | wire [SW:0] branch_B_47 ; |
---|
2112 | wire [SW:0] branch_A_48; |
---|
2113 | wire [SW:0] branch_B_48; |
---|
2114 | wire [SW:0] branch_A_49; |
---|
2115 | wire [SW:0] branch_B_49; |
---|
2116 | wire [SW:0] branch_A_50; |
---|
2117 | wire [SW:0] branch_B_50; |
---|
2118 | wire [SW:0] branch_A_51; |
---|
2119 | wire [SW:0] branch_B_51; |
---|
2120 | wire [SW:0] branch_A_52; |
---|
2121 | wire [SW:0] branch_B_52; |
---|
2122 | wire [SW:0] branch_A_53; |
---|
2123 | wire [SW:0] branch_B_53; |
---|
2124 | wire [SW:0] branch_A_54; |
---|
2125 | wire [SW:0] branch_B_54; |
---|
2126 | wire [SW:0] branch_A_55; |
---|
2127 | wire [SW:0] branch_B_55; |
---|
2128 | wire [SW:0] branch_A_56; |
---|
2129 | wire [SW:0] branch_B_56; |
---|
2130 | wire [SW:0] branch_A_57; |
---|
2131 | wire [SW:0] branch_B_57; |
---|
2132 | wire [SW:0] branch_A_58 ; |
---|
2133 | wire [SW:0] branch_B_58 ; |
---|
2134 | wire [SW:0] branch_A_59 ; |
---|
2135 | wire [SW:0] branch_B_59 ; |
---|
2136 | wire [SW:0] branch_A_60 ; |
---|
2137 | wire [SW:0] branch_B_60 ; |
---|
2138 | wire [SW:0] branch_A_61 ; |
---|
2139 | wire [SW:0] branch_B_61 ; |
---|
2140 | wire [SW:0] branch_A_62 ; |
---|
2141 | wire [SW:0] branch_B_62 ; |
---|
2142 | wire [SW:0] branch_A_63 ; |
---|
2143 | wire [SW:0] branch_B_63 ; |
---|
2144 | |
---|
2145 | reg [M -1:0] metric_0 ; |
---|
2146 | reg [M -1:0] metric_1 ; |
---|
2147 | reg [M -1:0] metric_2 ; |
---|
2148 | reg [M -1:0] metric_3 ; |
---|
2149 | reg [M -1:0] metric_4 ; |
---|
2150 | reg [M -1:0] metric_5 ; |
---|
2151 | reg [M -1:0] metric_6 ; |
---|
2152 | reg [M -1:0] metric_7 ; |
---|
2153 | reg [M -1:0] metric_8 ; |
---|
2154 | reg [M -1:0] metric_9 ; |
---|
2155 | reg [M -1:0] metric_10 ; |
---|
2156 | reg [M -1:0] metric_11 ; |
---|
2157 | reg [M -1:0] metric_12 ; |
---|
2158 | reg [M -1:0] metric_13 ; |
---|
2159 | reg [M -1:0] metric_14 ; |
---|
2160 | reg [M -1:0] metric_15 ; |
---|
2161 | reg [M -1:0] metric_16; |
---|
2162 | reg [M -1:0] metric_17; |
---|
2163 | reg [M -1:0] metric_18; |
---|
2164 | reg [M -1:0] metric_19; |
---|
2165 | reg [M -1:0] metric_20; |
---|
2166 | reg [M -1:0] metric_21; |
---|
2167 | reg [M -1:0] metric_22; |
---|
2168 | reg [M -1:0] metric_23; |
---|
2169 | reg [M -1:0] metric_24; |
---|
2170 | reg [M -1:0] metric_25; |
---|
2171 | reg [M -1:0] metric_26 ; |
---|
2172 | reg [M -1:0] metric_27 ; |
---|
2173 | reg [M -1:0] metric_28 ; |
---|
2174 | reg [M -1:0] metric_29 ; |
---|
2175 | reg [M -1:0] metric_30 ; |
---|
2176 | reg [M -1:0] metric_31 ; |
---|
2177 | reg [M -1:0] metric_32; |
---|
2178 | reg [M -1:0] metric_33; |
---|
2179 | reg [M -1:0] metric_34; |
---|
2180 | reg [M -1:0] metric_35; |
---|
2181 | reg [M -1:0] metric_36; |
---|
2182 | reg [M -1:0] metric_37; |
---|
2183 | reg [M -1:0] metric_38; |
---|
2184 | reg [M -1:0] metric_39; |
---|
2185 | reg [M -1:0] metric_40; |
---|
2186 | reg [M -1:0] metric_41; |
---|
2187 | reg [M -1:0] metric_42 ; |
---|
2188 | reg [M -1:0] metric_43 ; |
---|
2189 | reg [M -1:0] metric_44 ; |
---|
2190 | reg [M -1:0] metric_45 ; |
---|
2191 | reg [M -1:0] metric_46 ; |
---|
2192 | reg [M -1:0] metric_47 ; |
---|
2193 | reg [M -1:0] metric_48; |
---|
2194 | reg [M -1:0] metric_49; |
---|
2195 | reg [M -1:0] metric_50; |
---|
2196 | reg [M -1:0] metric_51; |
---|
2197 | reg [M -1:0] metric_52; |
---|
2198 | reg [M -1:0] metric_53; |
---|
2199 | reg [M -1:0] metric_54; |
---|
2200 | reg [M -1:0] metric_55; |
---|
2201 | reg [M -1:0] metric_56; |
---|
2202 | reg [M -1:0] metric_57; |
---|
2203 | reg [M -1:0] metric_58 ; |
---|
2204 | reg [M -1:0] metric_59 ; |
---|
2205 | reg [M -1:0] metric_60 ; |
---|
2206 | reg [M -1:0] metric_61 ; |
---|
2207 | reg [M -1:0] metric_62 ; |
---|
2208 | reg [M -1:0] metric_63 ; |
---|
2209 | |
---|
2210 | wire [M -1:0] metric_next_0 ; |
---|
2211 | wire [M -1:0] metric_next_1 ; |
---|
2212 | wire [M -1:0] metric_next_2 ; |
---|
2213 | wire [M -1:0] metric_next_3 ; |
---|
2214 | wire [M -1:0] metric_next_4 ; |
---|
2215 | wire [M -1:0] metric_next_5 ; |
---|
2216 | wire [M -1:0] metric_next_6 ; |
---|
2217 | wire [M -1:0] metric_next_7 ; |
---|
2218 | wire [M -1:0] metric_next_8 ; |
---|
2219 | wire [M -1:0] metric_next_9 ; |
---|
2220 | wire [M -1:0] metric_next_10 ; |
---|
2221 | wire [M -1:0] metric_next_11 ; |
---|
2222 | wire [M -1:0] metric_next_12 ; |
---|
2223 | wire [M -1:0] metric_next_13 ; |
---|
2224 | wire [M -1:0] metric_next_14 ; |
---|
2225 | wire [M -1:0] metric_next_15 ; |
---|
2226 | wire [M -1:0] metric_next_16; |
---|
2227 | wire [M -1:0] metric_next_17; |
---|
2228 | wire [M -1:0] metric_next_18; |
---|
2229 | wire [M -1:0] metric_next_19; |
---|
2230 | wire [M -1:0] metric_next_20; |
---|
2231 | wire [M -1:0] metric_next_21; |
---|
2232 | wire [M -1:0] metric_next_22; |
---|
2233 | wire [M -1:0] metric_next_23; |
---|
2234 | wire [M -1:0] metric_next_24; |
---|
2235 | wire [M -1:0] metric_next_25; |
---|
2236 | wire [M -1:0] metric_next_26 ; |
---|
2237 | wire [M -1:0] metric_next_27 ; |
---|
2238 | wire [M -1:0] metric_next_28 ; |
---|
2239 | wire [M -1:0] metric_next_29 ; |
---|
2240 | wire [M -1:0] metric_next_30 ; |
---|
2241 | wire [M -1:0] metric_next_31 ; |
---|
2242 | wire [M -1:0] metric_next_32; |
---|
2243 | wire [M -1:0] metric_next_33; |
---|
2244 | wire [M -1:0] metric_next_34; |
---|
2245 | wire [M -1:0] metric_next_35; |
---|
2246 | wire [M -1:0] metric_next_36; |
---|
2247 | wire [M -1:0] metric_next_37; |
---|
2248 | wire [M -1:0] metric_next_38; |
---|
2249 | wire [M -1:0] metric_next_39; |
---|
2250 | wire [M -1:0] metric_next_40; |
---|
2251 | wire [M -1:0] metric_next_41; |
---|
2252 | wire [M -1:0] metric_next_42 ; |
---|
2253 | wire [M -1:0] metric_next_43 ; |
---|
2254 | wire [M -1:0] metric_next_44 ; |
---|
2255 | wire [M -1:0] metric_next_45 ; |
---|
2256 | wire [M -1:0] metric_next_46 ; |
---|
2257 | wire [M -1:0] metric_next_47 ; |
---|
2258 | wire [M -1:0] metric_next_48; |
---|
2259 | wire [M -1:0] metric_next_49; |
---|
2260 | wire [M -1:0] metric_next_50; |
---|
2261 | wire [M -1:0] metric_next_51; |
---|
2262 | wire [M -1:0] metric_next_52; |
---|
2263 | wire [M -1:0] metric_next_53; |
---|
2264 | wire [M -1:0] metric_next_54; |
---|
2265 | wire [M -1:0] metric_next_55; |
---|
2266 | wire [M -1:0] metric_next_56; |
---|
2267 | wire [M -1:0] metric_next_57; |
---|
2268 | wire [M -1:0] metric_next_58 ; |
---|
2269 | wire [M -1:0] metric_next_59 ; |
---|
2270 | wire [M -1:0] metric_next_60 ; |
---|
2271 | wire [M -1:0] metric_next_61 ; |
---|
2272 | wire [M -1:0] metric_next_62 ; |
---|
2273 | wire [M -1:0] metric_next_63 ; |
---|
2274 | |
---|
2275 | wire [M -1:0] metric_A_0 ; |
---|
2276 | wire [M -1:0] metric_B_0 ; |
---|
2277 | wire [M -1:0] metric_A_1 ; |
---|
2278 | wire [M -1:0] metric_B_1 ; |
---|
2279 | wire [M -1:0] metric_A_2 ; |
---|
2280 | wire [M -1:0] metric_B_2 ; |
---|
2281 | wire [M -1:0] metric_A_3 ; |
---|
2282 | wire [M -1:0] metric_B_3 ; |
---|
2283 | wire [M -1:0] metric_A_4 ; |
---|
2284 | wire [M -1:0] metric_B_4 ; |
---|
2285 | wire [M -1:0] metric_A_5 ; |
---|
2286 | wire [M -1:0] metric_B_5 ; |
---|
2287 | wire [M -1:0] metric_A_6 ; |
---|
2288 | wire [M -1:0] metric_B_6 ; |
---|
2289 | wire [M -1:0] metric_A_7 ; |
---|
2290 | wire [M -1:0] metric_B_7 ; |
---|
2291 | wire [M -1:0] metric_A_8 ; |
---|
2292 | wire [M -1:0] metric_B_8 ; |
---|
2293 | wire [M -1:0] metric_A_9 ; |
---|
2294 | wire [M -1:0] metric_B_9 ; |
---|
2295 | wire [M -1:0] metric_A_10 ; |
---|
2296 | wire [M -1:0] metric_B_10 ; |
---|
2297 | wire [M -1:0] metric_A_11 ; |
---|
2298 | wire [M -1:0] metric_B_11 ; |
---|
2299 | wire [M -1:0] metric_A_12 ; |
---|
2300 | wire [M -1:0] metric_B_12 ; |
---|
2301 | wire [M -1:0] metric_A_13 ; |
---|
2302 | wire [M -1:0] metric_B_13 ; |
---|
2303 | wire [M -1:0] metric_A_14 ; |
---|
2304 | wire [M -1:0] metric_B_14 ; |
---|
2305 | wire [M -1:0] metric_A_15 ; |
---|
2306 | wire [M -1:0] metric_B_15 ; |
---|
2307 | wire [M -1:0] metric_A_16; |
---|
2308 | wire [M -1:0] metric_B_16; |
---|
2309 | wire [M -1:0] metric_A_17; |
---|
2310 | wire [M -1:0] metric_B_17; |
---|
2311 | wire [M -1:0] metric_A_18; |
---|
2312 | wire [M -1:0] metric_B_18; |
---|
2313 | wire [M -1:0] metric_A_19; |
---|
2314 | wire [M -1:0] metric_B_19; |
---|
2315 | wire [M -1:0] metric_A_20; |
---|
2316 | wire [M -1:0] metric_B_20; |
---|
2317 | wire [M -1:0] metric_A_21; |
---|
2318 | wire [M -1:0] metric_B_21; |
---|
2319 | wire [M -1:0] metric_A_22; |
---|
2320 | wire [M -1:0] metric_B_22; |
---|
2321 | wire [M -1:0] metric_A_23; |
---|
2322 | wire [M -1:0] metric_B_23; |
---|
2323 | wire [M -1:0] metric_A_24; |
---|
2324 | wire [M -1:0] metric_B_24; |
---|
2325 | wire [M -1:0] metric_A_25; |
---|
2326 | wire [M -1:0] metric_B_25; |
---|
2327 | wire [M -1:0] metric_A_26 ; |
---|
2328 | wire [M -1:0] metric_B_26 ; |
---|
2329 | wire [M -1:0] metric_A_27 ; |
---|
2330 | wire [M -1:0] metric_B_27 ; |
---|
2331 | wire [M -1:0] metric_A_28 ; |
---|
2332 | wire [M -1:0] metric_B_28 ; |
---|
2333 | wire [M -1:0] metric_A_29 ; |
---|
2334 | wire [M -1:0] metric_B_29 ; |
---|
2335 | wire [M -1:0] metric_A_30 ; |
---|
2336 | wire [M -1:0] metric_B_30 ; |
---|
2337 | wire [M -1:0] metric_A_31 ; |
---|
2338 | wire [M -1:0] metric_B_31 ; |
---|
2339 | wire [M -1:0] metric_A_32; |
---|
2340 | wire [M -1:0] metric_B_32; |
---|
2341 | wire [M -1:0] metric_A_33; |
---|
2342 | wire [M -1:0] metric_B_33; |
---|
2343 | wire [M -1:0] metric_A_34; |
---|
2344 | wire [M -1:0] metric_B_34; |
---|
2345 | wire [M -1:0] metric_A_35; |
---|
2346 | wire [M -1:0] metric_B_35; |
---|
2347 | wire [M -1:0] metric_A_36; |
---|
2348 | wire [M -1:0] metric_B_36; |
---|
2349 | wire [M -1:0] metric_A_37; |
---|
2350 | wire [M -1:0] metric_B_37; |
---|
2351 | wire [M -1:0] metric_A_38; |
---|
2352 | wire [M -1:0] metric_B_38; |
---|
2353 | wire [M -1:0] metric_A_39; |
---|
2354 | wire [M -1:0] metric_B_39; |
---|
2355 | wire [M -1:0] metric_A_40; |
---|
2356 | wire [M -1:0] metric_B_40; |
---|
2357 | wire [M -1:0] metric_A_41; |
---|
2358 | wire [M -1:0] metric_B_41; |
---|
2359 | wire [M -1:0] metric_A_42 ; |
---|
2360 | wire [M -1:0] metric_B_42 ; |
---|
2361 | wire [M -1:0] metric_A_43 ; |
---|
2362 | wire [M -1:0] metric_B_43 ; |
---|
2363 | wire [M -1:0] metric_A_44 ; |
---|
2364 | wire [M -1:0] metric_B_44 ; |
---|
2365 | wire [M -1:0] metric_A_45 ; |
---|
2366 | wire [M -1:0] metric_B_45 ; |
---|
2367 | wire [M -1:0] metric_A_46 ; |
---|
2368 | wire [M -1:0] metric_B_46 ; |
---|
2369 | wire [M -1:0] metric_A_47 ; |
---|
2370 | wire [M -1:0] metric_B_47 ; |
---|
2371 | wire [M -1:0] metric_A_48; |
---|
2372 | wire [M -1:0] metric_B_48; |
---|
2373 | wire [M -1:0] metric_A_49; |
---|
2374 | wire [M -1:0] metric_B_49; |
---|
2375 | wire [M -1:0] metric_A_50; |
---|
2376 | wire [M -1:0] metric_B_50; |
---|
2377 | wire [M -1:0] metric_A_51; |
---|
2378 | wire [M -1:0] metric_B_51; |
---|
2379 | wire [M -1:0] metric_A_52; |
---|
2380 | wire [M -1:0] metric_B_52; |
---|
2381 | wire [M -1:0] metric_A_53; |
---|
2382 | wire [M -1:0] metric_B_53; |
---|
2383 | wire [M -1:0] metric_A_54; |
---|
2384 | wire [M -1:0] metric_B_54; |
---|
2385 | wire [M -1:0] metric_A_55; |
---|
2386 | wire [M -1:0] metric_B_55; |
---|
2387 | wire [M -1:0] metric_A_56; |
---|
2388 | wire [M -1:0] metric_B_56; |
---|
2389 | wire [M -1:0] metric_A_57; |
---|
2390 | wire [M -1:0] metric_B_57; |
---|
2391 | wire [M -1:0] metric_A_58 ; |
---|
2392 | wire [M -1:0] metric_B_58 ; |
---|
2393 | wire [M -1:0] metric_A_59 ; |
---|
2394 | wire [M -1:0] metric_B_59 ; |
---|
2395 | wire [M -1:0] metric_A_60 ; |
---|
2396 | wire [M -1:0] metric_B_60 ; |
---|
2397 | wire [M -1:0] metric_A_61 ; |
---|
2398 | wire [M -1:0] metric_B_61 ; |
---|
2399 | wire [M -1:0] metric_A_62 ; |
---|
2400 | wire [M -1:0] metric_B_62 ; |
---|
2401 | wire [M -1:0] metric_A_63 ; |
---|
2402 | wire [M -1:0] metric_B_63 ; |
---|
2403 | |
---|
2404 | // 64 state tran |
---|
2405 | reg [0:0] tran_state_0 [TR -1:0] ; |
---|
2406 | reg [0:0] tran_state_1 [TR -1:0] ; |
---|
2407 | reg [0:0] tran_state_2 [TR -1:0] ; |
---|
2408 | reg [0:0] tran_state_3 [TR -1:0] ; |
---|
2409 | reg [0:0] tran_state_4 [TR -1:0] ; |
---|
2410 | reg [0:0] tran_state_5 [TR -1:0] ; |
---|
2411 | reg [0:0] tran_state_6 [TR -1:0] ; |
---|
2412 | reg [0:0] tran_state_7 [TR -1:0] ; |
---|
2413 | reg [0:0] tran_state_8 [TR -1:0] ; |
---|
2414 | reg [0:0] tran_state_9 [TR -1:0] ; |
---|
2415 | reg [0:0] tran_state_10 [TR -1:0] ; |
---|
2416 | reg [0:0] tran_state_11 [TR -1:0] ; |
---|
2417 | reg [0:0] tran_state_12 [TR -1:0] ; |
---|
2418 | reg [0:0] tran_state_13 [TR -1:0] ; |
---|
2419 | reg [0:0] tran_state_14 [TR -1:0] ; |
---|
2420 | reg [0:0] tran_state_15 [TR -1:0] ; |
---|
2421 | reg [0:0] tran_state_16 [TR -1:0] ; |
---|
2422 | reg [0:0] tran_state_17 [TR -1:0] ; |
---|
2423 | reg [0:0] tran_state_18 [TR -1:0] ; |
---|
2424 | reg [0:0] tran_state_19 [TR -1:0] ; |
---|
2425 | reg [0:0] tran_state_20 [TR -1:0] ; |
---|
2426 | reg [0:0] tran_state_21 [TR -1:0] ; |
---|
2427 | reg [0:0] tran_state_22 [TR -1:0] ; |
---|
2428 | reg [0:0] tran_state_23 [TR -1:0] ; |
---|
2429 | reg [0:0] tran_state_24 [TR -1:0] ; |
---|
2430 | reg [0:0] tran_state_25 [TR -1:0] ; |
---|
2431 | reg [0:0] tran_state_26 [TR -1:0] ; |
---|
2432 | reg [0:0] tran_state_27 [TR -1:0] ; |
---|
2433 | reg [0:0] tran_state_28 [TR -1:0] ; |
---|
2434 | reg [0:0] tran_state_29 [TR -1:0] ; |
---|
2435 | reg [0:0] tran_state_30 [TR -1:0] ; |
---|
2436 | reg [0:0] tran_state_31 [TR -1:0] ; |
---|
2437 | reg [0:0] tran_state_32 [TR -1:0] ; |
---|
2438 | reg [0:0] tran_state_33 [TR -1:0] ; |
---|
2439 | reg [0:0] tran_state_34 [TR -1:0] ; |
---|
2440 | reg [0:0] tran_state_35 [TR -1:0] ; |
---|
2441 | reg [0:0] tran_state_36 [TR -1:0] ; |
---|
2442 | reg [0:0] tran_state_37 [TR -1:0] ; |
---|
2443 | reg [0:0] tran_state_38 [TR -1:0] ; |
---|
2444 | reg [0:0] tran_state_39 [TR -1:0] ; |
---|
2445 | reg [0:0] tran_state_40 [TR -1:0] ; |
---|
2446 | reg [0:0] tran_state_41 [TR -1:0] ; |
---|
2447 | reg [0:0] tran_state_42 [TR -1:0] ; |
---|
2448 | reg [0:0] tran_state_43 [TR -1:0] ; |
---|
2449 | reg [0:0] tran_state_44 [TR -1:0] ; |
---|
2450 | reg [0:0] tran_state_45 [TR -1:0] ; |
---|
2451 | reg [0:0] tran_state_46 [TR -1:0] ; |
---|
2452 | reg [0:0] tran_state_47 [TR -1:0] ; |
---|
2453 | reg [0:0] tran_state_48 [TR -1:0] ; |
---|
2454 | reg [0:0] tran_state_49 [TR -1:0] ; |
---|
2455 | reg [0:0] tran_state_50 [TR -1:0] ; |
---|
2456 | reg [0:0] tran_state_51 [TR -1:0] ; |
---|
2457 | reg [0:0] tran_state_52 [TR -1:0] ; |
---|
2458 | reg [0:0] tran_state_53 [TR -1:0] ; |
---|
2459 | reg [0:0] tran_state_54 [TR -1:0] ; |
---|
2460 | reg [0:0] tran_state_55 [TR -1:0] ; |
---|
2461 | reg [0:0] tran_state_56 [TR -1:0] ; |
---|
2462 | reg [0:0] tran_state_57 [TR -1:0] ; |
---|
2463 | reg [0:0] tran_state_58 [TR -1:0] ; |
---|
2464 | reg [0:0] tran_state_59 [TR -1:0] ; |
---|
2465 | reg [0:0] tran_state_60 [TR -1:0] ; |
---|
2466 | reg [0:0] tran_state_61 [TR -1:0] ; |
---|
2467 | reg [0:0] tran_state_62 [TR -1:0] ; |
---|
2468 | reg [0:0] tran_state_63 [TR -1:0] ; |
---|
2469 | |
---|
2470 | reg [TRW -1:0] wptr ; |
---|
2471 | reg [TRW -1:0] last_wptr ; |
---|
2472 | |
---|
2473 | wire [M -1:0] diff_0 ; |
---|
2474 | wire [M -1:0] diff_1 ; |
---|
2475 | wire [M -1:0] diff_2 ; |
---|
2476 | wire [M -1:0] diff_3 ; |
---|
2477 | wire [M -1:0] diff_4 ; |
---|
2478 | wire [M -1:0] diff_5 ; |
---|
2479 | wire [M -1:0] diff_6 ; |
---|
2480 | wire [M -1:0] diff_7 ; |
---|
2481 | wire [M -1:0] diff_8 ; |
---|
2482 | wire [M -1:0] diff_9 ; |
---|
2483 | wire [M -1:0] diff_10; |
---|
2484 | wire [M -1:0] diff_11; |
---|
2485 | wire [M -1:0] diff_12; |
---|
2486 | wire [M -1:0] diff_13; |
---|
2487 | wire [M -1:0] diff_14; |
---|
2488 | wire [M -1:0] diff_15; |
---|
2489 | wire [M -1:0] diff_16; |
---|
2490 | wire [M -1:0] diff_17; |
---|
2491 | wire [M -1:0] diff_18; |
---|
2492 | wire [M -1:0] diff_19; |
---|
2493 | wire [M -1:0] diff_20; |
---|
2494 | wire [M -1:0] diff_21; |
---|
2495 | wire [M -1:0] diff_22; |
---|
2496 | wire [M -1:0] diff_23; |
---|
2497 | wire [M -1:0] diff_24; |
---|
2498 | wire [M -1:0] diff_25; |
---|
2499 | wire [M -1:0] diff_26; |
---|
2500 | wire [M -1:0] diff_27; |
---|
2501 | wire [M -1:0] diff_28; |
---|
2502 | wire [M -1:0] diff_29; |
---|
2503 | wire [M -1:0] diff_30; |
---|
2504 | wire [M -1:0] diff_31; |
---|
2505 | wire [M -1:0] diff_32; |
---|
2506 | wire [M -1:0] diff_33; |
---|
2507 | wire [M -1:0] diff_34; |
---|
2508 | wire [M -1:0] diff_35; |
---|
2509 | wire [M -1:0] diff_36; |
---|
2510 | wire [M -1:0] diff_37; |
---|
2511 | wire [M -1:0] diff_38; |
---|
2512 | wire [M -1:0] diff_39; |
---|
2513 | wire [M -1:0] diff_40; |
---|
2514 | wire [M -1:0] diff_41; |
---|
2515 | wire [M -1:0] diff_42; |
---|
2516 | wire [M -1:0] diff_43; |
---|
2517 | wire [M -1:0] diff_44; |
---|
2518 | wire [M -1:0] diff_45; |
---|
2519 | wire [M -1:0] diff_46; |
---|
2520 | wire [M -1:0] diff_47; |
---|
2521 | wire [M -1:0] diff_48; |
---|
2522 | wire [M -1:0] diff_49; |
---|
2523 | wire [M -1:0] diff_50; |
---|
2524 | wire [M -1:0] diff_51; |
---|
2525 | wire [M -1:0] diff_52; |
---|
2526 | wire [M -1:0] diff_53; |
---|
2527 | wire [M -1:0] diff_54; |
---|
2528 | wire [M -1:0] diff_55; |
---|
2529 | wire [M -1:0] diff_56; |
---|
2530 | wire [M -1:0] diff_57; |
---|
2531 | wire [M -1:0] diff_58; |
---|
2532 | wire [M -1:0] diff_59; |
---|
2533 | wire [M -1:0] diff_60; |
---|
2534 | wire [M -1:0] diff_61; |
---|
2535 | wire [M -1:0] diff_62; |
---|
2536 | wire [M -1:0] diff_63; |
---|
2537 | |
---|
2538 | reg nd ; |
---|
2539 | reg [LW -1:0] cnt ; |
---|
2540 | reg trace ; |
---|
2541 | reg trace_en ; |
---|
2542 | wire trace_done ; |
---|
2543 | reg trace_done_s0 ; |
---|
2544 | wire trace_done_pos ; |
---|
2545 | reg [TRW -1:0] trace_cnt ; |
---|
2546 | reg [L-1:0] res ; |
---|
2547 | wire [L-1:0] res_shift ; |
---|
2548 | wire [K-2: 0] init_state_i ; |
---|
2549 | reg [K-2: 0] trace_state ; |
---|
2550 | |
---|
2551 | wire [K-2: 0] cur_state0 ; |
---|
2552 | wire [K-2: 0] cur_state1 ; |
---|
2553 | wire [K-2: 0] next_state ; |
---|
2554 | reg [TRW -1:0] trace_start_wptr ; |
---|
2555 | wire [TRW -1:0] trace_start_pos ; |
---|
2556 | wire [TRW -1:0] trace_start_pos0 ; |
---|
2557 | wire [TRW -1:0] trace_start_pos1 ; |
---|
2558 | reg last_trace ; |
---|
2559 | reg last_trace_s0 ; |
---|
2560 | wire trace2 ; |
---|
2561 | reg trace2_s1 ; |
---|
2562 | reg trace2_s2 ; |
---|
2563 | reg trace_pos ; |
---|
2564 | wire trace_pos_i ; |
---|
2565 | reg [LW -1:0] last_trace_num ; |
---|
2566 | reg flush_en ; |
---|
2567 | wire flush ; |
---|
2568 | reg done_i ; |
---|
2569 | |
---|
2570 | wire [K-2: 0] state_0 ; |
---|
2571 | wire [K-2: 0] state_1 ; |
---|
2572 | wire [K-2: 0] state_2 ; |
---|
2573 | wire [K-2: 0] state_3 ; |
---|
2574 | wire [K-2: 0] state_4 ; |
---|
2575 | wire [K-2: 0] state_5 ; |
---|
2576 | wire [K-2: 0] state_6 ; |
---|
2577 | wire [K-2: 0] state_7 ; |
---|
2578 | wire [K-2: 0] state_8 ; |
---|
2579 | wire [K-2: 0] state_9 ; |
---|
2580 | wire [K-2: 0] state_10 ; |
---|
2581 | wire [K-2: 0] state_11 ; |
---|
2582 | wire [K-2: 0] state_12 ; |
---|
2583 | wire [K-2: 0] state_13 ; |
---|
2584 | wire [K-2: 0] state_14 ; |
---|
2585 | wire [K-2: 0] state_15 ; |
---|
2586 | |
---|
2587 | wire [K-2: 0] state_s1_0 ; |
---|
2588 | wire [K-2: 0] state_s1_1 ; |
---|
2589 | wire [K-2: 0] state_s1_2 ; |
---|
2590 | wire [K-2: 0] state_s1_3 ; |
---|
2591 | |
---|
2592 | wire [K-2: 0] state_s2_0 ; |
---|
2593 | |
---|
2594 | wire [M-1: 0] max_0 ; |
---|
2595 | wire [M-1: 0] max_1 ; |
---|
2596 | wire [M-1: 0] max_2 ; |
---|
2597 | wire [M-1: 0] max_3 ; |
---|
2598 | wire [M-1: 0] max_4 ; |
---|
2599 | wire [M-1: 0] max_5 ; |
---|
2600 | wire [M-1: 0] max_6 ; |
---|
2601 | wire [M-1: 0] max_7 ; |
---|
2602 | wire [M-1: 0] max_8 ; |
---|
2603 | wire [M-1: 0] max_9 ; |
---|
2604 | wire [M-1: 0] max_10 ; |
---|
2605 | wire [M-1: 0] max_11 ; |
---|
2606 | wire [M-1: 0] max_12 ; |
---|
2607 | wire [M-1: 0] max_13 ; |
---|
2608 | wire [M-1: 0] max_14 ; |
---|
2609 | wire [M-1: 0] max_15 ; |
---|
2610 | |
---|
2611 | wire [M-1: 0] max_s1_0 ; |
---|
2612 | wire [M-1: 0] max_s1_1 ; |
---|
2613 | wire [M-1: 0] max_s1_2 ; |
---|
2614 | wire [M-1: 0] max_s1_3 ; |
---|
2615 | |
---|
2616 | //reg [M-1: 0] max_s1_0_s0 ; |
---|
2617 | //reg [M-1: 0] max_s1_1_s0 ; |
---|
2618 | //reg [M-1: 0] max_s1_2_s0 ; |
---|
2619 | //reg [M-1: 0] max_s1_3_s0 ; |
---|
2620 | |
---|
2621 | //wire [M-1: 0] max_s2_0 ; |
---|
2622 | |
---|
2623 | wire [N -1:0] tran_all_0 ; |
---|
2624 | wire [N -1:0] tran_all_1 ; |
---|
2625 | |
---|
2626 | reg [6:0] flush_cnt ; |
---|
2627 | wire [LW -1:0] rem_i ; |
---|
2628 | reg [LW -1:0] last_cnt ; |
---|
2629 | wire [LW -1:0] last_cnt_next ; |
---|
2630 | reg last_trace_d0 ; |
---|
2631 | reg last_trace_d1 ; |
---|
2632 | reg last_trace_d2 ; |
---|
2633 | reg last_trace_d3 ; |
---|
2634 | reg last_trace_d4 ; |
---|
2635 | reg last_trace_d5 ; |
---|
2636 | reg one_more_out ; |
---|
2637 | reg in_dec ; |
---|
2638 | wire dv_in_gate ; |
---|
2639 | reg trace_pos_s0 ; |
---|
2640 | |
---|
2641 | //====================================== |
---|
2642 | // Main body of code |
---|
2643 | //====================================== |
---|
2644 | assign dv_out = trace_done_pos | one_more_out ; |
---|
2645 | assign res_shift = res << last_trace_num ; |
---|
2646 | assign dout = res_shift [L -1:C] ; |
---|
2647 | assign remain = last_trace ? rem_i : 0 ; |
---|
2648 | assign done = dv_out & done_i ; |
---|
2649 | assign rem_i = ~last_cnt_next[LW-1] ? 0 : last_cnt ; |
---|
2650 | |
---|
2651 | //assign dv_in_gate = dv_in & in_dec ; |
---|
2652 | assign dv_in_gate = dv_in & in_dec & (~packet_end) ; |
---|
2653 | |
---|
2654 | always @ (posedge clk or negedge nrst) |
---|
2655 | if (~nrst) |
---|
2656 | in_dec <= 1'b0 ; |
---|
2657 | else if (packet_start) |
---|
2658 | in_dec <= 1'b1 ; |
---|
2659 | else if (packet_end) |
---|
2660 | in_dec <= 1'b0 ; |
---|
2661 | |
---|
2662 | |
---|
2663 | //{coe_0 coe_1}, generated from C model gen_table |
---|
2664 | //0 0; |
---|
2665 | //0 1; |
---|
2666 | //1 0; |
---|
2667 | //1 1; |
---|
2668 | //1 0; |
---|
2669 | //1 1; |
---|
2670 | //0 0; |
---|
2671 | //0 1; |
---|
2672 | |
---|
2673 | assign branch_00 = {llr1[SW -1], llr1} + {llr0[SW -1], llr0} ; //LLR(bit1) + LLR(bit0) |
---|
2674 | assign branch_01 = {llr1[SW -1], llr1} ; //LLR(bit1) |
---|
2675 | assign branch_10 = {llr0[SW -1], llr0} ; //LLR(bit0) |
---|
2676 | assign branch_11 = 0 ; //0 |
---|
2677 | |
---|
2678 | assign branch_A_0 = branch_00 ; |
---|
2679 | assign branch_B_0 = branch_11 ; |
---|
2680 | assign branch_A_1 = branch_10 ; |
---|
2681 | assign branch_B_1 = branch_01 ; |
---|
2682 | assign branch_A_2 = branch_00 ; |
---|
2683 | assign branch_B_2 = branch_11 ; |
---|
2684 | assign branch_A_3 = branch_10 ; |
---|
2685 | assign branch_B_3 = branch_01 ; |
---|
2686 | assign branch_A_4 = branch_11 ; |
---|
2687 | assign branch_B_4 = branch_00 ; |
---|
2688 | assign branch_A_5 = branch_01 ; |
---|
2689 | assign branch_B_5 = branch_10 ; |
---|
2690 | assign branch_A_6 = branch_11 ; |
---|
2691 | assign branch_B_6 = branch_00 ; |
---|
2692 | assign branch_A_7 = branch_01 ; |
---|
2693 | assign branch_B_7 = branch_10 ; |
---|
2694 | assign branch_A_8 = branch_11 ; |
---|
2695 | assign branch_B_8 = branch_00 ; |
---|
2696 | assign branch_A_9 = branch_01 ; |
---|
2697 | assign branch_B_9 = branch_10 ; |
---|
2698 | assign branch_A_10 = branch_11 ; |
---|
2699 | assign branch_B_10 = branch_00 ; |
---|
2700 | assign branch_A_11 = branch_01 ; |
---|
2701 | assign branch_B_11 = branch_10 ; |
---|
2702 | assign branch_A_12 = branch_00 ; |
---|
2703 | assign branch_B_12 = branch_11 ; |
---|
2704 | assign branch_A_13 = branch_10 ; |
---|
2705 | assign branch_B_13 = branch_01 ; |
---|
2706 | assign branch_A_14 = branch_00 ; |
---|
2707 | assign branch_B_14 = branch_11 ; |
---|
2708 | assign branch_A_15 = branch_10 ; |
---|
2709 | assign branch_B_15 = branch_01 ; |
---|
2710 | assign branch_A_16 = branch_01 ; |
---|
2711 | assign branch_B_16 = branch_10 ; |
---|
2712 | assign branch_A_17 = branch_11 ; |
---|
2713 | assign branch_B_17 = branch_00 ; |
---|
2714 | assign branch_A_18 = branch_01 ; |
---|
2715 | assign branch_B_18 = branch_10 ; |
---|
2716 | assign branch_A_19 = branch_11 ; |
---|
2717 | assign branch_B_19 = branch_00 ; |
---|
2718 | assign branch_A_20 = branch_10 ; |
---|
2719 | assign branch_B_20 = branch_01 ; |
---|
2720 | assign branch_A_21 = branch_00 ; |
---|
2721 | assign branch_B_21 = branch_11 ; |
---|
2722 | assign branch_A_22 = branch_10 ; |
---|
2723 | assign branch_B_22 = branch_01 ; |
---|
2724 | assign branch_A_23 = branch_00 ; |
---|
2725 | assign branch_B_23 = branch_11 ; |
---|
2726 | assign branch_A_24 = branch_10 ; |
---|
2727 | assign branch_B_24 = branch_01 ; |
---|
2728 | assign branch_A_25 = branch_00 ; |
---|
2729 | assign branch_B_25 = branch_11 ; |
---|
2730 | assign branch_A_26 = branch_10 ; |
---|
2731 | assign branch_B_26 = branch_01 ; |
---|
2732 | assign branch_A_27 = branch_00 ; |
---|
2733 | assign branch_B_27 = branch_11 ; |
---|
2734 | assign branch_A_28 = branch_01 ; |
---|
2735 | assign branch_B_28 = branch_10 ; |
---|
2736 | assign branch_A_29 = branch_11 ; |
---|
2737 | assign branch_B_29 = branch_00 ; |
---|
2738 | assign branch_A_30 = branch_01 ; |
---|
2739 | assign branch_B_30 = branch_10 ; |
---|
2740 | assign branch_A_31 = branch_11 ; |
---|
2741 | assign branch_B_31 = branch_00 ; |
---|
2742 | |
---|
2743 | assign branch_A_32 = branch_B_0 ; |
---|
2744 | assign branch_B_32 = branch_A_0 ; |
---|
2745 | assign branch_A_33 = branch_B_1 ; |
---|
2746 | assign branch_B_33 = branch_A_1 ; |
---|
2747 | assign branch_A_34 = branch_B_2 ; |
---|
2748 | assign branch_B_34 = branch_A_2 ; |
---|
2749 | assign branch_A_35 = branch_B_3 ; |
---|
2750 | assign branch_B_35 = branch_A_3 ; |
---|
2751 | assign branch_A_36 = branch_B_4 ; |
---|
2752 | assign branch_B_36 = branch_A_4 ; |
---|
2753 | assign branch_A_37 = branch_B_5 ; |
---|
2754 | assign branch_B_37 = branch_A_5 ; |
---|
2755 | assign branch_A_38 = branch_B_6 ; |
---|
2756 | assign branch_B_38 = branch_A_6 ; |
---|
2757 | assign branch_A_39 = branch_B_7 ; |
---|
2758 | assign branch_B_39 = branch_A_7 ; |
---|
2759 | assign branch_A_40 = branch_B_8 ; |
---|
2760 | assign branch_B_40 = branch_A_8 ; |
---|
2761 | assign branch_A_41 = branch_B_9 ; |
---|
2762 | assign branch_B_41 = branch_A_9 ; |
---|
2763 | assign branch_A_42 = branch_B_10 ; |
---|
2764 | assign branch_B_42 = branch_A_10 ; |
---|
2765 | assign branch_A_43 = branch_B_11 ; |
---|
2766 | assign branch_B_43 = branch_A_11 ; |
---|
2767 | assign branch_A_44 = branch_B_12 ; |
---|
2768 | assign branch_B_44 = branch_A_12 ; |
---|
2769 | assign branch_A_45 = branch_B_13 ; |
---|
2770 | assign branch_B_45 = branch_A_13 ; |
---|
2771 | assign branch_A_46 = branch_B_14 ; |
---|
2772 | assign branch_B_46 = branch_A_14 ; |
---|
2773 | assign branch_A_47 = branch_B_15 ; |
---|
2774 | assign branch_B_47 = branch_A_15 ; |
---|
2775 | assign branch_A_48 = branch_B_16 ; |
---|
2776 | assign branch_B_48 = branch_A_16 ; |
---|
2777 | assign branch_A_49 = branch_B_17 ; |
---|
2778 | assign branch_B_49 = branch_A_17 ; |
---|
2779 | assign branch_A_50 = branch_B_18 ; |
---|
2780 | assign branch_B_50 = branch_A_18 ; |
---|
2781 | assign branch_A_51 = branch_B_19 ; |
---|
2782 | assign branch_B_51 = branch_A_19 ; |
---|
2783 | assign branch_A_52 = branch_B_20 ; |
---|
2784 | assign branch_B_52 = branch_A_20 ; |
---|
2785 | assign branch_A_53 = branch_B_21 ; |
---|
2786 | assign branch_B_53 = branch_A_21 ; |
---|
2787 | assign branch_A_54 = branch_B_22 ; |
---|
2788 | assign branch_B_54 = branch_A_22 ; |
---|
2789 | assign branch_A_55 = branch_B_23 ; |
---|
2790 | assign branch_B_55 = branch_A_23 ; |
---|
2791 | assign branch_A_56 = branch_B_24 ; |
---|
2792 | assign branch_B_56 = branch_A_24 ; |
---|
2793 | assign branch_A_57 = branch_B_25 ; |
---|
2794 | assign branch_B_57 = branch_A_25 ; |
---|
2795 | assign branch_A_58 = branch_B_26 ; |
---|
2796 | assign branch_B_58 = branch_A_26 ; |
---|
2797 | assign branch_A_59 = branch_B_27 ; |
---|
2798 | assign branch_B_59 = branch_A_27 ; |
---|
2799 | assign branch_A_60 = branch_B_28 ; |
---|
2800 | assign branch_B_60 = branch_A_28 ; |
---|
2801 | assign branch_A_61 = branch_B_29 ; |
---|
2802 | assign branch_B_61 = branch_A_29 ; |
---|
2803 | assign branch_A_62 = branch_B_30 ; |
---|
2804 | assign branch_B_62 = branch_A_30 ; |
---|
2805 | assign branch_A_63 = branch_B_31 ; |
---|
2806 | assign branch_B_63 = branch_A_31 ; |
---|
2807 | |
---|
2808 | assign metric_A_0 = metric_0 + {{(M -SW -1){branch_A_0[SW]}}, branch_A_0} ; |
---|
2809 | assign metric_B_0 = metric_1 + {{(M -SW -1){branch_B_0[SW]}}, branch_B_0} ; |
---|
2810 | assign metric_A_1 = metric_2 + {{(M -SW -1){branch_A_1[SW]}}, branch_A_1} ; |
---|
2811 | assign metric_B_1 = metric_3 + {{(M -SW -1){branch_B_1[SW]}}, branch_B_1} ; |
---|
2812 | assign metric_A_2 = metric_4 + {{(M -SW -1){branch_A_2[SW]}}, branch_A_2} ; |
---|
2813 | assign metric_B_2 = metric_5 + {{(M -SW -1){branch_B_2[SW]}}, branch_B_2} ; |
---|
2814 | assign metric_A_3 = metric_6 + {{(M -SW -1){branch_A_3[SW]}}, branch_A_3} ; |
---|
2815 | assign metric_B_3 = metric_7 + {{(M -SW -1){branch_B_3[SW]}}, branch_B_3} ; |
---|
2816 | assign metric_A_4 = metric_8 + {{(M -SW -1){branch_A_4[SW]}}, branch_A_4} ; |
---|
2817 | assign metric_B_4 = metric_9 + {{(M -SW -1){branch_B_4[SW]}}, branch_B_4} ; |
---|
2818 | assign metric_A_5 = metric_10 + {{(M -SW -1){branch_A_5[SW]}}, branch_A_5} ; |
---|
2819 | assign metric_B_5 = metric_11 + {{(M -SW -1){branch_B_5[SW]}}, branch_B_5} ; |
---|
2820 | assign metric_A_6 = metric_12 + {{(M -SW -1){branch_A_6[SW]}}, branch_A_6} ; |
---|
2821 | assign metric_B_6 = metric_13 + {{(M -SW -1){branch_B_6[SW]}}, branch_B_6} ; |
---|
2822 | assign metric_A_7 = metric_14 + {{(M -SW -1){branch_A_7[SW]}}, branch_A_7} ; |
---|
2823 | assign metric_B_7 = metric_15 + {{(M -SW -1){branch_B_7[SW]}}, branch_B_7} ; |
---|
2824 | assign metric_A_8 = metric_16 + {{(M -SW -1){branch_A_8[SW]}}, branch_A_8} ; |
---|
2825 | assign metric_B_8 = metric_17 + {{(M -SW -1){branch_B_8[SW]}}, branch_B_8} ; |
---|
2826 | assign metric_A_9 = metric_18 + {{(M -SW -1){branch_A_9[SW]}}, branch_A_9} ; |
---|
2827 | assign metric_B_9 = metric_19 + {{(M -SW -1){branch_B_9[SW]}}, branch_B_9} ; |
---|
2828 | assign metric_A_10 = metric_20 + {{(M -SW -1){branch_A_10[SW]}}, branch_A_10} ; |
---|
2829 | assign metric_B_10 = metric_21 + {{(M -SW -1){branch_B_10[SW]}}, branch_B_10} ; |
---|
2830 | assign metric_A_11 = metric_22 + {{(M -SW -1){branch_A_11[SW]}}, branch_A_11} ; |
---|
2831 | assign metric_B_11 = metric_23 + {{(M -SW -1){branch_B_11[SW]}}, branch_B_11} ; |
---|
2832 | assign metric_A_12 = metric_24 + {{(M -SW -1){branch_A_12[SW]}}, branch_A_12} ; |
---|
2833 | assign metric_B_12 = metric_25 + {{(M -SW -1){branch_B_12[SW]}}, branch_B_12} ; |
---|
2834 | assign metric_A_13 = metric_26 + {{(M -SW -1){branch_A_13[SW]}}, branch_A_13} ; |
---|
2835 | assign metric_B_13 = metric_27 + {{(M -SW -1){branch_B_13[SW]}}, branch_B_13} ; |
---|
2836 | assign metric_A_14 = metric_28 + {{(M -SW -1){branch_A_14[SW]}}, branch_A_14} ; |
---|
2837 | assign metric_B_14 = metric_29 + {{(M -SW -1){branch_B_14[SW]}}, branch_B_14} ; |
---|
2838 | assign metric_A_15 = metric_30 + {{(M -SW -1){branch_A_15[SW]}}, branch_A_15} ; |
---|
2839 | assign metric_B_15 = metric_31 + {{(M -SW -1){branch_B_15[SW]}}, branch_B_15} ; |
---|
2840 | assign metric_A_16 = metric_32 + {{(M -SW -1){branch_A_16[SW]}}, branch_A_16} ; |
---|
2841 | assign metric_B_16 = metric_33 + {{(M -SW -1){branch_B_16[SW]}}, branch_B_16} ; |
---|
2842 | assign metric_A_17 = metric_34 + {{(M -SW -1){branch_A_17[SW]}}, branch_A_17} ; |
---|
2843 | assign metric_B_17 = metric_35 + {{(M -SW -1){branch_B_17[SW]}}, branch_B_17} ; |
---|
2844 | assign metric_A_18 = metric_36 + {{(M -SW -1){branch_A_18[SW]}}, branch_A_18} ; |
---|
2845 | assign metric_B_18 = metric_37 + {{(M -SW -1){branch_B_18[SW]}}, branch_B_18} ; |
---|
2846 | assign metric_A_19 = metric_38 + {{(M -SW -1){branch_A_19[SW]}}, branch_A_19} ; |
---|
2847 | assign metric_B_19 = metric_39 + {{(M -SW -1){branch_B_19[SW]}}, branch_B_19} ; |
---|
2848 | assign metric_A_20 = metric_40 + {{(M -SW -1){branch_A_20[SW]}}, branch_A_20} ; |
---|
2849 | assign metric_B_20 = metric_41 + {{(M -SW -1){branch_B_20[SW]}}, branch_B_20} ; |
---|
2850 | assign metric_A_21 = metric_42 + {{(M -SW -1){branch_A_21[SW]}}, branch_A_21} ; |
---|
2851 | assign metric_B_21 = metric_43 + {{(M -SW -1){branch_B_21[SW]}}, branch_B_21} ; |
---|
2852 | assign metric_A_22 = metric_44 + {{(M -SW -1){branch_A_22[SW]}}, branch_A_22} ; |
---|
2853 | assign metric_B_22 = metric_45 + {{(M -SW -1){branch_B_22[SW]}}, branch_B_22} ; |
---|
2854 | assign metric_A_23 = metric_46 + {{(M -SW -1){branch_A_23[SW]}}, branch_A_23} ; |
---|
2855 | assign metric_B_23 = metric_47 + {{(M -SW -1){branch_B_23[SW]}}, branch_B_23} ; |
---|
2856 | assign metric_A_24 = metric_48 + {{(M -SW -1){branch_A_24[SW]}}, branch_A_24} ; |
---|
2857 | assign metric_B_24 = metric_49 + {{(M -SW -1){branch_B_24[SW]}}, branch_B_24} ; |
---|
2858 | assign metric_A_25 = metric_50 + {{(M -SW -1){branch_A_25[SW]}}, branch_A_25} ; |
---|
2859 | assign metric_B_25 = metric_51 + {{(M -SW -1){branch_B_25[SW]}}, branch_B_25} ; |
---|
2860 | assign metric_A_26 = metric_52 + {{(M -SW -1){branch_A_26[SW]}}, branch_A_26} ; |
---|
2861 | assign metric_B_26 = metric_53 + {{(M -SW -1){branch_B_26[SW]}}, branch_B_26} ; |
---|
2862 | assign metric_A_27 = metric_54 + {{(M -SW -1){branch_A_27[SW]}}, branch_A_27} ; |
---|
2863 | assign metric_B_27 = metric_55 + {{(M -SW -1){branch_B_27[SW]}}, branch_B_27} ; |
---|
2864 | assign metric_A_28 = metric_56 + {{(M -SW -1){branch_A_28[SW]}}, branch_A_28} ; |
---|
2865 | assign metric_B_28 = metric_57 + {{(M -SW -1){branch_B_28[SW]}}, branch_B_28} ; |
---|
2866 | assign metric_A_29 = metric_58 + {{(M -SW -1){branch_A_29[SW]}}, branch_A_29} ; |
---|
2867 | assign metric_B_29 = metric_59 + {{(M -SW -1){branch_B_29[SW]}}, branch_B_29} ; |
---|
2868 | assign metric_A_30 = metric_60 + {{(M -SW -1){branch_A_30[SW]}}, branch_A_30} ; |
---|
2869 | assign metric_B_30 = metric_61 + {{(M -SW -1){branch_B_30[SW]}}, branch_B_30} ; |
---|
2870 | assign metric_A_31 = metric_62 + {{(M -SW -1){branch_A_31[SW]}}, branch_A_31} ; |
---|
2871 | assign metric_B_31 = metric_63 + {{(M -SW -1){branch_B_31[SW]}}, branch_B_31} ; |
---|
2872 | assign metric_A_32 = metric_0 + {{(M -SW -1){branch_A_32[SW]}}, branch_A_32} ; |
---|
2873 | assign metric_B_32 = metric_1 + {{(M -SW -1){branch_B_32[SW]}}, branch_B_32} ; |
---|
2874 | assign metric_A_33 = metric_2 + {{(M -SW -1){branch_A_33[SW]}}, branch_A_33} ; |
---|
2875 | assign metric_B_33 = metric_3 + {{(M -SW -1){branch_B_33[SW]}}, branch_B_33} ; |
---|
2876 | assign metric_A_34 = metric_4 + {{(M -SW -1){branch_A_34[SW]}}, branch_A_34} ; |
---|
2877 | assign metric_B_34 = metric_5 + {{(M -SW -1){branch_B_34[SW]}}, branch_B_34} ; |
---|
2878 | assign metric_A_35 = metric_6 + {{(M -SW -1){branch_A_35[SW]}}, branch_A_35} ; |
---|
2879 | assign metric_B_35 = metric_7 + {{(M -SW -1){branch_B_35[SW]}}, branch_B_35} ; |
---|
2880 | assign metric_A_36 = metric_8 + {{(M -SW -1){branch_A_36[SW]}}, branch_A_36} ; |
---|
2881 | assign metric_B_36 = metric_9 + {{(M -SW -1){branch_B_36[SW]}}, branch_B_36} ; |
---|
2882 | assign metric_A_37 = metric_10 + {{(M -SW -1){branch_A_37[SW]}}, branch_A_37} ; |
---|
2883 | assign metric_B_37 = metric_11 + {{(M -SW -1){branch_B_37[SW]}}, branch_B_37} ; |
---|
2884 | assign metric_A_38 = metric_12 + {{(M -SW -1){branch_A_38[SW]}}, branch_A_38} ; |
---|
2885 | assign metric_B_38 = metric_13 + {{(M -SW -1){branch_B_38[SW]}}, branch_B_38} ; |
---|
2886 | assign metric_A_39 = metric_14 + {{(M -SW -1){branch_A_39[SW]}}, branch_A_39} ; |
---|
2887 | assign metric_B_39 = metric_15 + {{(M -SW -1){branch_B_39[SW]}}, branch_B_39} ; |
---|
2888 | assign metric_A_40 = metric_16 + {{(M -SW -1){branch_A_40[SW]}}, branch_A_40} ; |
---|
2889 | assign metric_B_40 = metric_17 + {{(M -SW -1){branch_B_40[SW]}}, branch_B_40} ; |
---|
2890 | assign metric_A_41 = metric_18 + {{(M -SW -1){branch_A_41[SW]}}, branch_A_41} ; |
---|
2891 | assign metric_B_41 = metric_19 + {{(M -SW -1){branch_B_41[SW]}}, branch_B_41} ; |
---|
2892 | assign metric_A_42 = metric_20 + {{(M -SW -1){branch_A_42[SW]}}, branch_A_42} ; |
---|
2893 | assign metric_B_42 = metric_21 + {{(M -SW -1){branch_B_42[SW]}}, branch_B_42} ; |
---|
2894 | assign metric_A_43 = metric_22 + {{(M -SW -1){branch_A_43[SW]}}, branch_A_43} ; |
---|
2895 | assign metric_B_43 = metric_23 + {{(M -SW -1){branch_B_43[SW]}}, branch_B_43} ; |
---|
2896 | assign metric_A_44 = metric_24 + {{(M -SW -1){branch_A_44[SW]}}, branch_A_44} ; |
---|
2897 | assign metric_B_44 = metric_25 + {{(M -SW -1){branch_B_44[SW]}}, branch_B_44} ; |
---|
2898 | assign metric_A_45 = metric_26 + {{(M -SW -1){branch_A_45[SW]}}, branch_A_45} ; |
---|
2899 | assign metric_B_45 = metric_27 + {{(M -SW -1){branch_B_45[SW]}}, branch_B_45} ; |
---|
2900 | assign metric_A_46 = metric_28 + {{(M -SW -1){branch_A_46[SW]}}, branch_A_46} ; |
---|
2901 | assign metric_B_46 = metric_29 + {{(M -SW -1){branch_B_46[SW]}}, branch_B_46} ; |
---|
2902 | assign metric_A_47 = metric_30 + {{(M -SW -1){branch_A_47[SW]}}, branch_A_47} ; |
---|
2903 | assign metric_B_47 = metric_31 + {{(M -SW -1){branch_B_47[SW]}}, branch_B_47} ; |
---|
2904 | assign metric_A_48 = metric_32 + {{(M -SW -1){branch_A_48[SW]}}, branch_A_48} ; |
---|
2905 | assign metric_B_48 = metric_33 + {{(M -SW -1){branch_B_48[SW]}}, branch_B_48} ; |
---|
2906 | assign metric_A_49 = metric_34 + {{(M -SW -1){branch_A_49[SW]}}, branch_A_49} ; |
---|
2907 | assign metric_B_49 = metric_35 + {{(M -SW -1){branch_B_49[SW]}}, branch_B_49} ; |
---|
2908 | assign metric_A_50 = metric_36 + {{(M -SW -1){branch_A_50[SW]}}, branch_A_50} ; |
---|
2909 | assign metric_B_50 = metric_37 + {{(M -SW -1){branch_B_50[SW]}}, branch_B_50} ; |
---|
2910 | assign metric_A_51 = metric_38 + {{(M -SW -1){branch_A_51[SW]}}, branch_A_51} ; |
---|
2911 | assign metric_B_51 = metric_39 + {{(M -SW -1){branch_B_51[SW]}}, branch_B_51} ; |
---|
2912 | assign metric_A_52 = metric_40 + {{(M -SW -1){branch_A_52[SW]}}, branch_A_52} ; |
---|
2913 | assign metric_B_52 = metric_41 + {{(M -SW -1){branch_B_52[SW]}}, branch_B_52} ; |
---|
2914 | assign metric_A_53 = metric_42 + {{(M -SW -1){branch_A_53[SW]}}, branch_A_53} ; |
---|
2915 | assign metric_B_53 = metric_43 + {{(M -SW -1){branch_B_53[SW]}}, branch_B_53} ; |
---|
2916 | assign metric_A_54 = metric_44 + {{(M -SW -1){branch_A_54[SW]}}, branch_A_54} ; |
---|
2917 | assign metric_B_54 = metric_45 + {{(M -SW -1){branch_B_54[SW]}}, branch_B_54} ; |
---|
2918 | assign metric_A_55 = metric_46 + {{(M -SW -1){branch_A_55[SW]}}, branch_A_55} ; |
---|
2919 | assign metric_B_55 = metric_47 + {{(M -SW -1){branch_B_55[SW]}}, branch_B_55} ; |
---|
2920 | assign metric_A_56 = metric_48 + {{(M -SW -1){branch_A_56[SW]}}, branch_A_56} ; |
---|
2921 | assign metric_B_56 = metric_49 + {{(M -SW -1){branch_B_56[SW]}}, branch_B_56} ; |
---|
2922 | assign metric_A_57 = metric_50 + {{(M -SW -1){branch_A_57[SW]}}, branch_A_57} ; |
---|
2923 | assign metric_B_57 = metric_51 + {{(M -SW -1){branch_B_57[SW]}}, branch_B_57} ; |
---|
2924 | assign metric_A_58 = metric_52 + {{(M -SW -1){branch_A_58[SW]}}, branch_A_58} ; |
---|
2925 | assign metric_B_58 = metric_53 + {{(M -SW -1){branch_B_58[SW]}}, branch_B_58} ; |
---|
2926 | assign metric_A_59 = metric_54 + {{(M -SW -1){branch_A_59[SW]}}, branch_A_59} ; |
---|
2927 | assign metric_B_59 = metric_55 + {{(M -SW -1){branch_B_59[SW]}}, branch_B_59} ; |
---|
2928 | assign metric_A_60 = metric_56 + {{(M -SW -1){branch_A_60[SW]}}, branch_A_60} ; |
---|
2929 | assign metric_B_60 = metric_57 + {{(M -SW -1){branch_B_60[SW]}}, branch_B_60} ; |
---|
2930 | assign metric_A_61 = metric_58 + {{(M -SW -1){branch_A_61[SW]}}, branch_A_61} ; |
---|
2931 | assign metric_B_61 = metric_59 + {{(M -SW -1){branch_B_61[SW]}}, branch_B_61} ; |
---|
2932 | assign metric_A_62 = metric_60 + {{(M -SW -1){branch_A_62[SW]}}, branch_A_62} ; |
---|
2933 | assign metric_B_62 = metric_61 + {{(M -SW -1){branch_B_62[SW]}}, branch_B_62} ; |
---|
2934 | assign metric_A_63 = metric_62 + {{(M -SW -1){branch_A_63[SW]}}, branch_A_63} ; |
---|
2935 | assign metric_B_63 = metric_63 + {{(M -SW -1){branch_B_63[SW]}}, branch_B_63} ; |
---|
2936 | |
---|
2937 | assign diff_0 = metric_A_0 - metric_B_0 ; |
---|
2938 | assign diff_1 = metric_A_1 - metric_B_1 ; |
---|
2939 | assign diff_2 = metric_A_2 - metric_B_2 ; |
---|
2940 | assign diff_3 = metric_A_3 - metric_B_3 ; |
---|
2941 | assign diff_4 = metric_A_4 - metric_B_4 ; |
---|
2942 | assign diff_5 = metric_A_5 - metric_B_5 ; |
---|
2943 | assign diff_6 = metric_A_6 - metric_B_6 ; |
---|
2944 | assign diff_7 = metric_A_7 - metric_B_7 ; |
---|
2945 | assign diff_8 = metric_A_8 - metric_B_8 ; |
---|
2946 | assign diff_9 = metric_A_9 - metric_B_9 ; |
---|
2947 | assign diff_10 = metric_A_10 - metric_B_10 ; |
---|
2948 | assign diff_11 = metric_A_11 - metric_B_11 ; |
---|
2949 | assign diff_12 = metric_A_12 - metric_B_12 ; |
---|
2950 | assign diff_13 = metric_A_13 - metric_B_13 ; |
---|
2951 | assign diff_14 = metric_A_14 - metric_B_14 ; |
---|
2952 | assign diff_15 = metric_A_15 - metric_B_15 ; |
---|
2953 | assign diff_16 = metric_A_16 - metric_B_16 ; |
---|
2954 | assign diff_17 = metric_A_17 - metric_B_17 ; |
---|
2955 | assign diff_18 = metric_A_18 - metric_B_18 ; |
---|
2956 | assign diff_19 = metric_A_19 - metric_B_19 ; |
---|
2957 | assign diff_20 = metric_A_20 - metric_B_20 ; |
---|
2958 | assign diff_21 = metric_A_21 - metric_B_21 ; |
---|
2959 | assign diff_22 = metric_A_22 - metric_B_22 ; |
---|
2960 | assign diff_23 = metric_A_23 - metric_B_23 ; |
---|
2961 | assign diff_24 = metric_A_24 - metric_B_24 ; |
---|
2962 | assign diff_25 = metric_A_25 - metric_B_25 ; |
---|
2963 | assign diff_26 = metric_A_26 - metric_B_26 ; |
---|
2964 | assign diff_27 = metric_A_27 - metric_B_27 ; |
---|
2965 | assign diff_28 = metric_A_28 - metric_B_28 ; |
---|
2966 | assign diff_29 = metric_A_29 - metric_B_29 ; |
---|
2967 | assign diff_30 = metric_A_30 - metric_B_30 ; |
---|
2968 | assign diff_31 = metric_A_31 - metric_B_31 ; |
---|
2969 | assign diff_32 = metric_A_32 - metric_B_32 ; |
---|
2970 | assign diff_33 = metric_A_33 - metric_B_33 ; |
---|
2971 | assign diff_34 = metric_A_34 - metric_B_34 ; |
---|
2972 | assign diff_35 = metric_A_35 - metric_B_35 ; |
---|
2973 | assign diff_36 = metric_A_36 - metric_B_36 ; |
---|
2974 | assign diff_37 = metric_A_37 - metric_B_37 ; |
---|
2975 | assign diff_38 = metric_A_38 - metric_B_38 ; |
---|
2976 | assign diff_39 = metric_A_39 - metric_B_39 ; |
---|
2977 | assign diff_40 = metric_A_40 - metric_B_40 ; |
---|
2978 | assign diff_41 = metric_A_41 - metric_B_41 ; |
---|
2979 | assign diff_42 = metric_A_42 - metric_B_42 ; |
---|
2980 | assign diff_43 = metric_A_43 - metric_B_43 ; |
---|
2981 | assign diff_44 = metric_A_44 - metric_B_44 ; |
---|
2982 | assign diff_45 = metric_A_45 - metric_B_45 ; |
---|
2983 | assign diff_46 = metric_A_46 - metric_B_46 ; |
---|
2984 | assign diff_47 = metric_A_47 - metric_B_47 ; |
---|
2985 | assign diff_48 = metric_A_48 - metric_B_48 ; |
---|
2986 | assign diff_49 = metric_A_49 - metric_B_49 ; |
---|
2987 | assign diff_50 = metric_A_50 - metric_B_50 ; |
---|
2988 | assign diff_51 = metric_A_51 - metric_B_51 ; |
---|
2989 | assign diff_52 = metric_A_52 - metric_B_52 ; |
---|
2990 | assign diff_53 = metric_A_53 - metric_B_53 ; |
---|
2991 | assign diff_54 = metric_A_54 - metric_B_54 ; |
---|
2992 | assign diff_55 = metric_A_55 - metric_B_55 ; |
---|
2993 | assign diff_56 = metric_A_56 - metric_B_56 ; |
---|
2994 | assign diff_57 = metric_A_57 - metric_B_57 ; |
---|
2995 | assign diff_58 = metric_A_58 - metric_B_58 ; |
---|
2996 | assign diff_59 = metric_A_59 - metric_B_59 ; |
---|
2997 | assign diff_60 = metric_A_60 - metric_B_60 ; |
---|
2998 | assign diff_61 = metric_A_61 - metric_B_61 ; |
---|
2999 | assign diff_62 = metric_A_62 - metric_B_62 ; |
---|
3000 | assign diff_63 = metric_A_63 - metric_B_63 ; |
---|
3001 | |
---|
3002 | assign metric_next_0 = diff_0 [M -1] ? metric_B_0 : metric_A_0 ; |
---|
3003 | assign metric_next_1 = diff_1 [M -1] ? metric_B_1 : metric_A_1 ; |
---|
3004 | assign metric_next_2 = diff_2 [M -1] ? metric_B_2 : metric_A_2 ; |
---|
3005 | assign metric_next_3 = diff_3 [M -1] ? metric_B_3 : metric_A_3 ; |
---|
3006 | assign metric_next_4 = diff_4 [M -1] ? metric_B_4 : metric_A_4 ; |
---|
3007 | assign metric_next_5 = diff_5 [M -1] ? metric_B_5 : metric_A_5 ; |
---|
3008 | assign metric_next_6 = diff_6 [M -1] ? metric_B_6 : metric_A_6 ; |
---|
3009 | assign metric_next_7 = diff_7 [M -1] ? metric_B_7 : metric_A_7 ; |
---|
3010 | assign metric_next_8 = diff_8 [M -1] ? metric_B_8 : metric_A_8 ; |
---|
3011 | assign metric_next_9 = diff_9 [M -1] ? metric_B_9 : metric_A_9 ; |
---|
3012 | assign metric_next_10 = diff_10 [M -1] ? metric_B_10 : metric_A_10 ; |
---|
3013 | assign metric_next_11 = diff_11 [M -1] ? metric_B_11 : metric_A_11 ; |
---|
3014 | assign metric_next_12 = diff_12 [M -1] ? metric_B_12 : metric_A_12 ; |
---|
3015 | assign metric_next_13 = diff_13 [M -1] ? metric_B_13 : metric_A_13 ; |
---|
3016 | assign metric_next_14 = diff_14 [M -1] ? metric_B_14 : metric_A_14 ; |
---|
3017 | assign metric_next_15 = diff_15 [M -1] ? metric_B_15 : metric_A_15 ; |
---|
3018 | assign metric_next_16 = diff_16 [M -1] ? metric_B_16 : metric_A_16 ; |
---|
3019 | assign metric_next_17 = diff_17 [M -1] ? metric_B_17 : metric_A_17 ; |
---|
3020 | assign metric_next_18 = diff_18 [M -1] ? metric_B_18 : metric_A_18 ; |
---|
3021 | assign metric_next_19 = diff_19 [M -1] ? metric_B_19 : metric_A_19 ; |
---|
3022 | assign metric_next_20 = diff_20 [M -1] ? metric_B_20 : metric_A_20 ; |
---|
3023 | assign metric_next_21 = diff_21 [M -1] ? metric_B_21 : metric_A_21 ; |
---|
3024 | assign metric_next_22 = diff_22 [M -1] ? metric_B_22 : metric_A_22 ; |
---|
3025 | assign metric_next_23 = diff_23 [M -1] ? metric_B_23 : metric_A_23 ; |
---|
3026 | assign metric_next_24 = diff_24 [M -1] ? metric_B_24 : metric_A_24 ; |
---|
3027 | assign metric_next_25 = diff_25 [M -1] ? metric_B_25 : metric_A_25 ; |
---|
3028 | assign metric_next_26 = diff_26 [M -1] ? metric_B_26 : metric_A_26 ; |
---|
3029 | assign metric_next_27 = diff_27 [M -1] ? metric_B_27 : metric_A_27 ; |
---|
3030 | assign metric_next_28 = diff_28 [M -1] ? metric_B_28 : metric_A_28 ; |
---|
3031 | assign metric_next_29 = diff_29 [M -1] ? metric_B_29 : metric_A_29 ; |
---|
3032 | assign metric_next_30 = diff_30 [M -1] ? metric_B_30 : metric_A_30 ; |
---|
3033 | assign metric_next_31 = diff_31 [M -1] ? metric_B_31 : metric_A_31 ; |
---|
3034 | assign metric_next_32 = diff_32 [M -1] ? metric_B_32 : metric_A_32 ; |
---|
3035 | assign metric_next_33 = diff_33 [M -1] ? metric_B_33 : metric_A_33 ; |
---|
3036 | assign metric_next_34 = diff_34 [M -1] ? metric_B_34 : metric_A_34 ; |
---|
3037 | assign metric_next_35 = diff_35 [M -1] ? metric_B_35 : metric_A_35 ; |
---|
3038 | assign metric_next_36 = diff_36 [M -1] ? metric_B_36 : metric_A_36 ; |
---|
3039 | assign metric_next_37 = diff_37 [M -1] ? metric_B_37 : metric_A_37 ; |
---|
3040 | assign metric_next_38 = diff_38 [M -1] ? metric_B_38 : metric_A_38 ; |
---|
3041 | assign metric_next_39 = diff_39 [M -1] ? metric_B_39 : metric_A_39 ; |
---|
3042 | assign metric_next_40 = diff_40 [M -1] ? metric_B_40 : metric_A_40 ; |
---|
3043 | assign metric_next_41 = diff_41 [M -1] ? metric_B_41 : metric_A_41 ; |
---|
3044 | assign metric_next_42 = diff_42 [M -1] ? metric_B_42 : metric_A_42 ; |
---|
3045 | assign metric_next_43 = diff_43 [M -1] ? metric_B_43 : metric_A_43 ; |
---|
3046 | assign metric_next_44 = diff_44 [M -1] ? metric_B_44 : metric_A_44 ; |
---|
3047 | assign metric_next_45 = diff_45 [M -1] ? metric_B_45 : metric_A_45 ; |
---|
3048 | assign metric_next_46 = diff_46 [M -1] ? metric_B_46 : metric_A_46 ; |
---|
3049 | assign metric_next_47 = diff_47 [M -1] ? metric_B_47 : metric_A_47 ; |
---|
3050 | assign metric_next_48 = diff_48 [M -1] ? metric_B_48 : metric_A_48 ; |
---|
3051 | assign metric_next_49 = diff_49 [M -1] ? metric_B_49 : metric_A_49 ; |
---|
3052 | assign metric_next_50 = diff_50 [M -1] ? metric_B_50 : metric_A_50 ; |
---|
3053 | assign metric_next_51 = diff_51 [M -1] ? metric_B_51 : metric_A_51 ; |
---|
3054 | assign metric_next_52 = diff_52 [M -1] ? metric_B_52 : metric_A_52 ; |
---|
3055 | assign metric_next_53 = diff_53 [M -1] ? metric_B_53 : metric_A_53 ; |
---|
3056 | assign metric_next_54 = diff_54 [M -1] ? metric_B_54 : metric_A_54 ; |
---|
3057 | assign metric_next_55 = diff_55 [M -1] ? metric_B_55 : metric_A_55 ; |
---|
3058 | assign metric_next_56 = diff_56 [M -1] ? metric_B_56 : metric_A_56 ; |
---|
3059 | assign metric_next_57 = diff_57 [M -1] ? metric_B_57 : metric_A_57 ; |
---|
3060 | assign metric_next_58 = diff_58 [M -1] ? metric_B_58 : metric_A_58 ; |
---|
3061 | assign metric_next_59 = diff_59 [M -1] ? metric_B_59 : metric_A_59 ; |
---|
3062 | assign metric_next_60 = diff_60 [M -1] ? metric_B_60 : metric_A_60 ; |
---|
3063 | assign metric_next_61 = diff_61 [M -1] ? metric_B_61 : metric_A_61 ; |
---|
3064 | assign metric_next_62 = diff_62 [M -1] ? metric_B_62 : metric_A_62 ; |
---|
3065 | assign metric_next_63 = diff_63 [M -1] ? metric_B_63 : metric_A_63 ; |
---|
3066 | |
---|
3067 | always @ (posedge clk or negedge nrst) |
---|
3068 | if (~nrst) |
---|
3069 | begin |
---|
3070 | metric_0 <= 10 ; |
---|
3071 | metric_1 <= 0 ; |
---|
3072 | metric_2 <= 0 ; |
---|
3073 | metric_3 <= 0 ; |
---|
3074 | metric_4 <= 0 ; |
---|
3075 | metric_5 <= 0 ; |
---|
3076 | metric_6 <= 0 ; |
---|
3077 | metric_7 <= 0 ; |
---|
3078 | metric_8 <= 0 ; |
---|
3079 | metric_9 <= 0 ; |
---|
3080 | metric_10 <= 0 ; |
---|
3081 | metric_11 <= 0 ; |
---|
3082 | metric_12 <= 0 ; |
---|
3083 | metric_13 <= 0 ; |
---|
3084 | metric_14 <= 0 ; |
---|
3085 | metric_15 <= 0 ; |
---|
3086 | metric_16 <= 0 ; |
---|
3087 | metric_17 <= 0 ; |
---|
3088 | metric_18 <= 0 ; |
---|
3089 | metric_19 <= 0 ; |
---|
3090 | metric_20 <= 0 ; |
---|
3091 | metric_21 <= 0 ; |
---|
3092 | metric_22 <= 0 ; |
---|
3093 | metric_23 <= 0 ; |
---|
3094 | metric_24 <= 0 ; |
---|
3095 | metric_25 <= 0 ; |
---|
3096 | metric_26 <= 0 ; |
---|
3097 | metric_27 <= 0 ; |
---|
3098 | metric_28 <= 0 ; |
---|
3099 | metric_29 <= 0 ; |
---|
3100 | metric_30 <= 0 ; |
---|
3101 | metric_31 <= 0 ; |
---|
3102 | metric_32 <= 0 ; |
---|
3103 | metric_33 <= 0 ; |
---|
3104 | metric_34 <= 0 ; |
---|
3105 | metric_35 <= 0 ; |
---|
3106 | metric_36 <= 0 ; |
---|
3107 | metric_37 <= 0 ; |
---|
3108 | metric_38 <= 0 ; |
---|
3109 | metric_39 <= 0 ; |
---|
3110 | metric_40 <= 0 ; |
---|
3111 | metric_41 <= 0 ; |
---|
3112 | metric_42 <= 0 ; |
---|
3113 | metric_43 <= 0 ; |
---|
3114 | metric_44 <= 0 ; |
---|
3115 | metric_45 <= 0 ; |
---|
3116 | metric_46 <= 0 ; |
---|
3117 | metric_47 <= 0 ; |
---|
3118 | metric_48 <= 0 ; |
---|
3119 | metric_49 <= 0 ; |
---|
3120 | metric_50 <= 0 ; |
---|
3121 | metric_51 <= 0 ; |
---|
3122 | metric_52 <= 0 ; |
---|
3123 | metric_53 <= 0 ; |
---|
3124 | metric_54 <= 0 ; |
---|
3125 | metric_55 <= 0 ; |
---|
3126 | metric_56 <= 0 ; |
---|
3127 | metric_57 <= 0 ; |
---|
3128 | metric_58 <= 0 ; |
---|
3129 | metric_59 <= 0 ; |
---|
3130 | metric_60 <= 0 ; |
---|
3131 | metric_61 <= 0 ; |
---|
3132 | metric_62 <= 0 ; |
---|
3133 | metric_63 <= 0 ; |
---|
3134 | end |
---|
3135 | else if (packet_start) |
---|
3136 | begin |
---|
3137 | metric_0 <= 10 ; |
---|
3138 | metric_1 <= 0 ; |
---|
3139 | metric_2 <= 0 ; |
---|
3140 | metric_3 <= 0 ; |
---|
3141 | metric_4 <= 0 ; |
---|
3142 | metric_5 <= 0 ; |
---|
3143 | metric_6 <= 0 ; |
---|
3144 | metric_7 <= 0 ; |
---|
3145 | metric_8 <= 0 ; |
---|
3146 | metric_9 <= 0 ; |
---|
3147 | metric_10 <= 0 ; |
---|
3148 | metric_11 <= 0 ; |
---|
3149 | metric_12 <= 0 ; |
---|
3150 | metric_13 <= 0 ; |
---|
3151 | metric_14 <= 0 ; |
---|
3152 | metric_15 <= 0 ; |
---|
3153 | metric_16 <= 0 ; |
---|
3154 | metric_17 <= 0 ; |
---|
3155 | metric_18 <= 0 ; |
---|
3156 | metric_19 <= 0 ; |
---|
3157 | metric_20 <= 0 ; |
---|
3158 | metric_21 <= 0 ; |
---|
3159 | metric_22 <= 0 ; |
---|
3160 | metric_23 <= 0 ; |
---|
3161 | metric_24 <= 0 ; |
---|
3162 | metric_25 <= 0 ; |
---|
3163 | metric_26 <= 0 ; |
---|
3164 | metric_27 <= 0 ; |
---|
3165 | metric_28 <= 0 ; |
---|
3166 | metric_29 <= 0 ; |
---|
3167 | metric_30 <= 0 ; |
---|
3168 | metric_31 <= 0 ; |
---|
3169 | metric_32 <= 0 ; |
---|
3170 | metric_33 <= 0 ; |
---|
3171 | metric_34 <= 0 ; |
---|
3172 | metric_35 <= 0 ; |
---|
3173 | metric_36 <= 0 ; |
---|
3174 | metric_37 <= 0 ; |
---|
3175 | metric_38 <= 0 ; |
---|
3176 | metric_39 <= 0 ; |
---|
3177 | metric_40 <= 0 ; |
---|
3178 | metric_41 <= 0 ; |
---|
3179 | metric_42 <= 0 ; |
---|
3180 | metric_43 <= 0 ; |
---|
3181 | metric_44 <= 0 ; |
---|
3182 | metric_45 <= 0 ; |
---|
3183 | metric_46 <= 0 ; |
---|
3184 | metric_47 <= 0 ; |
---|
3185 | metric_48 <= 0 ; |
---|
3186 | metric_49 <= 0 ; |
---|
3187 | metric_50 <= 0 ; |
---|
3188 | metric_51 <= 0 ; |
---|
3189 | metric_52 <= 0 ; |
---|
3190 | metric_53 <= 0 ; |
---|
3191 | metric_54 <= 0 ; |
---|
3192 | metric_55 <= 0 ; |
---|
3193 | metric_56 <= 0 ; |
---|
3194 | metric_57 <= 0 ; |
---|
3195 | metric_58 <= 0 ; |
---|
3196 | metric_59 <= 0 ; |
---|
3197 | metric_60 <= 0 ; |
---|
3198 | metric_61 <= 0 ; |
---|
3199 | metric_62 <= 0 ; |
---|
3200 | metric_63 <= 0 ; |
---|
3201 | end |
---|
3202 | else if (dv_in_gate) |
---|
3203 | begin |
---|
3204 | // update metric |
---|
3205 | metric_0 <= metric_next_0 ; |
---|
3206 | metric_1 <= metric_next_1 ; |
---|
3207 | metric_2 <= metric_next_2 ; |
---|
3208 | metric_3 <= metric_next_3 ; |
---|
3209 | metric_4 <= metric_next_4 ; |
---|
3210 | metric_5 <= metric_next_5 ; |
---|
3211 | metric_6 <= metric_next_6 ; |
---|
3212 | metric_7 <= metric_next_7 ; |
---|
3213 | metric_8 <= metric_next_8 ; |
---|
3214 | metric_9 <= metric_next_9 ; |
---|
3215 | metric_10 <= metric_next_10; |
---|
3216 | metric_11 <= metric_next_11; |
---|
3217 | metric_12 <= metric_next_12; |
---|
3218 | metric_13 <= metric_next_13; |
---|
3219 | metric_14 <= metric_next_14; |
---|
3220 | metric_15 <= metric_next_15; |
---|
3221 | metric_16 <= metric_next_16 ; |
---|
3222 | metric_17 <= metric_next_17; |
---|
3223 | metric_18 <= metric_next_18; |
---|
3224 | metric_19 <= metric_next_19; |
---|
3225 | metric_20 <= metric_next_20; |
---|
3226 | metric_21 <= metric_next_21; |
---|
3227 | metric_22 <= metric_next_22; |
---|
3228 | metric_23 <= metric_next_23; |
---|
3229 | metric_24 <= metric_next_24; |
---|
3230 | metric_25 <= metric_next_25; |
---|
3231 | metric_26 <= metric_next_26; |
---|
3232 | metric_27 <= metric_next_27; |
---|
3233 | metric_28 <= metric_next_28; |
---|
3234 | metric_29 <= metric_next_29; |
---|
3235 | metric_30 <= metric_next_30; |
---|
3236 | metric_31 <= metric_next_31; |
---|
3237 | metric_32 <= metric_next_32 ; |
---|
3238 | metric_33 <= metric_next_33; |
---|
3239 | metric_34 <= metric_next_34; |
---|
3240 | metric_35 <= metric_next_35; |
---|
3241 | metric_36 <= metric_next_36; |
---|
3242 | metric_37 <= metric_next_37; |
---|
3243 | metric_38 <= metric_next_38; |
---|
3244 | metric_39 <= metric_next_39; |
---|
3245 | metric_40 <= metric_next_40; |
---|
3246 | metric_41 <= metric_next_41; |
---|
3247 | metric_42 <= metric_next_42; |
---|
3248 | metric_43 <= metric_next_43; |
---|
3249 | metric_44 <= metric_next_44; |
---|
3250 | metric_45 <= metric_next_45; |
---|
3251 | metric_46 <= metric_next_46; |
---|
3252 | metric_47 <= metric_next_47; |
---|
3253 | metric_48 <= metric_next_48 ; |
---|
3254 | metric_49 <= metric_next_49; |
---|
3255 | metric_50 <= metric_next_50; |
---|
3256 | metric_51 <= metric_next_51; |
---|
3257 | metric_52 <= metric_next_52; |
---|
3258 | metric_53 <= metric_next_53; |
---|
3259 | metric_54 <= metric_next_54; |
---|
3260 | metric_55 <= metric_next_55; |
---|
3261 | metric_56 <= metric_next_56; |
---|
3262 | metric_57 <= metric_next_57; |
---|
3263 | metric_58 <= metric_next_58; |
---|
3264 | metric_59 <= metric_next_59; |
---|
3265 | metric_60 <= metric_next_60; |
---|
3266 | metric_61 <= metric_next_61; |
---|
3267 | metric_62 <= metric_next_62; |
---|
3268 | metric_63 <= metric_next_63; |
---|
3269 | end |
---|
3270 | |
---|
3271 | always @ (posedge clk or negedge nrst) |
---|
3272 | if (~nrst) |
---|
3273 | wptr <= 0 ; |
---|
3274 | else if (packet_start) |
---|
3275 | wptr <= 0 ; |
---|
3276 | else if (dv_in_gate) |
---|
3277 | wptr <= wptr + 1 ; |
---|
3278 | |
---|
3279 | always @ (posedge clk or negedge nrst) |
---|
3280 | if (~nrst) |
---|
3281 | last_wptr <= 1'b0 ; |
---|
3282 | else if (dv_in_gate) |
---|
3283 | last_wptr <= wptr ; |
---|
3284 | |
---|
3285 | always @ (posedge clk) |
---|
3286 | if(dv_in_gate) |
---|
3287 | begin |
---|
3288 | // update transition |
---|
3289 | tran_state_0 [wptr] <= diff_0 [M -1] ; |
---|
3290 | tran_state_1 [wptr] <= diff_1 [M -1] ; |
---|
3291 | tran_state_2 [wptr] <= diff_2 [M -1] ; |
---|
3292 | tran_state_3 [wptr] <= diff_3 [M -1] ; |
---|
3293 | tran_state_4 [wptr] <= diff_4 [M -1] ; |
---|
3294 | tran_state_5 [wptr] <= diff_5 [M -1] ; |
---|
3295 | tran_state_6 [wptr] <= diff_6 [M -1] ; |
---|
3296 | tran_state_7 [wptr] <= diff_7 [M -1] ; |
---|
3297 | tran_state_8 [wptr] <= diff_8 [M -1] ; |
---|
3298 | tran_state_9 [wptr] <= diff_9 [M -1] ; |
---|
3299 | tran_state_10 [wptr] <= diff_10 [M -1] ; |
---|
3300 | tran_state_11 [wptr] <= diff_11 [M -1] ; |
---|
3301 | tran_state_12 [wptr] <= diff_12 [M -1] ; |
---|
3302 | tran_state_13 [wptr] <= diff_13 [M -1] ; |
---|
3303 | tran_state_14 [wptr] <= diff_14 [M -1] ; |
---|
3304 | tran_state_15 [wptr] <= diff_15 [M -1] ; |
---|
3305 | tran_state_16 [wptr] <= diff_16 [M -1] ; |
---|
3306 | tran_state_17 [wptr] <= diff_17 [M -1] ; |
---|
3307 | tran_state_18 [wptr] <= diff_18 [M -1] ; |
---|
3308 | tran_state_19 [wptr] <= diff_19 [M -1] ; |
---|
3309 | tran_state_20 [wptr] <= diff_20 [M -1] ; |
---|
3310 | tran_state_21 [wptr] <= diff_21 [M -1] ; |
---|
3311 | tran_state_22 [wptr] <= diff_22 [M -1] ; |
---|
3312 | tran_state_23 [wptr] <= diff_23 [M -1] ; |
---|
3313 | tran_state_24 [wptr] <= diff_24 [M -1] ; |
---|
3314 | tran_state_25 [wptr] <= diff_25 [M -1] ; |
---|
3315 | tran_state_26 [wptr] <= diff_26 [M -1] ; |
---|
3316 | tran_state_27 [wptr] <= diff_27 [M -1] ; |
---|
3317 | tran_state_28 [wptr] <= diff_28 [M -1] ; |
---|
3318 | tran_state_29 [wptr] <= diff_29 [M -1] ; |
---|
3319 | tran_state_30 [wptr] <= diff_30 [M -1] ; |
---|
3320 | tran_state_31 [wptr] <= diff_31 [M -1] ; |
---|
3321 | tran_state_32 [wptr] <= diff_32 [M -1] ; |
---|
3322 | tran_state_33 [wptr] <= diff_33 [M -1] ; |
---|
3323 | tran_state_34 [wptr] <= diff_34 [M -1] ; |
---|
3324 | tran_state_35 [wptr] <= diff_35 [M -1] ; |
---|
3325 | tran_state_36 [wptr] <= diff_36 [M -1] ; |
---|
3326 | tran_state_37 [wptr] <= diff_37 [M -1] ; |
---|
3327 | tran_state_38 [wptr] <= diff_38 [M -1] ; |
---|
3328 | tran_state_39 [wptr] <= diff_39 [M -1] ; |
---|
3329 | tran_state_40 [wptr] <= diff_40 [M -1] ; |
---|
3330 | tran_state_41 [wptr] <= diff_41 [M -1] ; |
---|
3331 | tran_state_42 [wptr] <= diff_42 [M -1] ; |
---|
3332 | tran_state_43 [wptr] <= diff_43 [M -1] ; |
---|
3333 | tran_state_44 [wptr] <= diff_44 [M -1] ; |
---|
3334 | tran_state_45 [wptr] <= diff_45 [M -1] ; |
---|
3335 | tran_state_46 [wptr] <= diff_46 [M -1] ; |
---|
3336 | tran_state_47 [wptr] <= diff_47 [M -1] ; |
---|
3337 | tran_state_48 [wptr] <= diff_48 [M -1] ; |
---|
3338 | tran_state_49 [wptr] <= diff_49 [M -1] ; |
---|
3339 | tran_state_50 [wptr] <= diff_50 [M -1] ; |
---|
3340 | tran_state_51 [wptr] <= diff_51 [M -1] ; |
---|
3341 | tran_state_52 [wptr] <= diff_52 [M -1] ; |
---|
3342 | tran_state_53 [wptr] <= diff_53 [M -1] ; |
---|
3343 | tran_state_54 [wptr] <= diff_54 [M -1] ; |
---|
3344 | tran_state_55 [wptr] <= diff_55 [M -1] ; |
---|
3345 | tran_state_56 [wptr] <= diff_56 [M -1] ; |
---|
3346 | tran_state_57 [wptr] <= diff_57 [M -1] ; |
---|
3347 | tran_state_58 [wptr] <= diff_58 [M -1] ; |
---|
3348 | tran_state_59 [wptr] <= diff_59 [M -1] ; |
---|
3349 | tran_state_60 [wptr] <= diff_60 [M -1] ; |
---|
3350 | tran_state_61 [wptr] <= diff_61 [M -1] ; |
---|
3351 | tran_state_62 [wptr] <= diff_62 [M -1] ; |
---|
3352 | tran_state_63 [wptr] <= diff_63 [M -1] ; |
---|
3353 | end |
---|
3354 | |
---|
3355 | always @ (posedge clk or negedge nrst) |
---|
3356 | if (~nrst) |
---|
3357 | begin |
---|
3358 | trace <= 1'b0 ; |
---|
3359 | cnt <= 0 ; |
---|
3360 | trace_start_wptr <= 0 ; |
---|
3361 | end |
---|
3362 | else if (packet_start) |
---|
3363 | begin |
---|
3364 | trace <= 1'b0 ; |
---|
3365 | cnt <= 0 ; |
---|
3366 | end |
---|
3367 | else if (dv_in_gate) |
---|
3368 | begin |
---|
3369 | if (cnt == L-1) |
---|
3370 | begin |
---|
3371 | trace <= 1'b1 ; |
---|
3372 | trace_start_wptr <= wptr ; |
---|
3373 | cnt <= C ; |
---|
3374 | end |
---|
3375 | else |
---|
3376 | begin |
---|
3377 | trace <= 1'b0 ; |
---|
3378 | cnt <= cnt + 1 ; |
---|
3379 | end |
---|
3380 | end |
---|
3381 | else if (trace2) |
---|
3382 | trace_start_wptr <= last_wptr ; |
---|
3383 | else |
---|
3384 | trace <= 1'b0 ; |
---|
3385 | |
---|
3386 | always @ (posedge clk or negedge nrst) |
---|
3387 | if (~nrst) |
---|
3388 | begin |
---|
3389 | flush_en <= 1'b0 ; |
---|
3390 | flush_cnt <= 0 ; |
---|
3391 | end |
---|
3392 | else if (packet_end) |
---|
3393 | begin |
---|
3394 | flush_en <= 1 ; |
---|
3395 | flush_cnt <= 0 ; |
---|
3396 | end |
---|
3397 | else if (flush_en) |
---|
3398 | begin |
---|
3399 | if (flush_cnt == 63) |
---|
3400 | flush_en <= 1'b0 ; |
---|
3401 | else |
---|
3402 | flush_cnt <= flush_cnt + 1 ; |
---|
3403 | end |
---|
3404 | |
---|
3405 | assign flush = flush_cnt == 60 ; |
---|
3406 | |
---|
3407 | always @ (posedge clk or negedge nrst) |
---|
3408 | if (~nrst) |
---|
3409 | done_i <= 1'b0 ; |
---|
3410 | else if (packet_start) |
---|
3411 | done_i <= 1'b0 ; |
---|
3412 | //else if (packet_end && cnt == L-1) |
---|
3413 | else if (trace2 & last_cnt_next[LW-1]) |
---|
3414 | done_i <= 1'b1 ; |
---|
3415 | else if (last_trace_d3) |
---|
3416 | done_i <= 1'b1 ; |
---|
3417 | |
---|
3418 | |
---|
3419 | always @ (posedge clk or negedge nrst) |
---|
3420 | if (~nrst) |
---|
3421 | last_trace <= 1'b0 ; |
---|
3422 | else if (packet_start) |
---|
3423 | last_trace <= 1'b0 ; |
---|
3424 | else if (flush && trace_done && cnt !=L-1 ) |
---|
3425 | last_trace <= 1'b1 ; |
---|
3426 | |
---|
3427 | always @ (posedge clk) |
---|
3428 | last_trace_s0 <= last_trace ; |
---|
3429 | |
---|
3430 | assign trace2 = ~last_trace_s0 & last_trace ; |
---|
3431 | assign trace_pos_i = trace | trace2 ; |
---|
3432 | |
---|
3433 | always @ (posedge clk or negedge nrst) |
---|
3434 | if (~nrst) |
---|
3435 | begin |
---|
3436 | trace2_s1 <= 1'b0 ; |
---|
3437 | trace2_s2 <= 1'b0 ; |
---|
3438 | end |
---|
3439 | else |
---|
3440 | begin |
---|
3441 | trace2_s1 <= trace2 ; |
---|
3442 | trace2_s2 <= trace2_s1 ; |
---|
3443 | end |
---|
3444 | |
---|
3445 | |
---|
3446 | always @ (posedge clk) |
---|
3447 | begin |
---|
3448 | trace_pos_s0 <= trace_pos_i ; |
---|
3449 | trace_pos <= trace_pos_s0 ; |
---|
3450 | end |
---|
3451 | |
---|
3452 | always @ (posedge clk or negedge nrst) |
---|
3453 | if(~nrst) |
---|
3454 | last_trace_num <= 0 ; |
---|
3455 | else |
---|
3456 | begin |
---|
3457 | if (packet_start) |
---|
3458 | last_trace_num <= 0 ; |
---|
3459 | else if (trace2) |
---|
3460 | last_trace_num <= L -cnt ; |
---|
3461 | else if (last_trace_d0) |
---|
3462 | last_trace_num <= last_trace_num + R ; |
---|
3463 | end |
---|
3464 | |
---|
3465 | always @ (posedge clk) |
---|
3466 | begin |
---|
3467 | last_trace_d0 <= last_trace & trace_done_pos ; |
---|
3468 | last_trace_d1 <= last_trace_d0 ; |
---|
3469 | last_trace_d2 <= last_trace_d1 ; |
---|
3470 | last_trace_d3 <= last_trace_d2 ; |
---|
3471 | last_trace_d4 <= last_trace_d3 ; |
---|
3472 | last_trace_d5 <= last_trace_d4 ; |
---|
3473 | end |
---|
3474 | |
---|
3475 | assign last_cnt_next = last_cnt - R ; |
---|
3476 | |
---|
3477 | always @ (posedge clk or negedge nrst) |
---|
3478 | if(~nrst) |
---|
3479 | begin |
---|
3480 | one_more_out <= 1'b0 ; |
---|
3481 | last_cnt <= 0 ; |
---|
3482 | end |
---|
3483 | else |
---|
3484 | begin |
---|
3485 | if (packet_start) |
---|
3486 | begin |
---|
3487 | one_more_out <= 1'b0 ; |
---|
3488 | last_cnt <= 0 ; |
---|
3489 | end |
---|
3490 | else if (flush) |
---|
3491 | last_cnt <= cnt ; |
---|
3492 | else if (last_trace_d5) |
---|
3493 | begin |
---|
3494 | if (~last_cnt_next[LW-1]) |
---|
3495 | begin |
---|
3496 | last_cnt <= last_cnt_next ; |
---|
3497 | one_more_out <= 1'b1 ; |
---|
3498 | end |
---|
3499 | end |
---|
3500 | else |
---|
3501 | one_more_out <= 1'b0 ; |
---|
3502 | end |
---|
3503 | |
---|
3504 | always @ (posedge clk or negedge nrst) |
---|
3505 | if (~nrst) |
---|
3506 | trace_en <= 0 ; |
---|
3507 | else if (packet_start) |
---|
3508 | trace_en <= 0 ; |
---|
3509 | else if (trace_pos) |
---|
3510 | trace_en <= 1'b1 ; |
---|
3511 | else if (trace_cnt == L-2) |
---|
3512 | trace_en <= 1'b0 ; |
---|
3513 | |
---|
3514 | always @ (posedge clk or negedge nrst) |
---|
3515 | if (~nrst) |
---|
3516 | trace_cnt <= 0 ; |
---|
3517 | else if (trace_pos) |
---|
3518 | trace_cnt <= 0 ; |
---|
3519 | else if (trace_en) |
---|
3520 | trace_cnt <= trace_cnt + 2; |
---|
3521 | |
---|
3522 | assign trace_done = trace_cnt == L ; |
---|
3523 | |
---|
3524 | always @ (posedge clk) |
---|
3525 | trace_done_s0 <= trace_done ; |
---|
3526 | assign trace_done_pos = ~trace_done_s0 & trace_done ; |
---|
3527 | |
---|
3528 | //============================== |
---|
3529 | // Get max metric |
---|
3530 | //============================== |
---|
3531 | max_metric #(M, K) max_metric_0 ( |
---|
3532 | .clk (clk ), |
---|
3533 | .a (metric_0 ), |
---|
3534 | .b (metric_1 ), |
---|
3535 | .c (metric_2 ), |
---|
3536 | .d (metric_3 ), |
---|
3537 | .sa (6'd0 ), |
---|
3538 | .sb (6'd1 ), |
---|
3539 | .sc (6'd2 ), |
---|
3540 | .sd (6'd3 ), |
---|
3541 | .state (state_0 ), |
---|
3542 | .max (max_0 ) |
---|
3543 | ) ; |
---|
3544 | |
---|
3545 | //============================== |
---|
3546 | // Get max metric |
---|
3547 | //============================== |
---|
3548 | max_metric #(M, K) max_metric_1 ( |
---|
3549 | .clk (clk ), |
---|
3550 | .a (metric_4 ), |
---|
3551 | .b (metric_5 ), |
---|
3552 | .c (metric_6 ), |
---|
3553 | .d (metric_7 ), |
---|
3554 | .sa (6'd4 ), |
---|
3555 | .sb (6'd5 ), |
---|
3556 | .sc (6'd6 ), |
---|
3557 | .sd (6'd7 ), |
---|
3558 | .state (state_1 ), |
---|
3559 | .max (max_1 ) |
---|
3560 | ) ; |
---|
3561 | |
---|
3562 | //============================== |
---|
3563 | // Get max metric |
---|
3564 | //============================== |
---|
3565 | max_metric #(M, K) max_metric_2 ( |
---|
3566 | .clk (clk ), |
---|
3567 | .a (metric_8 ), |
---|
3568 | .b (metric_9 ), |
---|
3569 | .c (metric_10 ), |
---|
3570 | .d (metric_11 ), |
---|
3571 | .sa (6'd8 ), |
---|
3572 | .sb (6'd9 ), |
---|
3573 | .sc (6'd10 ), |
---|
3574 | .sd (6'd11 ), |
---|
3575 | .state (state_2 ), |
---|
3576 | .max (max_2 ) |
---|
3577 | ) ; |
---|
3578 | |
---|
3579 | //============================== |
---|
3580 | // Get max metric |
---|
3581 | //============================== |
---|
3582 | max_metric #(M, K) max_metric_3 ( |
---|
3583 | .clk (clk ), |
---|
3584 | .a (metric_12 ), |
---|
3585 | .b (metric_13 ), |
---|
3586 | .c (metric_14 ), |
---|
3587 | .d (metric_15 ), |
---|
3588 | .sa (6'd12 ), |
---|
3589 | .sb (6'd13 ), |
---|
3590 | .sc (6'd14 ), |
---|
3591 | .sd (6'd15 ), |
---|
3592 | .state (state_3 ), |
---|
3593 | .max (max_3 ) |
---|
3594 | ) ; |
---|
3595 | |
---|
3596 | //============================== |
---|
3597 | // Get max metric |
---|
3598 | //============================== |
---|
3599 | max_metric #(M, K) max_metric_4 ( |
---|
3600 | .clk (clk ), |
---|
3601 | .a (metric_16 ), |
---|
3602 | .b (metric_17 ), |
---|
3603 | .c (metric_18 ), |
---|
3604 | .d (metric_19 ), |
---|
3605 | .sa (6'd16 ), |
---|
3606 | .sb (6'd17 ), |
---|
3607 | .sc (6'd18 ), |
---|
3608 | .sd (6'd19 ), |
---|
3609 | .state (state_4 ), |
---|
3610 | .max (max_4 ) |
---|
3611 | ) ; |
---|
3612 | |
---|
3613 | //============================== |
---|
3614 | // Get max metric |
---|
3615 | //============================== |
---|
3616 | max_metric #(M, K) max_metric_5 ( |
---|
3617 | .clk (clk ), |
---|
3618 | .a (metric_20 ), |
---|
3619 | .b (metric_21 ), |
---|
3620 | .c (metric_22 ), |
---|
3621 | .d (metric_23 ), |
---|
3622 | .sa (6'd20 ), |
---|
3623 | .sb (6'd21 ), |
---|
3624 | .sc (6'd22 ), |
---|
3625 | .sd (6'd23 ), |
---|
3626 | .state (state_5 ), |
---|
3627 | .max (max_5 ) |
---|
3628 | ) ; |
---|
3629 | |
---|
3630 | //============================== |
---|
3631 | // Get max metric |
---|
3632 | //============================== |
---|
3633 | max_metric #(M, K) max_metric_6 ( |
---|
3634 | .clk (clk ), |
---|
3635 | .a (metric_24 ), |
---|
3636 | .b (metric_25 ), |
---|
3637 | .c (metric_26 ), |
---|
3638 | .d (metric_27 ), |
---|
3639 | .sa (6'd24 ), |
---|
3640 | .sb (6'd25 ), |
---|
3641 | .sc (6'd26 ), |
---|
3642 | .sd (6'd27 ), |
---|
3643 | .state (state_6 ), |
---|
3644 | .max (max_6 ) |
---|
3645 | ) ; |
---|
3646 | |
---|
3647 | //============================== |
---|
3648 | // Get max metric |
---|
3649 | //============================== |
---|
3650 | max_metric #(M, K) max_metric_7 ( |
---|
3651 | .clk (clk ), |
---|
3652 | .a (metric_28 ), |
---|
3653 | .b (metric_29 ), |
---|
3654 | .c (metric_30 ), |
---|
3655 | .d (metric_31 ), |
---|
3656 | .sa (6'd28 ), |
---|
3657 | .sb (6'd29 ), |
---|
3658 | .sc (6'd30 ), |
---|
3659 | .sd (6'd31 ), |
---|
3660 | .state (state_7 ), |
---|
3661 | .max (max_7 ) |
---|
3662 | ) ; |
---|
3663 | |
---|
3664 | //============================== |
---|
3665 | // Get max metric |
---|
3666 | //============================== |
---|
3667 | max_metric #(M, K) max_metric_8 ( |
---|
3668 | .clk (clk ), |
---|
3669 | .a (metric_32 ), |
---|
3670 | .b (metric_33 ), |
---|
3671 | .c (metric_34 ), |
---|
3672 | .d (metric_35 ), |
---|
3673 | .sa (6'd32 ), |
---|
3674 | .sb (6'd33 ), |
---|
3675 | .sc (6'd34 ), |
---|
3676 | .sd (6'd35 ), |
---|
3677 | .state (state_8 ), |
---|
3678 | .max (max_8 ) |
---|
3679 | ) ; |
---|
3680 | |
---|
3681 | //============================== |
---|
3682 | // Get max metric |
---|
3683 | //============================== |
---|
3684 | max_metric #(M, K) max_metric_9 ( |
---|
3685 | .clk (clk ), |
---|
3686 | .a (metric_36 ), |
---|
3687 | .b (metric_37 ), |
---|
3688 | .c (metric_38 ), |
---|
3689 | .d (metric_39 ), |
---|
3690 | .sa (6'd36 ), |
---|
3691 | .sb (6'd37 ), |
---|
3692 | .sc (6'd38 ), |
---|
3693 | .sd (6'd39 ), |
---|
3694 | .state (state_9 ), |
---|
3695 | .max (max_9 ) |
---|
3696 | ) ; |
---|
3697 | |
---|
3698 | //============================== |
---|
3699 | // Get max metric |
---|
3700 | //============================== |
---|
3701 | max_metric #(M, K) max_metric_10 ( |
---|
3702 | .clk (clk ), |
---|
3703 | .a (metric_40 ), |
---|
3704 | .b (metric_41 ), |
---|
3705 | .c (metric_42 ), |
---|
3706 | .d (metric_43 ), |
---|
3707 | .sa (6'd40 ), |
---|
3708 | .sb (6'd41 ), |
---|
3709 | .sc (6'd42 ), |
---|
3710 | .sd (6'd43 ), |
---|
3711 | .state (state_10 ), |
---|
3712 | .max (max_10 ) |
---|
3713 | ) ; |
---|
3714 | |
---|
3715 | //============================== |
---|
3716 | // Get max metric |
---|
3717 | //============================== |
---|
3718 | max_metric #(M, K) max_metric_11 ( |
---|
3719 | .clk (clk ), |
---|
3720 | .a (metric_44 ), |
---|
3721 | .b (metric_45 ), |
---|
3722 | .c (metric_46 ), |
---|
3723 | .d (metric_47 ), |
---|
3724 | .sa (6'd44 ), |
---|
3725 | .sb (6'd45 ), |
---|
3726 | .sc (6'd46 ), |
---|
3727 | .sd (6'd47 ), |
---|
3728 | .state (state_11 ), |
---|
3729 | .max (max_11 ) |
---|
3730 | ) ; |
---|
3731 | |
---|
3732 | //============================== |
---|
3733 | // Get max metric |
---|
3734 | //============================== |
---|
3735 | max_metric #(M, K) max_metric_12 ( |
---|
3736 | .clk (clk ), |
---|
3737 | .a (metric_48 ), |
---|
3738 | .b (metric_49 ), |
---|
3739 | .c (metric_50 ), |
---|
3740 | .d (metric_51 ), |
---|
3741 | .sa (6'd48 ), |
---|
3742 | .sb (6'd49 ), |
---|
3743 | .sc (6'd50 ), |
---|
3744 | .sd (6'd51 ), |
---|
3745 | .state (state_12 ), |
---|
3746 | .max (max_12 ) |
---|
3747 | ) ; |
---|
3748 | |
---|
3749 | //============================== |
---|
3750 | // Get max metric |
---|
3751 | //============================== |
---|
3752 | max_metric #(M, K) max_metric_13 ( |
---|
3753 | .clk (clk ), |
---|
3754 | .a (metric_52 ), |
---|
3755 | .b (metric_53 ), |
---|
3756 | .c (metric_54 ), |
---|
3757 | .d (metric_55 ), |
---|
3758 | .sa (6'd52 ), |
---|
3759 | .sb (6'd53 ), |
---|
3760 | .sc (6'd54 ), |
---|
3761 | .sd (6'd55 ), |
---|
3762 | .state (state_13 ), |
---|
3763 | .max (max_13 ) |
---|
3764 | ) ; |
---|
3765 | |
---|
3766 | //============================== |
---|
3767 | // Get max metric |
---|
3768 | //============================== |
---|
3769 | max_metric #(M, K) max_metric_14 ( |
---|
3770 | .clk (clk ), |
---|
3771 | .a (metric_56 ), |
---|
3772 | .b (metric_57 ), |
---|
3773 | .c (metric_58 ), |
---|
3774 | .d (metric_59 ), |
---|
3775 | .sa (6'd56 ), |
---|
3776 | .sb (6'd57 ), |
---|
3777 | .sc (6'd58 ), |
---|
3778 | .sd (6'd59 ), |
---|
3779 | .state (state_14 ), |
---|
3780 | .max (max_14 ) |
---|
3781 | ) ; |
---|
3782 | |
---|
3783 | //============================== |
---|
3784 | // Get max metric |
---|
3785 | //============================== |
---|
3786 | max_metric #(M, K) max_metric_15 ( |
---|
3787 | .clk (clk ), |
---|
3788 | .a (metric_60 ), |
---|
3789 | .b (metric_61 ), |
---|
3790 | .c (metric_62 ), |
---|
3791 | .d (metric_63 ), |
---|
3792 | .sa (6'd60 ), |
---|
3793 | .sb (6'd61 ), |
---|
3794 | .sc (6'd62 ), |
---|
3795 | .sd (6'd63 ), |
---|
3796 | .state (state_15 ), |
---|
3797 | .max (max_15 ) |
---|
3798 | ) ; |
---|
3799 | |
---|
3800 | //============================== |
---|
3801 | // Get max metric |
---|
3802 | //============================== |
---|
3803 | max_metric #(M, K) max_metric_s1_0 ( |
---|
3804 | .clk (clk ), |
---|
3805 | .a (max_0 ), |
---|
3806 | .b (max_1 ), |
---|
3807 | .c (max_2 ), |
---|
3808 | .d (max_3 ), |
---|
3809 | .sa (state_0 ), |
---|
3810 | .sb (state_1 ), |
---|
3811 | .sc (state_2 ), |
---|
3812 | .sd (state_3 ), |
---|
3813 | .state (state_s1_0 ), |
---|
3814 | .max (max_s1_0 ) |
---|
3815 | ) ; |
---|
3816 | |
---|
3817 | //============================== |
---|
3818 | // Get max metric |
---|
3819 | //============================== |
---|
3820 | max_metric #(M, K) max_metric_s1_1 ( |
---|
3821 | .clk (clk ), |
---|
3822 | .a (max_4 ), |
---|
3823 | .b (max_5 ), |
---|
3824 | .c (max_6 ), |
---|
3825 | .d (max_7 ), |
---|
3826 | .sa (state_4 ), |
---|
3827 | .sb (state_5 ), |
---|
3828 | .sc (state_6 ), |
---|
3829 | .sd (state_7 ), |
---|
3830 | .state (state_s1_1 ), |
---|
3831 | .max (max_s1_1 ) |
---|
3832 | ) ; |
---|
3833 | |
---|
3834 | //============================== |
---|
3835 | // Get max metric |
---|
3836 | //============================== |
---|
3837 | max_metric #(M, K) max_metric_s1_2 ( |
---|
3838 | .clk (clk ), |
---|
3839 | .a (max_8 ), |
---|
3840 | .b (max_9 ), |
---|
3841 | .c (max_10 ), |
---|
3842 | .d (max_11 ), |
---|
3843 | .sa (state_8 ), |
---|
3844 | .sb (state_9 ), |
---|
3845 | .sc (state_10 ), |
---|
3846 | .sd (state_11 ), |
---|
3847 | .state (state_s1_2 ), |
---|
3848 | .max (max_s1_2 ) |
---|
3849 | ) ; |
---|
3850 | |
---|
3851 | //============================== |
---|
3852 | // Get max metric |
---|
3853 | //============================== |
---|
3854 | max_metric #(M, K) max_metric_s1_3 ( |
---|
3855 | .clk (clk ), |
---|
3856 | .a (max_12 ), |
---|
3857 | .b (max_13 ), |
---|
3858 | .c (max_14 ), |
---|
3859 | .d (max_15 ), |
---|
3860 | .sa (state_12 ), |
---|
3861 | .sb (state_13 ), |
---|
3862 | .sc (state_14 ), |
---|
3863 | .sd (state_15 ), |
---|
3864 | .state (state_s1_3 ), |
---|
3865 | .max (max_s1_3 ) |
---|
3866 | ) ; |
---|
3867 | |
---|
3868 | //============================== |
---|
3869 | // Get max metric |
---|
3870 | //============================== |
---|
3871 | max_metric_logic #(M, K) max_metric_s2_0 ( |
---|
3872 | .a (max_s1_0 ), |
---|
3873 | .b (max_s1_1 ), |
---|
3874 | .c (max_s1_2 ), |
---|
3875 | .d (max_s1_3 ), |
---|
3876 | .sa (state_s1_0 ), |
---|
3877 | .sb (state_s1_1 ), |
---|
3878 | .sc (state_s1_2 ), |
---|
3879 | .sd (state_s1_3 ), |
---|
3880 | .state (state_s2_0 ), |
---|
3881 | .max ( ) |
---|
3882 | ) ; |
---|
3883 | |
---|
3884 | assign init_state_i = state_s2_0 ; |
---|
3885 | |
---|
3886 | always @ (posedge clk or negedge nrst) |
---|
3887 | if(~nrst) |
---|
3888 | trace_state <= 0 ; |
---|
3889 | else |
---|
3890 | begin |
---|
3891 | if (trace_pos) |
---|
3892 | begin |
---|
3893 | if(zero_tail & trace2_s2) |
---|
3894 | trace_state <= 0 ; |
---|
3895 | else |
---|
3896 | trace_state <= init_state_i ; |
---|
3897 | end |
---|
3898 | else if (trace_en) |
---|
3899 | trace_state <= next_state ; |
---|
3900 | end |
---|
3901 | |
---|
3902 | assign trace_start_pos = trace_start_wptr ; |
---|
3903 | |
---|
3904 | assign trace_start_pos0 = trace_start_pos - trace_cnt ; |
---|
3905 | assign trace_start_pos1 = trace_start_pos - trace_cnt -1 ; |
---|
3906 | |
---|
3907 | assign cur_state0 = trace_state ; |
---|
3908 | |
---|
3909 | assign tran_all_0 = { |
---|
3910 | tran_state_63[trace_start_pos0], tran_state_62[trace_start_pos0], tran_state_61[trace_start_pos0], tran_state_60[trace_start_pos0], |
---|
3911 | tran_state_59[trace_start_pos0], tran_state_58[trace_start_pos0], tran_state_57[trace_start_pos0], tran_state_56[trace_start_pos0], |
---|
3912 | tran_state_55[trace_start_pos0], tran_state_54[trace_start_pos0], tran_state_53[trace_start_pos0], tran_state_52[trace_start_pos0], |
---|
3913 | tran_state_51[trace_start_pos0], tran_state_50[trace_start_pos0], tran_state_49[trace_start_pos0], tran_state_48[trace_start_pos0], |
---|
3914 | |
---|
3915 | tran_state_47[trace_start_pos0], tran_state_46[trace_start_pos0], tran_state_45[trace_start_pos0], tran_state_44[trace_start_pos0], |
---|
3916 | tran_state_43[trace_start_pos0], tran_state_42[trace_start_pos0], tran_state_41[trace_start_pos0], tran_state_40[trace_start_pos0], |
---|
3917 | tran_state_39[trace_start_pos0], tran_state_38[trace_start_pos0], tran_state_37[trace_start_pos0], tran_state_36[trace_start_pos0], |
---|
3918 | tran_state_35[trace_start_pos0], tran_state_34[trace_start_pos0], tran_state_33[trace_start_pos0], tran_state_32[trace_start_pos0], |
---|
3919 | |
---|
3920 | tran_state_31[trace_start_pos0], tran_state_30[trace_start_pos0], tran_state_29[trace_start_pos0], tran_state_28[trace_start_pos0], |
---|
3921 | tran_state_27[trace_start_pos0], tran_state_26[trace_start_pos0], tran_state_25[trace_start_pos0], tran_state_24[trace_start_pos0], |
---|
3922 | tran_state_23[trace_start_pos0], tran_state_22[trace_start_pos0], tran_state_21[trace_start_pos0], tran_state_20[trace_start_pos0], |
---|
3923 | tran_state_19[trace_start_pos0], tran_state_18[trace_start_pos0], tran_state_17[trace_start_pos0], tran_state_16[trace_start_pos0], |
---|
3924 | |
---|
3925 | tran_state_15[trace_start_pos0], tran_state_14[trace_start_pos0], tran_state_13[trace_start_pos0], tran_state_12[trace_start_pos0], |
---|
3926 | tran_state_11[trace_start_pos0], tran_state_10[trace_start_pos0], tran_state_9[trace_start_pos0], tran_state_8[trace_start_pos0], |
---|
3927 | tran_state_7[trace_start_pos0], tran_state_6[trace_start_pos0], tran_state_5[trace_start_pos0], tran_state_4[trace_start_pos0], |
---|
3928 | tran_state_3[trace_start_pos0], tran_state_2[trace_start_pos0], tran_state_1[trace_start_pos0], tran_state_0[trace_start_pos0]} ; |
---|
3929 | |
---|
3930 | assign tran_all_1 = { |
---|
3931 | tran_state_63[trace_start_pos1], tran_state_62[trace_start_pos1], tran_state_61[trace_start_pos1], tran_state_60[trace_start_pos1], |
---|
3932 | tran_state_59[trace_start_pos1], tran_state_58[trace_start_pos1], tran_state_57[trace_start_pos1], tran_state_56[trace_start_pos1], |
---|
3933 | tran_state_55[trace_start_pos1], tran_state_54[trace_start_pos1], tran_state_53[trace_start_pos1], tran_state_52[trace_start_pos1], |
---|
3934 | tran_state_51[trace_start_pos1], tran_state_50[trace_start_pos1], tran_state_49[trace_start_pos1], tran_state_48[trace_start_pos1], |
---|
3935 | |
---|
3936 | tran_state_47[trace_start_pos1], tran_state_46[trace_start_pos1], tran_state_45[trace_start_pos1], tran_state_44[trace_start_pos1], |
---|
3937 | tran_state_43[trace_start_pos1], tran_state_42[trace_start_pos1], tran_state_41[trace_start_pos1], tran_state_40[trace_start_pos1], |
---|
3938 | tran_state_39[trace_start_pos1], tran_state_38[trace_start_pos1], tran_state_37[trace_start_pos1], tran_state_36[trace_start_pos1], |
---|
3939 | tran_state_35[trace_start_pos1], tran_state_34[trace_start_pos1], tran_state_33[trace_start_pos1], tran_state_32[trace_start_pos1], |
---|
3940 | |
---|
3941 | tran_state_31[trace_start_pos1], tran_state_30[trace_start_pos1], tran_state_29[trace_start_pos1], tran_state_28[trace_start_pos1], |
---|
3942 | tran_state_27[trace_start_pos1], tran_state_26[trace_start_pos1], tran_state_25[trace_start_pos1], tran_state_24[trace_start_pos1], |
---|
3943 | tran_state_23[trace_start_pos1], tran_state_22[trace_start_pos1], tran_state_21[trace_start_pos1], tran_state_20[trace_start_pos1], |
---|
3944 | tran_state_19[trace_start_pos1], tran_state_18[trace_start_pos1], tran_state_17[trace_start_pos1], tran_state_16[trace_start_pos1], |
---|
3945 | |
---|
3946 | tran_state_15[trace_start_pos1], tran_state_14[trace_start_pos1], tran_state_13[trace_start_pos1], tran_state_12[trace_start_pos1], |
---|
3947 | tran_state_11[trace_start_pos1], tran_state_10[trace_start_pos1], tran_state_9[trace_start_pos1], tran_state_8[trace_start_pos1], |
---|
3948 | tran_state_7[trace_start_pos1], tran_state_6[trace_start_pos1], tran_state_5[trace_start_pos1], tran_state_4[trace_start_pos1], |
---|
3949 | tran_state_3[trace_start_pos1], tran_state_2[trace_start_pos1], tran_state_1[trace_start_pos1], tran_state_0[trace_start_pos1]} ; |
---|
3950 | |
---|
3951 | |
---|
3952 | assign cur_state1 = get_next_trace_state (cur_state0, tran_all_0) ; |
---|
3953 | assign next_state = get_next_trace_state (cur_state1, tran_all_1) ; |
---|
3954 | |
---|
3955 | assign state0_bit = cur_state0 [K -2] ; |
---|
3956 | assign state1_bit = cur_state1 [K -2] ; |
---|
3957 | |
---|
3958 | always @ (posedge clk or negedge nrst) |
---|
3959 | if(~nrst) |
---|
3960 | res <= 0 ; |
---|
3961 | else |
---|
3962 | begin |
---|
3963 | if (trace_pos) |
---|
3964 | res <= 0 ; |
---|
3965 | else if (trace_en) |
---|
3966 | begin |
---|
3967 | res <= {state1_bit, state0_bit, res [L-1:2]} ; |
---|
3968 | end |
---|
3969 | end |
---|
3970 | |
---|
3971 | //====================================== |
---|
3972 | // function: get_next_trace_state |
---|
3973 | //====================================== |
---|
3974 | function [K-2:0] get_next_trace_state ; |
---|
3975 | input [K-2:0] cur_state_in ; |
---|
3976 | input [N -1:0] tran_state_in ; |
---|
3977 | reg [N -1:0] tmp ; |
---|
3978 | begin |
---|
3979 | tmp = tran_state_in >> cur_state_in ; |
---|
3980 | get_next_trace_state = {cur_state_in [K-3:0], tmp[0]} ; |
---|
3981 | end |
---|
3982 | endfunction |
---|
3983 | |
---|
3984 | endmodule |
---|
3985 | |
---|
3986 | |
---|