1 | |
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2 | function fec_decoder_simOnly_config(this_block) |
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3 | |
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4 | % Revision History: |
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5 | % |
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6 | % 20-Apr-2012 (12:19 hours): |
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7 | % Original code was machine generated by Xilinx's System Generator after parsing |
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8 | % C:\work\PHY\MIMO_OFDM\sysgen13p4\fec_decoder_simOnly.v |
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9 | % |
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10 | % |
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11 | |
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12 | this_block.setTopLevelLanguage('Verilog'); |
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13 | |
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14 | this_block.setEntityName('fec_decoder_simOnly'); |
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15 | |
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16 | % System Generator has to assume that your entity has a combinational feed through; |
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17 | % if it doesn't, then comment out the following line: |
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18 | this_block.tagAsCombinational; |
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19 | |
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20 | this_block.addSimulinkInport('nrst'); |
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21 | this_block.addSimulinkInport('fec_reg'); |
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22 | this_block.addSimulinkInport('start'); |
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23 | this_block.addSimulinkInport('vin'); |
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24 | this_block.addSimulinkInport('xk_index'); |
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25 | this_block.addSimulinkInport('mod_level'); |
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26 | this_block.addSimulinkInport('rx_i'); |
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27 | this_block.addSimulinkInport('rx_q'); |
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28 | |
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29 | this_block.addSimulinkOutport('rx_we'); |
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30 | this_block.addSimulinkOutport('rx_addr'); |
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31 | this_block.addSimulinkOutport('rx_data'); |
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32 | this_block.addSimulinkOutport('rx_done'); |
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33 | this_block.addSimulinkOutport('rx_we_2'); |
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34 | this_block.addSimulinkOutport('rx_addr_2'); |
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35 | this_block.addSimulinkOutport('rx_data_2'); |
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36 | this_block.addSimulinkOutport('rx_done_2'); |
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37 | |
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38 | rx_we_port = this_block.port('rx_we'); |
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39 | rx_we_port.setType('UFix_1_0'); |
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40 | rx_we_port.useHDLVector(false); |
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41 | rx_addr_port = this_block.port('rx_addr'); |
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42 | rx_addr_port.setType('UFix_14_0'); |
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43 | rx_data_port = this_block.port('rx_data'); |
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44 | rx_data_port.setType('UFix_8_0'); |
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45 | rx_done_port = this_block.port('rx_done'); |
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46 | rx_done_port.setType('UFix_1_0'); |
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47 | rx_done_port.useHDLVector(false); |
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48 | rx_we_2_port = this_block.port('rx_we_2'); |
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49 | rx_we_2_port.setType('UFix_1_0'); |
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50 | rx_we_2_port.useHDLVector(false); |
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51 | rx_addr_2_port = this_block.port('rx_addr_2'); |
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52 | rx_addr_2_port.setType('UFix_14_0'); |
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53 | rx_data_2_port = this_block.port('rx_data_2'); |
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54 | rx_data_2_port.setType('UFix_8_0'); |
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55 | rx_done_2_port = this_block.port('rx_done_2'); |
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56 | rx_done_2_port.setType('UFix_1_0'); |
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57 | rx_done_2_port.useHDLVector(false); |
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58 | |
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59 | % ----------------------------- |
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60 | if (this_block.inputTypesKnown) |
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61 | % do input type checking, dynamic output type and generic setup in this code block. |
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62 | |
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63 | if (this_block.port('nrst').width ~= 1); |
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64 | this_block.setError('Input data type for port "nrst" must have width=1.'); |
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65 | end |
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66 | |
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67 | this_block.port('nrst').useHDLVector(false); |
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68 | |
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69 | if (this_block.port('fec_reg').width ~= 32); |
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70 | this_block.setError('Input data type for port "fec_reg" must have width=32.'); |
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71 | end |
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72 | |
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73 | if (this_block.port('start').width ~= 1); |
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74 | this_block.setError('Input data type for port "start" must have width=1.'); |
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75 | end |
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76 | |
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77 | this_block.port('start').useHDLVector(false); |
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78 | |
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79 | if (this_block.port('vin').width ~= 1); |
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80 | this_block.setError('Input data type for port "vin" must have width=1.'); |
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81 | end |
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82 | |
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83 | this_block.port('vin').useHDLVector(false); |
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84 | |
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85 | if (this_block.port('xk_index').width ~= 6); |
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86 | this_block.setError('Input data type for port "xk_index" must have width=6.'); |
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87 | end |
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88 | |
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89 | if (this_block.port('mod_level').width ~= 4); |
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90 | this_block.setError('Input data type for port "mod_level" must have width=4.'); |
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91 | end |
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92 | |
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93 | if (this_block.port('rx_i').width ~= 16); |
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94 | this_block.setError('Input data type for port "rx_i" must have width=16.'); |
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95 | end |
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96 | |
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97 | if (this_block.port('rx_q').width ~= 16); |
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98 | this_block.setError('Input data type for port "rx_q" must have width=16.'); |
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99 | end |
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100 | |
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101 | end % if(inputTypesKnown) |
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102 | % ----------------------------- |
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103 | |
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104 | % ----------------------------- |
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105 | if (this_block.inputRatesKnown) |
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106 | setup_as_single_rate(this_block,'clk','ce') |
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107 | end % if(inputRatesKnown) |
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108 | % ----------------------------- |
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109 | |
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110 | % (!) Set the inout port rate to be the same as the first input |
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111 | % rate. Change the following code if this is untrue. |
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112 | uniqueInputRates = unique(this_block.getInputRates); |
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113 | |
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114 | |
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115 | % Add addtional source files as needed. |
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116 | % |------------- |
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117 | % | Add files in the order in which they should be compiled. |
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118 | % | If two files "a.vhd" and "b.vhd" contain the entities |
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119 | % | entity_a and entity_b, and entity_a contains a |
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120 | % | component of type entity_b, the correct sequence of |
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121 | % | addFile() calls would be: |
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122 | % | this_block.addFile('b.vhd'); |
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123 | % | this_block.addFile('a.vhd'); |
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124 | % |------------- |
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125 | |
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126 | % this_block.addFile(''); |
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127 | % this_block.addFile(''); |
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128 | this_block.addFile('fec_decoder_simOnly.v'); |
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129 | % this_block.addFile('fec_decoder_rest.v'); |
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130 | return; |
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131 | |
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132 | |
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133 | % ------------------------------------------------------------ |
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134 | |
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135 | function setup_as_single_rate(block,clkname,cename) |
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136 | inputRates = block.inputRates; |
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137 | uniqueInputRates = unique(inputRates); |
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138 | if (length(uniqueInputRates)==1 & uniqueInputRates(1)==Inf) |
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139 | block.addError('The inputs to this block cannot all be constant.'); |
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140 | return; |
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141 | end |
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142 | if (uniqueInputRates(end) == Inf) |
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143 | hasConstantInput = true; |
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144 | uniqueInputRates = uniqueInputRates(1:end-1); |
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145 | end |
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146 | if (length(uniqueInputRates) ~= 1) |
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147 | block.addError('The inputs to this block must run at a single rate.'); |
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148 | return; |
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149 | end |
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150 | theInputRate = uniqueInputRates(1); |
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151 | for i = 1:block.numSimulinkOutports |
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152 | block.outport(i).setRate(theInputRate); |
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153 | end |
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154 | block.addClkCEPair(clkname,cename,theInputRate); |
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155 | return; |
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156 | |
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157 | % ------------------------------------------------------------ |
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158 | |
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