source: ResearchApps/PHY/WARPLAB/WARPLab7/Sysgen_Reference/w3/warplab_trigger_proc/trig_idelays_config.m

Last change on this file was 4830, checked in by welsh, 7 years ago

Version 1.07.g - Output delays are now 16 bit for all outputs. Moved trigger input enables to register in IOB.

File size: 4.1 KB
Line 
1
2function trig_idelays_config(this_block)
3
4  % Revision History:
5  %
6  %   22-Oct-2015  (17:07 hours):
7  %     Original code was machine generated by Xilinx's System Generator after parsing
8  %     C:\work\svn_work\WARP\ResearchApps\PHY\WARPLAB\WARPLab7\Sysgen_Reference\w3\warplab_trigger_proc\trig_idelays.v
9  %
10  %
11
12  this_block.setTopLevelLanguage('Verilog');
13
14  this_block.setEntityName('trig_idelays');
15
16  % System Generator has to assume that your entity  has a combinational feed through;
17  %   if it  doesn't, then comment out the following line:
18  this_block.tagAsCombinational;
19
20  this_block.addSimulinkInport('trigs_disable');
21  this_block.addSimulinkInport('trigs_in_pin');
22  this_block.addSimulinkInport('trig0_dly');
23  this_block.addSimulinkInport('trig1_dly');
24  this_block.addSimulinkInport('trig2_dly');
25  this_block.addSimulinkInport('trig3_dly');
26  this_block.addSimulinkInport('update_delays');
27
28  this_block.addSimulinkOutport('trigs_in_delayed');
29
30  trigs_in_delayed_port = this_block.port('trigs_in_delayed');
31  trigs_in_delayed_port.setType('UFix_4_0');
32
33  % -----------------------------
34  if (this_block.inputTypesKnown)
35    % do input type checking, dynamic output type and generic setup in this code block.
36
37    if (this_block.port('trigs_disable').width ~= 4);
38      this_block.setError('Input data type for port "trigs_disable" must have width=1.');
39    end
40
41    if (this_block.port('trigs_in_pin').width ~= 4);
42      this_block.setError('Input data type for port "trigs_in_pin" must have width=4.');
43    end
44
45    if (this_block.port('trig0_dly').width ~= 5);
46      this_block.setError('Input data type for port "trig0_dly" must have width=5.');
47    end
48
49    if (this_block.port('trig1_dly').width ~= 5);
50      this_block.setError('Input data type for port "trig1_dly" must have width=5.');
51    end
52
53    if (this_block.port('trig2_dly').width ~= 5);
54      this_block.setError('Input data type for port "trig2_dly" must have width=5.');
55    end
56
57    if (this_block.port('trig3_dly').width ~= 5);
58      this_block.setError('Input data type for port "trig3_dly" must have width=5.');
59    end
60
61    if (this_block.port('update_delays').width ~= 1);
62      this_block.setError('Input data type for port "update_delays" must have width=1.');
63    end
64
65    this_block.port('update_delays').useHDLVector(false);
66
67  end  % if(inputTypesKnown)
68  % -----------------------------
69
70  % -----------------------------
71   if (this_block.inputRatesKnown)
72     setup_as_single_rate(this_block,'clk','ce')
73   end  % if(inputRatesKnown)
74  % -----------------------------
75
76    % (!) Set the inout port rate to be the same as the first input
77    %     rate. Change the following code if this is untrue.
78    uniqueInputRates = unique(this_block.getInputRates);
79
80
81  % Add addtional source files as needed.
82  %  |-------------
83  %  | Add files in the order in which they should be compiled.
84  %  | If two files "a.vhd" and "b.vhd" contain the entities
85  %  | entity_a and entity_b, and entity_a contains a
86  %  | component of type entity_b, the correct sequence of
87  %  | addFile() calls would be:
88  %  |    this_block.addFile('b.vhd');
89  %  |    this_block.addFile('a.vhd');
90  %  |-------------
91
92  %    this_block.addFile('');
93  %    this_block.addFile('');
94  this_block.addFile('trig_idelay.v');
95  this_block.addFile('trig_idelays.v');
96
97return;
98
99
100% ------------------------------------------------------------
101
102function setup_as_single_rate(block,clkname,cename) 
103  inputRates = block.inputRates; 
104  uniqueInputRates = unique(inputRates); 
105  if (length(uniqueInputRates)==1 & uniqueInputRates(1)==Inf) 
106    block.addError('The inputs to this block cannot all be constant.'); 
107    return; 
108  end 
109  if (uniqueInputRates(end) == Inf) 
110     hasConstantInput = true; 
111     uniqueInputRates = uniqueInputRates(1:end-1); 
112  end 
113  if (length(uniqueInputRates) ~= 1) 
114    block.addError('The inputs to this block must run at a single rate.'); 
115    return; 
116  end 
117  theInputRate = uniqueInputRates(1); 
118  for i = 1:block.numSimulinkOutports
119     block.outport(i).setRate(theInputRate); 
120  end 
121  block.addClkCEPair(clkname,cename,theInputRate); 
122  return; 
123
124% ------------------------------------------------------------
125
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