[4747] | 1 | |
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| 2 | function trig_idelays_config(this_block) |
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| 3 | |
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| 4 | % Revision History: |
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| 5 | % |
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| 6 | % 22-Oct-2015 (17:07 hours): |
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| 7 | % Original code was machine generated by Xilinx's System Generator after parsing |
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| 8 | % C:\work\svn_work\WARP\ResearchApps\PHY\WARPLAB\WARPLab7\Sysgen_Reference\w3\warplab_trigger_proc\trig_idelays.v |
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| 9 | % |
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| 10 | % |
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| 11 | |
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| 12 | this_block.setTopLevelLanguage('Verilog'); |
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| 13 | |
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| 14 | this_block.setEntityName('trig_idelays'); |
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| 15 | |
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| 16 | % System Generator has to assume that your entity has a combinational feed through; |
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| 17 | % if it doesn't, then comment out the following line: |
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| 18 | this_block.tagAsCombinational; |
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| 19 | |
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[4830] | 20 | this_block.addSimulinkInport('trigs_disable'); |
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[4747] | 21 | this_block.addSimulinkInport('trigs_in_pin'); |
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| 22 | this_block.addSimulinkInport('trig0_dly'); |
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| 23 | this_block.addSimulinkInport('trig1_dly'); |
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| 24 | this_block.addSimulinkInport('trig2_dly'); |
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| 25 | this_block.addSimulinkInport('trig3_dly'); |
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| 26 | this_block.addSimulinkInport('update_delays'); |
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| 27 | |
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| 28 | this_block.addSimulinkOutport('trigs_in_delayed'); |
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| 29 | |
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| 30 | trigs_in_delayed_port = this_block.port('trigs_in_delayed'); |
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| 31 | trigs_in_delayed_port.setType('UFix_4_0'); |
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| 32 | |
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| 33 | % ----------------------------- |
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| 34 | if (this_block.inputTypesKnown) |
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| 35 | % do input type checking, dynamic output type and generic setup in this code block. |
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| 36 | |
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[4830] | 37 | if (this_block.port('trigs_disable').width ~= 4); |
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| 38 | this_block.setError('Input data type for port "trigs_disable" must have width=1.'); |
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| 39 | end |
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| 40 | |
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[4747] | 41 | if (this_block.port('trigs_in_pin').width ~= 4); |
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| 42 | this_block.setError('Input data type for port "trigs_in_pin" must have width=4.'); |
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| 43 | end |
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| 44 | |
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| 45 | if (this_block.port('trig0_dly').width ~= 5); |
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| 46 | this_block.setError('Input data type for port "trig0_dly" must have width=5.'); |
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| 47 | end |
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| 48 | |
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| 49 | if (this_block.port('trig1_dly').width ~= 5); |
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| 50 | this_block.setError('Input data type for port "trig1_dly" must have width=5.'); |
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| 51 | end |
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| 52 | |
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| 53 | if (this_block.port('trig2_dly').width ~= 5); |
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| 54 | this_block.setError('Input data type for port "trig2_dly" must have width=5.'); |
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| 55 | end |
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| 56 | |
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| 57 | if (this_block.port('trig3_dly').width ~= 5); |
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| 58 | this_block.setError('Input data type for port "trig3_dly" must have width=5.'); |
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| 59 | end |
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| 60 | |
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| 61 | if (this_block.port('update_delays').width ~= 1); |
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| 62 | this_block.setError('Input data type for port "update_delays" must have width=1.'); |
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| 63 | end |
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| 64 | |
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| 65 | this_block.port('update_delays').useHDLVector(false); |
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| 66 | |
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| 67 | end % if(inputTypesKnown) |
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| 68 | % ----------------------------- |
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| 69 | |
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| 70 | % ----------------------------- |
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| 71 | if (this_block.inputRatesKnown) |
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| 72 | setup_as_single_rate(this_block,'clk','ce') |
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| 73 | end % if(inputRatesKnown) |
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| 74 | % ----------------------------- |
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| 75 | |
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| 76 | % (!) Set the inout port rate to be the same as the first input |
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| 77 | % rate. Change the following code if this is untrue. |
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| 78 | uniqueInputRates = unique(this_block.getInputRates); |
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| 79 | |
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| 80 | |
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| 81 | % Add addtional source files as needed. |
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| 82 | % |------------- |
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| 83 | % | Add files in the order in which they should be compiled. |
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| 84 | % | If two files "a.vhd" and "b.vhd" contain the entities |
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| 85 | % | entity_a and entity_b, and entity_a contains a |
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| 86 | % | component of type entity_b, the correct sequence of |
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| 87 | % | addFile() calls would be: |
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| 88 | % | this_block.addFile('b.vhd'); |
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| 89 | % | this_block.addFile('a.vhd'); |
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| 90 | % |------------- |
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| 91 | |
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| 92 | % this_block.addFile(''); |
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| 93 | % this_block.addFile(''); |
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| 94 | this_block.addFile('trig_idelay.v'); |
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| 95 | this_block.addFile('trig_idelays.v'); |
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| 96 | |
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| 97 | return; |
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| 98 | |
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| 99 | |
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| 100 | % ------------------------------------------------------------ |
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| 101 | |
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| 102 | function setup_as_single_rate(block,clkname,cename) |
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| 103 | inputRates = block.inputRates; |
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| 104 | uniqueInputRates = unique(inputRates); |
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| 105 | if (length(uniqueInputRates)==1 & uniqueInputRates(1)==Inf) |
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| 106 | block.addError('The inputs to this block cannot all be constant.'); |
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| 107 | return; |
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| 108 | end |
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| 109 | if (uniqueInputRates(end) == Inf) |
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| 110 | hasConstantInput = true; |
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| 111 | uniqueInputRates = uniqueInputRates(1:end-1); |
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| 112 | end |
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| 113 | if (length(uniqueInputRates) ~= 1) |
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| 114 | block.addError('The inputs to this block must run at a single rate.'); |
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| 115 | return; |
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| 116 | end |
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| 117 | theInputRate = uniqueInputRates(1); |
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| 118 | for i = 1:block.numSimulinkOutports |
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| 119 | block.outport(i).setRate(theInputRate); |
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| 120 | end |
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| 121 | block.addClkCEPair(clkname,cename,theInputRate); |
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| 122 | return; |
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| 123 | |
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| 124 | % ------------------------------------------------------------ |
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| 125 | |
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