Changes between Version 5 and Version 6 of 802.11/wlan_exp/app_notes/four_radio
- Timestamp:
- Apr 13, 2016, 2:59:20 PM (8 years ago)
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802.11/wlan_exp/app_notes/four_radio
v5 v6 1 = Adding 4 antenna support=2 '''WORK IN PROGRESS''' 1 = Modifying the 802.11 Reference Design for 4 Radios = 2 The 802.11 Reference Design Tx and Rx PHY cores implement ports for 4 RF interfaces. The reference hardware project only connects RF A and RF B in order to maintain compatibility with WARP v3 nodes using third-party FMC modules. In order to use the reference design with 4 RF interfaces (2 WARP v3 on-board, 2 on FMC-RF-2X245 module) the following changes must be made to the XPS project's {{{system.mhs}}} and {{{data/system.ucf}}} files. The changes below are based on 802.11 Reference Design v1.5. 3 3 4 4 == MHS Changes == 5 6 The changes below apply to the XPS project's {{{system.mhs}}} file. 5 7 6 8 Add new top-level ports: … … 75 77 Add new instances of {{{w3_ad_bridge}}} and {{{w3_iic_eeprom_axi}}} cores: 76 78 {{{#!sh 79 # samp_ce unused in FMC ad_bridge; on-board ad_bridge drives PHY's ce ports 77 80 BEGIN w3_ad_bridge 78 81 PARAMETER INSTANCE = ad_bridge_FMC 79 PARAMETER HW_VER = 3.0 1.e82 PARAMETER HW_VER = 3.03.a 80 83 # Clock ports (inputs to w3_ad_bridge) 81 PORT sys_samp_clk_Tx = clk_20MHz 82 PORT sys_samp_clk_Tx_90 = clk_20MHz_90degphase 83 PORT sys_samp_clk_Rx = clk_20MHz 84 PORT sys_clk = clk_160MHz 84 85 PORT ad_TXCLK_out_en = RF_AD_TXCLK_out_en 85 86 # Top-level AD9963 ports … … 108 109 BEGIN w3_iic_eeprom_axi 109 110 PARAMETER INSTANCE = w3_iic_eeprom_FMC 110 PARAMETER HW_VER = 1.0 0.b111 PARAMETER C_BASEADDR = 0x 70410000112 PARAMETER C_HIGHADDR = 0x 7041ffff111 PARAMETER HW_VER = 1.02.a 112 PARAMETER C_BASEADDR = 0x82010000 113 PARAMETER C_HIGHADDR = 0x8201FFFF 113 114 PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 7 114 115 PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 7 … … 116 117 PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 7 117 118 PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 7 118 BUS_INTERFACE S_AXI = mb_ low_axi_periph119 BUS_INTERFACE S_AXI = mb_shared_axi_periph 119 120 PORT S_AXI_ACLK = clk_160MHz 120 PORT iic_scl 121 PORT iic_sda 121 PORT iic_scl_io= iic_eeprom_fmc_scl_pin 122 PORT iic_sda_io= iic_eeprom_fmc_sda_pin 122 123 END 123 124 }}} … … 173 174 }}} 174 175 175 Add parameter and port connections to {{{w3_ad_controller_axi}}} instance:176 Add parameter and port connections to the existing {{{w3_ad_controller_axi}}} instance: 176 177 {{{#!sh 177 178 BEGIN w3_ad_controller_axi … … 192 193 193 194 194 Add port connections to {{{wlan_mac_dcf_hw_axiw}}} core:195 {{{#!sh 196 BEGIN wlan_mac_ dcf_hw_axiw195 Add port connections to the existing {{{wlan_mac_hw}}} instance: 196 {{{#!sh 197 BEGIN wlan_mac_hw 197 198 ... 198 199 PORT phy_tx_gain_c = mac_phy_tx_gain_c … … 202 203 }}} 203 204 204 Add port connections to {{{wlan_phy_tx_pmd_axiw}}} core:205 Add port connections to the existing {{{wlan_phy_tx_pmd_axiw}}} instance: 205 206 206 207 {{{#!sh … … 224 225 }}} 225 226 226 Add port connections to {{{wlan_phy_rx_pmd_axiw}}} core:227 Add port connections to the existing {{{wlan_phy_rx_pmd_axiw}}} instance: 227 228 {{{#!sh 228 229 BEGIN wlan_phy_rx_pmd_axiw … … 244 245 }}} 245 246 246 Add port connections to {{{wlan_agc_axiw}}} core:247 Add port connections to the existing {{{wlan_agc_axiw}}} instance: 247 248 {{{#!sh 248 249 BEGIN wlan_agc_axiw … … 273 274 == UCF Changes == 274 275 275 Add LOC and timing constraints for FMC-RF-2X245 signals :276 Add LOC and timing constraints for FMC-RF-2X245 signals to {{{data/system.ucf}}}: 276 277 277 278 {{{#!sh … … 446 447 447 448 #Timing 449 #AD9963 data interface clock constraints 448 450 Net RFC_AD_TRXCLK TNM_NET = TNM_RFC_AD_TRXCLK; 449 451 Net RFD_AD_TRXCLK TNM_NET = TNM_RFD_AD_TRXCLK; 450 452 451 #TRXCLK runs at 20MHz (using decimation in AD9963s) 452 TIMESPEC TS_RFC_AD_TRXCLK = PERIOD TNM_RFC_AD_TRXCLK TS_samp_clk_pin*4; 453 TIMESPEC TS_RFD_AD_TRXCLK = PERIOD TNM_RFD_AD_TRXCLK TS_samp_clk_pin*4; 454 455 #TRXCLK -> clk20 is first stage of registers (IDDR -> 2xDFF) 456 TIMESPEC TS_RFC_TRX_TO_20M = FROM "TNM_RFC_AD_TRXCLK" to "TNM_clk_20MHz" 40ns; 457 TIMESPEC TS_RFD_TRX_TO_20M = FROM "TNM_RFD_AD_TRXCLK" to "TNM_clk_20MHz" 40ns; 458 459 #clk20 -> clk160 is paths from ad_bridge to sample-consuming PHY cores 460 TIMESPEC TS_RFC_20M_TO_160M = FROM "TNM_clk_20MHz" to "TNM_clk_160" 6.2ns; 461 TIMESPEC TS_RFD_20M_TO_160M = FROM "TNM_clk_20MHz" to "TNM_clk_160" 6.2ns; 462 463 453 #TRXCLK runs up to 40MHz (no decimation in AD9963s) 454 TIMESPEC TS_RFC_AD_TRXCLK = PERIOD TNM_RFC_AD_TRXCLK TS_samp_clk*2; 455 TIMESPEC TS_RFD_AD_TRXCLK = PERIOD TNM_RFD_AD_TRXCLK TS_samp_clk*2; 456 457 #Define relationship of TRXD and TRXCLK, based on AD9963 specs 458 # Using worst-case output delay from AD9963 datasheet table 23 459 # TRXCLK leads TRXD transition by t_OD2; ad_bridge uses IDELAY to shift this to mid valid window 460 # VALID window below assumes DDR interleaved I/Q at 20MSps rate (25nsec / half sample) 464 461 INST "RFC_AD_TRXD<*>" TNM = RFC_AD_TRXD_group; 465 462 NET "RFC_AD_TRXCLK" TNM_NET = RFC_AD_TRXCLK; … … 471 468 TIMEGRP "RFD_AD_TRXD_group" OFFSET = IN 0.7 ns VALID 22 ns BEFORE "RFD_AD_TRXCLK" RISING; 472 469 TIMEGRP "RFD_AD_TRXD_group" OFFSET = IN 0.7 ns VALID 22 ns BEFORE "RFD_AD_TRXCLK" FALLING; 473 474 #Mark TRX-samp_clk_rx paths as fully async, with short max route (use DFFs near ILOGIC.IDDRs) 475 INST "ad_bridge_FMC/ad_bridge_FMC/DDR_REGS_RFA_RFB[*].IDDR*" TNM = "AD_TRXCLK_IDDRS_FMC"; 476 INST "ad_bridge_FMC/ad_bridge_FMC/DDR_REGS_RFA_RFB[*].DFF2*" TNM = "AD_SYSCLK_FFS_FMC"; 477 478 TIMESPEC TS_async_rx_samp_clks_FMC_IN = FROM "AD_TRXCLK_IDDRS_FMC" TO "AD_SYSCLK_FFS_FMC" 2 ns DATAPATHONLY; 479 TIMESPEC TS_async_rx_samp_clks_FMC_OUT = FROM "AD_SYSCLK_FFS_FMC" TO "AD_TRXCLK_IDDRS_FMC" 2 ns DATAPATHONLY; 480 481 }}} 470 }}}
