| | 18 | In this exercise, we provide users with a custom peripheral core: the prng_useriosrc. This core is a pseudorandom number generator with ports that are meant to be connected to the User I/O core that is present in the template WARP design. The above figure describes is a simplified diagram of the final after adding the custom pcore. Inside the custom core there is a Linear Feedback Shift Register ([http://en.wikipedia.org/wiki/Linear_feedback_shift_register LFSR]) that produces a sequence of pseudorandom values. These values are then latched by a counter circuit to slow them down and make their changes visible to the naked eye when observing a board. The output of this latch is sliced up and connected to output ports on the core. All pcores have two distinct ways of getting information into and out of the peripheral: |
| | 19 | |
| | 20 | * Ports: Shown in yellow in the above figure, ports allow direct connectivity between peripherals. They can serve as inputs or outputs of the design. |
| | 21 | * Registers: Shown in red in the above figure, registers allow peripherals to be controlled by software running in a Microblaze soft processor. Registers allow the core to hang off a bus such as the Processor Local Bus (PLB) and allow custom C-code to read or write memory addresses to control the core. |
| | 22 | |
| | 23 | The prng_useriosrc pcore has the following inputs and outputs: |
| | 24 | |
| | 25 | === Inputs === |
| | 26 | |
| | 27 | === Outputs === |
