Introduction to the Xilinx Platform Studio (XPS)

(compatible with WARP v2 and WARP v3)

In this exercise, users will be introduced to the Xilinx Platform Studio (XPS). This tool is used by designers to build complete systems out of separate peripheral cores known as "pcores." In this exercise, user's will extend a provided template project by adding a custom pcore that implements a pseudorandom number generator (PRNG) directly in the FPGA. This core is then connected to the template project's User I/O core so it can drive random values out to LEDs and hexadecimal displays.

Prerequisites

• You have a WARP v2 or WARP v3 board
• ESD protection for the WARP board (wrist strap, etc)
• WARP v2: USB cable for programming and USB cable for UART
• WARP v3: External USB JTAG cable and a micro USB cable for UART
• Complete installation of ISE System Edition 13.4
• Checked out a local copy of the WARP Repository
• Set up a terminal on your computer using PuTTY or an alternative. Instructions to do this are available instructions here?.
• Familiarity with the Xilinx SDK. Make sure you have completed the Introduction to the SDK exercise.

Overview

In this exercise, we provide users with a custom peripheral core: the prng_useriosrc. This core is a pseudorandom number generator with ports that are meant to be connected to the User I/O core that is present in the template WARP design. The above figure describes is a simplified diagram of the final after adding the custom pcore. Inside the custom core there is a Linear Feedback Shift Register (​LFSR) that produces a sequence of pseudorandom values. These values are then latched by a counter circuit to slow them down and make their changes visible to the naked eye when observing a board. The output of this latch is sliced up and connected to output ports on the core. All pcores have two distinct ways of getting information into and out of the peripheral:

• Ports: Shown in yellow in the above figure, ports allow direct connectivity between peripherals. They can serve as inputs or outputs of the design.
• Registers: Shown in red in the above figure, registers allow peripherals to be controlled by software running in a Microblaze soft processor. Registers allow the core to hang off a bus such as the Processor Local Bus (PLB) and allow custom C-code to read or write memory addresses to control the core.

The prng_useriosrc pcore has the following inputs and outputs:

Inputs

• User I/O Pushbutton Port: This port is connected directly to the User I/O "up" pushbutton port. When the user presses the button on the board, the latch inside the prng_useriosrc core will stop updating the outputs. This will effectively "pause" the core and allow the user to read the current set of outputs from the LEDs and other display elements.
• Capture Period Register: This register attaches to the bus and allows C-code executing inside the MicroBlaze to control how often the latch on the LFSR triggers. In effect, this is a way for C-code to control how fast the output updates occur. Note: even though we have listed this as an input to the core, this register can also be read by the C-code in order to check and see what it had been set to.

Outputs

• Left/Right Hex Display Ports: The left and right hexadecimal displays contain seven individual on/off segments. These output ports drive 7-bit wide random numbers to the equivalent input ports on the User I/O core.
• Red/Green LED Ports: The banks of red and green LEDs each contain 4 elements. These 4-bit wide random numbers drive the equivalent input ports on the User I/O core.
• Captured Output Register: This register attaches to the bus and allows C-code executing inside the MicroBlaze to read the current latched output of the LFSR.

You will also notice in the diagram the green "FPGA Pins" ports. These are top-level ports that are routed out to physical pins on the FPGA. These pins are connected to other components on the WARP board. For the purpose of this exercise, we have provided this pcore as an example of a hardware peripheral you may want to integrate into your design. The Exporting pcores from System Generator? exercise covers how this pcore was created.

Instructions

1. Download either the WARP v3 Template Project or the WARP v2 Template Project? according to the which hardware you are using. Note: We recommend using the "lite" template for this exercise as it will build the quickest.
2. Extract the archive into a folder on your hard drive. Note: this folder must not contain any spaces in the path (this includes the the Windows desktop, as that lives in a folder known as "Documents and Settings").
3. Download the provided pcore​. Unzip the archive and place the "prng_useriosrc_plbw_v1_02_a" folder inside the "pcores" folder in the extracted template project.
4. Launch XPS from the Start menu. Click "Open project" and navigate to the system.xmp file from the template project. Click Open.
   • If this is the first time you have run XPS, you will receive a number of error messages saying that cores cannot be found. XPS must be told where to find the WARP SVN repository in order for it to find these files. In XPS, click Edit→Preferences. Then, under the "Application" category, click "Browse ..." under the "Global Peripheral Repository Search Path." Navigate to and select the "edk_user_repository" folder on your hard drive. If you do not have an "edk_user_respotory" SVN working copy, please see our SVN documentation. After making this selection, close and reopen XPS. This step of adding the global repository path only needs to be done once per installation of the Xilinx tools.
5. To connect the new pcore to the system, we will modify the Microprocessor Hardware Specification "system.mhs" You can find this file in the "Project" tab under "Project Files." Double-click this file to open it.

6. Add the following chunk of code to the bottom of the system.mhs file:

BEGIN prng_useriosrc_plbw
 PARAMETER INSTANCE = prng_useriosrc_plbw_0
 PARAMETER HW_VER = 1.02.a
 PARAMETER C_BASEADDR = 0xc4000000
 PARAMETER C_HIGHADDR = 0xc400ffff
 BUS_INTERFACE SPLB = plb_secondary_80MHz
 PORT sysgen_clk = clk_80MHz
 PORT hexdisp_left = LeftHexDisplay
 PORT hexdisp_right = RightHexDisplay
 PORT leds_green = GreenLEDs
 PORT leds_red = RedLEDs
 PORT pause = UpPushbutton
END

This chunk of code will instantiate the prng_useriosrc core in the design and attaches it to the bus (here, the plb_secondary_80MHz bus). Additionally, it attaches the input/output ports of core to some unique net names (LeftHexDisplay, RightHexDisplay, GreenLEDs, RedLEDs, and UpPushbutton). These net names are arbitrary; the important thing is that the names match on the corresponding ports to whatever the core is connected to.

7. Find the chunk of code that starts with "BEGIN w3_userio." Before the "END" line, add the following port connections:

 PORT usr_hexdisp_left = LeftHexDisplay
 PORT usr_hexdisp_right = RightHexDisplay
 PORT usr_leds_green = GreenLEDs
 PORT usr_leds_red = RedLEDs
 PORT usr_pb_u = UpPushbutton

This connects the ports from the prng_useriosrc_plbw to the appropriate ports on the User I/O core. Click File→Save. You will be asked if you want to reload the project; click "Reload." At this point, you may wonder how you are supposed to know the names of ports themselves. Unfortunately, ports that are floating (i.e. disconnected) do not show up in the system.mhs file. The best way to find a full list of all ports a pcore has is by looking at its entry in the "System Assembly View" tab. In the next step, we'll be looking at this view to verify that the prng_useriosrc pcore is correctly hooked up to the system.

8. Open the System Assembly View tab and make sure you are looking at the "Bus Interfaces" subtab. To the left of prng_useriosrc_plbw_0, you see a yellow circle connecting the core to the plb_secondary_80MHz bus. Unconnected pcores show an empty, white circle.

9. Next, click on the "Ports" subtab.

Testing the Design

WARP v3 Template Project - Lite
Board serial number: W3-a-00006

Running User I/O Example
                    Left Hex  -------------     -------------  Right Hex
                    Red LEDs  -------                 -------  Green LEDs
        PRNG Captured Value:  1 1 1 0 1 1 1 0 1 1 1 1 0 1 0 0

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