Changes between Version 9 and Version 10 of FAQ/Hardware

Timestamp:

Jan 27, 2007, 8:52:26 PM (17 years ago)

Author:

murphpo

Comment:

--

FAQ/Hardware

@@ -34 +34 @@
 
  1. Locate the 14-pin programming header (component J51) on the back of the FPGA board that is labaled 'CPLD'. Of the two programming headers, this one is nearer the center of the board.
- 1. Connect the programming cable's JTAG header to the header.
+ 1. Connect the programming cable's JTAG cable to this header.
  1. Run Xilinx iMPACT (Start->Programs->Xilinx ISE->Accessories->iMPACT)
- 1. Initialize the boundary-scan chain
- 1. Right-click on the CPLD (probably displaed as part XC2C256) and choose Erase.
+ 1. Initialize the boundary-scan chain. A single CPLD device should be located.
+ 1. Right-click on the CPLD (probably labeled XC2C256) and choose Erase.
 
-iMPACT should then display a blue notice that the erasing process was successful. If so, the USB circuit is now bypassed and the FPGA can be configured by its JTAG header (J49). The USB circuit will be automatically re-enabled the next time it is used in iMPACT.
+iMPACT should then display a blue notice that the erasing process was successful. If so, the USB circuit is now bypassed and the FPGA can be configured by its own JTAG header (J49). The USB circuit will be automatically re-enabled the next time it is used in iMPACT.