Changes between Version 6 and Version 7 of FAQ/Hardware


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Timestamp:
Jan 27, 2007, 8:46:23 PM (17 years ago)
Author:
murphpo
Comment:

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  • FAQ/Hardware

    v6 v7  
    2121We suggest using 56700 bps; we have observed problems interacting with some PCs at the maximum speed of 115200 bps.
    2222----
     23== Why can't I configure the FPGA using the JTAG connector on the board? ==
     24The WARP FPGA board supports downloading bitstreams by two methods.
     25
     26The recommended method is to use the built-in USB programming capability on the WARP FPGA Board. Simply connect a USB cable to the USB port on the bottom of the board (component J52). The first time you connect this to your PC, Windows will install the appropriate drivers. This process usually takes a few minutes. Wait until Windows notifies you that "Your new hardware is installed and ready for use" before trying to configure the FPGA. Once the drivers are installed, any Xilinx configuration tool (iMPACT, ChipScope, XPS) will see a standard JTAG cable attached to your PC.
     27
     28The alternate method is to use a Xilinx programming cable like the [http://www.xilinx.com/onlinestore/program_solutions.htm Parallel IV or Platform USB] cables. These cables connect to the standard 14-pin programming header on the FPGA board. The header is labeled 'SysACE' and is component J49. If your FPGA board has previously been configured via the USB port, this connector will *not* work until you disable the USB port. Follow the directions below to accomplish this.
     29
     30== How do I bypass the USB configuration interface? ==
     31In some cases, it is necessary to bypass the WARP FPGA board's built-in USB configuration circuit. You will need an external Xilinx programming cable to do this.
     32
     33 1. Locate the 14-pin programming header on the back of the FPGA board that is labaled 'CPLD'. Of the two programming headers, this one is nearer the center of the board.
     34 1. Connect the programming cable's JTAG header to the header.
     35 1. Run Xilinx iMPACT (Start->Programs->Xilinx ISE->Accessories->iMPACT)
     36 1. Initialize the boundary-scan chain
     37 1. Right-click on the CPLD (probably displaed as part XC2C256) and choose Erase.
     38
     39iMPACT should then display a blue notice that the erasing process was successful. If so, the USB circuit is now bypassed and the FPGA can be configured by its JTAG header (J49). The USB circuit will be automatically re-enabled the next time it is used in iMPACT.