Changes between Version 10 and Version 11 of GettingStarted/WARPv3/IntroToTools

Timestamp:

Aug 13, 2012, 2:59:58 PM (12 years ago)

Author:

murphpo

Comment:

--

GettingStarted/WARPv3/IntroToTools

@@ -1 +1 @@
 [[TracNav(GettingStarted/WARPv3/TOC)]]
 
-= What do you want to do? =
+= WARP v3 Getting Started Exercises =
 
-WARP is used to study [wiki:PapersandPresentations a variety of different research areas]. The first steps to getting started using WARP depend on what you want to do.
+Developing custom applications on WARP requires using design tools from Xilinx. These tools are sophisticated (i.e. they're complicated) and can be daunting to a new user. We've created some simple exercises that introduce the core tools most WARP users will use.
 
 
+== Basic Design Structure ==
+All WARP reference designs are built using the Xilinx Embedded Development Kit (EDK). The EDK enables construction of designs with both a processor, for running custom software, and custom hardware cores for real-time processing and connecting to off-chip hardware.
 
-{{{#!th style="background: #eef"
-[#phy I want to study the physical layer]
-}}}
-{{{#!th style="background: #eef"
-[#mac I want to study the higher networking layers]
-}}}
+The EDK includes two primary tools:
+ * Xilinx Platform Studio (XPS): integrates the hardware cores for a design, including the MicroBlaze processor, memory, peripherals and interfaces for off-chip hardware
+ * Xilinx Software Development Kit (SDK): a full suite of software compilation and debugging tools for the MicroBlaze processor
 
+The basic structure of WARP reference designs is illustrated below.
+[[Image(GettingStarted/WARPv3/files:w3_EDK_Proj_BlkDiag.png, nolink)]]
 
-= I Want to Study the Physical Layer = #phy
+The MicroBlaze processor and connected cores are all implemented in the FPGA fabric using XPS. The output of the XPS flow is a "bitstream" with the fully synthesized and implemented hardware design. This bitstream integrates the MicroBlaze, the standard peripheral cores, your custom cores, I/O assignments, clock configurations and timing constraints. However the MicroBlaze instruction and data memories are blank in this bitstream.
 
-The FPGA on WARP provides the resources to implement a full, real-time physical layer. Typically, a physical layer is implemented as a periphal core (pcore) that attaches to a microprocessor core that executes C-code to control it. This C-code can, for example, implement a wireless MAC. We have provided two exercises that demonstrate how to control WARP from a microprocessor and how export a custom peripheral from Xiling System Generator.
+The XPS-generated bitstream (and its associated hardware specification) is the starting point for an SDK project. The SDK compiles custom code for the MicroBlaze, along with drivers for the various cores included in the XPS hardware design. The output of this process is an "elf" file, the software binary ready for execution by the MicroBlaze. The elf binary is combined with the XPS-generated bitstream to program the FPGA with the final hardware+software design.
 
- * [wiki:Exercises/HelloWorld] - The Hello World exercise is what we recommend all new users of WARP start with. By the end of it, users will use C-code to control LEDs on the board as well as print messages over UART.
+== Exercises ==
+
+'''[wiki:Exercises/HelloWorld SDK Intro:]''' This is the classic "hello world" project for WARP v3 using the Xilinx SDK. We provide an already-built bitstream with a MicroBlaze and some basic peripheral cores. This exercise uses the SDK to write some simple C code, compile it for the template hardware project and download the harware+software design to the WARP v3 board. At the end of this exercise you should be comfortable with the basic software design flow using the SDK.
+
+'''[wiki:Exercises/SysGenExport XPS Intro:]''' This exercise introduces 
+
 * [wiki:Exercises/SysGenExport] - In this exercise, users will instead control the LEDs on the board with an FPGA design constructed in Xilinx System Generator. The process this exercise takes you through mirrors the steps that would occur if this peripheral core were a new physical layer.