Changes between Version 11 and Version 12 of GettingStarted/WARPv3/IntroToTools

Timestamp:

Aug 13, 2012, 7:44:17 PM (12 years ago)

Author:

murphpo

Comment:

--

GettingStarted/WARPv3/IntroToTools

@@ -14 +14 @@
 
 The basic structure of WARP reference designs is illustrated below.
+
 [[Image(GettingStarted/WARPv3/files:w3_EDK_Proj_BlkDiag.png, nolink)]]
+
+The major components of this architecture are:
+ * MicroBlaze soft processor: The MicroBlaze is a processor core implemented in the FPGA fabric and is supplied by Xilinx as part of the EDK. This processor replaces the hard PPC405 core familiar to users of WARP v1 and v2.
+ * Memories: the Virtex-6 FPGA includes a large number of "block RAMs", or internal RAM blocks which can be interconnected to form arbitrarily sized memory areas accessible to the MicroBlaze. These block RAMs are used for cache, instruction and data storage.
+ * Processor bus: a standard bus connects the MicroBlaze to each core in the system. Current reference designs use a bus called PLB; future designs will migrate to the newer AXI standard.
+ * Peripheral cores: a collection of peripheral cores compose every hardware design. Some are provided by Xilinx (like the UART and Ethernet MAC). We have designed others (like the WARP v3 user I/O and radio interface cores).
+ * Off-chip resources: these blocks represent the other hardware on WARP v3 besides the FPGA, like the radio interfaces, FTDI USB-UART transceiver and Marvell Ethernet PHYs
 
 The MicroBlaze processor and connected cores are all implemented in the FPGA fabric using XPS. The output of the XPS flow is a "bitstream" with the fully synthesized and implemented hardware design. This bitstream integrates the MicroBlaze, the standard peripheral cores, your custom cores, I/O assignments, clock configurations and timing constraints. However the MicroBlaze instruction and data memories are blank in this bitstream.