Changes between Initial Version and Version 1 of HardwareUsersGuides/CM-PLL/Connectors

Timestamp:

Mar 1, 2015, 8:29:34 PM (9 years ago)

Author:

murphpo

Comment:

--

HardwareUsersGuides/CM-PLL/Connectors

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+[[TracNav(HardwareUsersGuides/CM-PLL/TOC)]]
+
+= CM-PLL Clock Module: Connectors =
+
+The CM-PLL board has 3 connectors for external cable connections:
+ * MMCX jack
+ * Board-to-board Header In
+ * Board-to-board Header Out
+
+[[Image(wiki:HardwareUsersGuides/CM-PLL/files:connectors.png, nolink)]]
+
+|| [[Image(wiki:HardwareUsersGuides/WARPv3/files:important.png,nolink,valign=middle)]] || The WARP v3 board should be powered off before any cables are connected or disconnected from the CM-PLL connectors. The equipment driving the cables should also be powered off when making connections. ||
+
+== MMCX Jack ==
+
+The MMAC jack is used to feed a reference clock signal from external equipment, such as test equipment with a 10MHz reference output. This connector is a standard-polarity, standard-gender 50-ohm MMCX jack, also known as a MMCX female connector. The mating cable should have a 50 ohm MMCX plug (male connector). 
+
+The MMCX jack feeds a simple circuit which converts the single-ended input signal into a differential signal, which then drives one of the inputs of the reference clock mux. The MMCX reference input can be selected with the appropriate [wiki:../Configuration#ReferenceClockSource DIP switch setting].
+
+The MMCX reference input presents a 50-ohm load and requires a clock signal amplitude at least 800mVp-p.
+
+The reference designs which use the CM-PLL and [wiki:cores/w3_clock_controller w3_clock_controller core] assume a 10MHz reference frequency. However the AD9511 PLL can be configured for a wide range of reference frequencies. Refer to the AD9511 datasheet for details on appropriate divider settings for alternate reference frequencies. Custom divider settings can be implemented using the [wiki:cores/w3_clock_controller#CustomConfigurations w3_clock_controller custom config] feature.
+
+== Board-to-Board Headers ==
+
+The board-to-board headers are designed to support daisy chaining multiple WARP v3 kits equipped with CM-PLL modules. The "In" header dedicates one pin to a reference clock input, selected by the appropriate [wiki:../Configuration#ReferenceClockSource DIP switch setting]. The "Out" header dedicates one pin to a copy of the reference clock signal. This output can be enabled or disabled via [wiki:../Configuration#ReferenceClockOutput via the DIP switch].
+
+Each header also has 4 pins tied to dedicated FPGA I/O. These FPGA pins are bidirectional. User designs can assign the pins whatever function the application requires. The [wiki:WARPLab WARPLab reference design], for example, uses the 4 I/O on the "In" header as trigger inputs, and 4 I/O on the "Out" header as trigger outputs.
+
+The 8 FPGA I/O pins routed to the board-to-board headers use 2.5v levels. These pins are '''not''' 3.3v tolerant.
+
+The board-to-board headers are 5x2-pin [http://www.samtec.com/technical-specifications/Default.aspx?seriesMaster=tfm Samtec TFM series connectors], part number 105-02-S-D-WT.
+
+=== Pinout ===
+The pinout of the two headers is specified below. The figure is oriented the same as the photo above.
+
+[[Image(wiki:HardwareUsersGuides/CM-PLL/files:brd_to_brd_conns, nolink)]]
+
+||||=  '''In''' Header  =||
+|| Pin || Function || Specs ||
+|| 1 || Reference Clock Input || Single-ended clock signal, 3.3v max ||
+|| 3 || HDR_IN<0> || FPGA Pin V28 ||
+|| 5 || HDR_IN<1> || FPGA Pin V27 ||
+|| 7 || HDR_IN<2> || FPGA Pin V33 ||
+|| 9 || HDR_IN<3> || FPGA Pin V34 ||
+|| (2,4,6,8,10] || Ground ||||
+
+
+
+=== Cables ===
+There are multiple cable options: