Changes between Version 1 and Version 2 of HardwareUsersGuides/CM-PLL/Connectors
- Timestamp:
- Mar 1, 2015, 8:31:21 PM (9 years ago)
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HardwareUsersGuides/CM-PLL/Connectors
v1 v2 35 35 The pinout of the two headers is specified below. The figure is oriented the same as the photo above. 36 36 37 [[Image(wiki:HardwareUsersGuides/CM-PLL/files:brd_to_brd_conns , nolink)]]37 [[Image(wiki:HardwareUsersGuides/CM-PLL/files:brd_to_brd_conns.png, nolink)]] 38 38 39 |||| = '''In''' Header =||39 ||||||= '''In''' Header =|| 40 40 || Pin || Function || Specs || 41 41 || 1 || Reference Clock Input || Single-ended clock signal, 3.3v max || … … 46 46 || (2,4,6,8,10] || Ground |||| 47 47 48 48 ||||||= '''Out''' Header =|| 49 || Pin || Function || Specs || 50 || 1 || HDR_OUT<3> || FPGA Pin W29 || 51 || 3 || HDR_OUT<2> || FPGA Pin V32 || 52 || 5 || HDR_OUT<1> || FPGA Pin W34 || 53 || 7 || HDR_OUT<0> || FPGA Pin W30 || 54 || 9 || Reference Clock Output || Single-ended clock signal, 3.3v max || 55 || (2,4,6,8,10] || Ground |||| 49 56 50 57 === Cables ===
