Changes between Version 2 and Version 3 of HardwareUsersGuides/ClockBoard_v1.1/Configuration


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Timestamp:
Jan 31, 2010, 12:09:18 PM (14 years ago)
Author:
murphpo
Comment:

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  • HardwareUsersGuides/ClockBoard_v1.1/Configuration

    v2 v3  
    44== WARP Clock Board Configuration ==
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    6 The AD9510 clock buffers have serial interfaces for configuring their internal register banks. We provide a custom hardware core which implements the necessary logic to drive these interfaces. The [source:/PlatformSupport/CustomPeripherals/pcores/clock_board_config_v1_03_a clock_board_config] core automatically configures the clock board when included in an FPGA design. This core requires a clock input which does not come from the clock board; the FPGA board's 100 MHz oscillator works well. Most of the core's other ports must be tied to the clock board connector's data pins, according to the following table. This assignment is handled automatically if you build your project using Base System Builder and the WARP FPGA Board's [source:/PlatformSupport/XBD/boards/ XBD].
     6The AD9510 clock buffers have serial interfaces for configuring their internal register banks. We provide a custom hardware core which implements the necessary logic to drive these interfaces. The [source:/PlatformSupport/CustomPeripherals/pcores/clock_board_config_v1_04_a clock_board_config] core automatically configures the clock board when included in an FPGA design. This core requires a clock input which does not come from the clock board; the FPGA board's 100 MHz oscillator works well. Most of the core's other ports must be tied to the clock board connector's data pins, according to the following table. This assignment is handled automatically if you build your project using Base System Builder and the WARP FPGA Board's [source:/PlatformSupport/XBD/boards/ XBD].
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    88|| '''clock_board_config[[BR]]Port''' || '''Clock Board[[BR]]Header Pin''' || '''FPGA[[BR]]Pin''' ||