Changes between Version 3 and Version 4 of HardwareUsersGuides/FPGABoard_v1.2/Clocking
- Timestamp:
- Jul 9, 2007, 1:07:21 PM (17 years ago)
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HardwareUsersGuides/FPGABoard_v1.2/Clocking
v3 v4 6 6 The FPGA board has two oscillator footprints for general clocks. By default, one 100MHz oscillator is mounted (component Y5) and one footprint is left empty (component Y6) for future customization. Both oscillator footprints are connected to global clock (GCLK) pins on the FPGA. 7 7 8 A third oscillator is used for the SystemACE CompactFlash controller. This clock runs at 33MHz and is routed to both the Sysace and FPGA. 9 10 || Clock || Component || FPGA Pin || 11 || 100MHz || Y5 || AH21 || 12 || NM || Y6 || AH20 || 13 8 14 === Off-board Clock Sources === 9 The FPGA board has a header dedicated to off-board clocks. This header (component J29) is generallyused by the [wiki:HardwareUsersGuides/ClockBoard WARP Clock Board]. The header connects to four global clock (GCLK) pins on the FPGA, the 3.3v power plane and 8 general FPGA I/O.15 The FPGA board has a header dedicated to off-board clocks. This header (component J29) is used by the [wiki:HardwareUsersGuides/ClockBoard WARP Clock Board]. The header connects to four global clock (GCLK) pins on the FPGA, the 3.3v power plane and 8 general FPGA I/O. 10 16 11 [[BR]][[Image(HardwareUsersGuides/FPGABoard_v1.2/Images:FPGA_Board_ClkHeader.jpg)]] 17 [[Image(HardwareUsersGuides/FPGABoard_v1.2/Images:FPGA_Board_ClkHeader.jpg)]] 18 19 || Header Pin || FPGA GCLK || FPGA Pin || 20 || 3 || GCLK0P || AK20 || 21 || 4 || GCLK1S || AL20 || 22 || 7 || GCLK6P || AT20 || 23 || 8 || GCLK7S || AR20 || 12 24 13 25 === SystemACE CF Clocking === 14 26 The SystemACE CF controller requires a 33MHz clock which runs at all times. The FPGA requires a copy of this clock in order to use the SystemACE controller's microprocessor interface. A dedicated 33MHz oscillator (component Y4) is used on the FPGA board to supply this clock. The oscillator's output is split and driven to both the FPGA and the SystemACE CF controller. 15 27 28 || Clock || Component || FPGA Pin || 29 || 33MHz || Y4 || N20 || 30 16 31 === MGT Clocking === 17 32 Please see [wiki:HardwareUsersGuides/FPGABoard_v1.2/MGTs#Clocking MGTs] for details on clocking the FPGA's multi-gigabit transceivers.
