Changes between Version 7 and Version 8 of HardwareUsersGuides/FPGABoard_v1.2/Clocking
- Timestamp:
- Jul 9, 2007, 1:20:21 PM (17 years ago)
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HardwareUsersGuides/FPGABoard_v1.2/Clocking
v7 v8 6 6 The FPGA board has two oscillator footprints for general clocks. By default, one 100MHz oscillator is mounted (component Y5) and one footprint is left empty (component Y6) for future customization. Both oscillator footprints are connected to global clock (GCLK) pins on the FPGA. 7 7 8 A third oscillator is used for the SystemACE CompactFlash controller. This clock runs at 33MHz and is routed to both the Sysace and FPGA.8 The Virtex-II Pro FPGA contains 8 Digital Clock Managers (DCM) which can synthesize a wide range of clock signals given the 100MHz oscillator input. 9 9 10 10 || '''Clock''' || '''Component''' || '''FPGA Pin''' || … … 31 31 === MGT Clocking === 32 32 Please see [wiki:HardwareUsersGuides/FPGABoard_v1.2/MGTs#Clocking MGTs] for details on clocking the FPGA's multi-gigabit transceivers. 33 34 === Other References === 35 * [http://direct.xilinx.com/bvdocs/publications/ds083.pdf Xilinx Virtex-II Pro Datasheet] (Module 3: DC & Switching Characteristics) 36 * [http://direct.xilinx.com/bvdocs/userguides/ug012.pdf Xilinx Virtex-II Pro Users Guide] (Chapter 2: Timing Models and Chapter 3: Digital Clock Managers) 37 * [source:/Hardware/FPGA_Board/Rev1.2/Schematics_FPGABoard_1.2.pdf WARP FPGA Board Schematics] (pg. 2)
