Changes between Version 2 and Version 3 of HardwareUsersGuides/FPGABoard_v1.2/MGTs


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Timestamp:
Jul 9, 2007, 11:04:31 AM (17 years ago)
Author:
murphpo
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  • HardwareUsersGuides/FPGABoard_v1.2/MGTs

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    22[[TracNav(HardwareUsersGuides/FPGABoard_v1.2/TOC)]]
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     4The FPGA board provides 8 multi-gigabit transceiver connections for board-to-board links. These transceivers are each capable of 3.125Gb/sec full-duplex communication with another board. The MGTs are provided to enable very high-speed connections between multiple WARP FPGA boards for applications requiring the processing resources of multiple FPGAs.
     5
     6For extensive documentation on using the MGTs, refer to Xilinx's [http://direct.xilinx.com/bvdocs/userguides/ug024.pdf Virtex-II Pro MGT Users Guide].
     7
     8The MGT connections are arrayed along the top of the FPGA board, numbered 1-8 right-to-left.
     9
    410[[Image(HardwareUsersGuides/FPGABoard_v1.2/Images:FPGA_Board_MGTs.jpg)]]
     11
     12=== MGT Clocking ===
     13
     14MGTs require reference clocks provided by very low jitter differential oscillators. The WARP FPGA board includes footprints for two such oscillators. One is mounted by default; the other is left unmounted for future customization.
     15
     16The MGTs require clocks driven into specific pins on the FPGA, refered to as BREFCLK and BREFCLK2. The left oscillator (component Y1) drives BREFCLK; the right oscillator (component Y3) drives BREFCLK2. The pin mapping for these clock signals are:
     17
     18|| Clk Input || Schematic Name || FPGA Pin ||
     19|| BREFCLK+ || MGT_CLK0P || E20 ||
     20|| BREFCLK- || MGT_CLK0N || D20 ||
     21|| BREFCLK2+ || MGT_CLK1P || J20 ||
     22|| BREFCLK2- || MGT_CLK1N || K20 ||
     23
     24|| BREFCLK Oscillator || BREFCLK2 Oscillator ||
     25|| [[Image(HardwareUsersGuides/FPGABoard_v1.2/Images:FPGA_Board_MGTCLK1.jpg)]] || [[Image(HardwareUsersGuides/FPGABoard_v1.2/Images:FPGA_Board_MGTCLK2.jpg)]] ||
     26
     27The oscillators can be disabled by mounting shunts on the adjascent 2-pin headers. When disabled, the reference clock can be driven to the FPGA through a pair of MMCX connectors. This allows multiple FPGA boards to share a common MGT reference clock, which enables an applicaiton to bypass the high-latency elastic buffers in the transceivers.
    528
    629=== VTRX Configuration ===
    … …  
    932[[Image(HardwareUsersGuides/FPGABoard_v1.2/Images:FPGA_Board_MGTVTRX.jpg)]]
    1033
    11 === Clocking ===
    1234
    13 Left-oscillator connects to BREFCLK, right-oscillator connects to BREFCLK2, mount shunts to disable oscillators
    14 
    15 [[Image(HardwareUsersGuides/FPGABoard_v1.2/Images:FPGA_Board_MGTCLK1.jpg)]]
    16 
    17 [[Image(HardwareUsersGuides/FPGABoard_v1.2/Images:FPGA_Board_MGTCLK2.jpg)]]
    1835
    1936=== Cables ===
    … …  
    2138[[BR]]
    2239[http://www.molex.com/cgi-bin/bv/molex/jsp/products/datasheet.jsp?productid=35277 Molex HSDDC2 Cables]
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