Changes between Version 2 and Version 3 of HardwareUsersGuides/FPGABoard_v1.2/UserIO


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Timestamp:
Jul 9, 2007, 1:51:37 PM (17 years ago)
Author:
murphpo
Comment:

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  • HardwareUsersGuides/FPGABoard_v1.2/UserIO

    v2 v3  
    55
    66=== Push Buttons ===
    7 Five push buttons are connected to dedicated FPGA inputs and are arranged in a cross. They are generally referred as up, down, left, right and center. The buttons are normally open connections with external pull down resistors. Thus, the FPGA will observe logic high when a button is depressed, logic low otherwise. The switches are debounced by a simple low pass filter on the board, but user applications which are sensitive to accidental or repeated rising edges should further debounce the input digitally.
     7Five push buttons are connected to dedicated FPGA inputs and are arranged in a cross. They are generally referred as up, down, left, right and center. The buttons are normally open connections with external pull down resistors. Thus, the FPGA will observe logic high when a button is depressed, logic low otherwise.
     8
     9The switches are debounced by a simple low pass filter on the board, but user applications which are sensitive to accidental or repeated rising edges should further debounce the input digitally.
    810
    911In most FPGA designs, the down button is assigned to the PowerPC's soft reset input. When pushed and released, the PowerPC will reset and re-enter the user's main() function. If desired, the choice of the reset button can be changed in an EDK project's UCF file.
     12
     13|| '''Button''' || '''FPGA Pin''' ||
     14|| Up || AJ22 ||
     15|| Down || AM16 ||
     16|| Left || AJ15 ||
     17|| Right || AG18 ||
     18|| Center || AG17 ||
     19
    1020
    1121=== DIP Switch ===
    1222The 4-position DIP switch drives four dedicated inputs on the FPGA. Sliding a switch to the left drives the input to logic low; to the right drives the input to logic high.
    1323
     24|| '''Switch''' || '''FPGA Pin''' ||
     25|| 1 (top) || Y27 ||
     26|| 2 || Y28 ||
     27|| 3 || AA27 ||
     28|| 4 (bottom) || Y29 ||
     29
    1430=== LEDs ===
    1531Four discrete LEDs are connected to four FPGA outputs. A logic high output will cause a LED to glow.
    1632
     33|| '''LED''' || '''FPGA Pin''' ||
     34|| 1 (top) || AJ14 ||
     35|| 2 || AM13 ||
     36|| 3 || AR12 ||
     37|| 4 (bottom) || AH13 ||
     38
    1739=== Seven Segment Displays ===
    18 Two 7-segment LED displays are connected to 14 dedicated FPGA outputs, where each segment is driven by an separate FPGA output. The segments are mapped as shown in the image below. The decimal point LEDs on the displays are not used.
     40Two 7-segment LED displays are connected to 14 dedicated FPGA outputs, where each segment is driven by an separate FPGA output. The segments are mapped as shown in the image below. The decimal point LEDs on the displays are not used. A logic high causes the corresponding LED segment to illuminate.
    1941
    20 [[Image(HardwareUsersGuides/FPGABoard_v1.2/Images:FPGA_Board_7seg.jpg, align=left, 150)]]
     42Your applicaiton must handle the mapping of hexadecimal digits to the 7 LED segments. Example Verilog and C code is included below which implements this mapping.
     43
     44[[Image(HardwareUsersGuides/FPGABoard_v1.2/Images:FPGA_Board_7seg.jpg, align=center, 150)]]
     45
     46|| '''Display''' || '''Segment''' || '''FPGA Pin''' ||
     47|| Left (D12) || 0 || AJ26 ||
     48|| Left (D12) || 1 || AH26 ||
     49|| Left (D12) || 2 || AH24 ||
     50|| Left (D12) || 3 || AH25 ||
     51|| Left (D12) || 4 || AH23 ||
     52|| Left (D12) || 5 || AG22 ||
     53|| Left (D12) || 6 || AG23 ||
     54|| Right (D13) || 0 || AG19 ||
     55|| Right (D13) || 1 || AG21 ||
     56|| Right (D13) || 2 || AH19 ||
     57|| Right (D13) || 3 || AJ19 ||
     58|| Right (D13) || 4 || AP12 ||
     59|| Right (D13) || 5 || AN13 ||
     60|| Right (D13) || 6 || AL15 ||
     61
     62
     63{{{
     64#!verilog
     65module sevenSegmentMap
     66(
     67        input   [3:0]   fourBitInput,
     68        output  [6:0]   hexDisplay
     69);
     70
     71reg     [6:0]   hexDisplay;
     72
     73always @(fourBitInput[3:0])
     74        case (fourBitInput[3:0])
     75                4'b0001 : hexDisplay = ~(7'b1111001);   // 1
     76                4'b0010 : hexDisplay = ~(7'b0100100);   // 2
     77                4'b0011 : hexDisplay = ~(7'b0110000);   // 3
     78                4'b0100 : hexDisplay = ~(7'b0011001);   // 4
     79                4'b0101 : hexDisplay = ~(7'b0010010);   // 5
     80                4'b0110 : hexDisplay = ~(7'b0000010);   // 6
     81                4'b0111 : hexDisplay = ~(7'b1111000);   // 7
     82                4'b1000 : hexDisplay = ~(7'b0000000);   // 8
     83                4'b1001 : hexDisplay = ~(7'b0010000);   // 9
     84                4'b1010 : hexDisplay = ~(7'b0001000);   // A
     85                4'b1011 : hexDisplay = ~(7'b0000011);   // b
     86                4'b1100 : hexDisplay = ~(7'b1000110);   // C
     87                4'b1101 : hexDisplay = ~(7'b0100001);   // d
     88                4'b1110 : hexDisplay = ~(7'b0000110);   // E
     89                4'b1111 : hexDisplay = ~(7'b0001110);   // F
     90                default : hexDisplay = ~(7'b1000000);   // 0
     91        endcase
     92endmodule
     93}}}
     94
     95{{{
     96#!C
     97unsigned char sevenSegmentMap(unsigned char x)
     98{
     99        switch(x)
     100        {
     101                case(0x0) : return 0x007E;
     102                case(0x1) : return 0x0030;
     103                case(0x2) : return 0x006D;
     104                case(0x3) : return 0x0079;
     105                case(0x4) : return 0x0033;
     106                case(0x5) : return 0x005B;
     107                case(0x6) : return 0x005F;
     108                case(0x7) : return 0x0070;
     109                case(0x8) : return 0x007F;
     110                case(0x9) : return 0x007B;
     111
     112                case(0xA) : return 0x0077;
     113                case(0xB) : return 0x007F;
     114                case(0xC) : return 0x004E;
     115                case(0xD) : return 0x007E;
     116                case(0xE) : return 0x004F;
     117                case(0xF) : return 0x0047;
     118                default   : return 0x0000;
     119        }
     120}
     121}}}