Changes between Version 4 and Version 5 of HardwareUsersGuides/FPGABoard_v2.2/Memory


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Timestamp:
Oct 19, 2009, 12:38:22 AM (10 years ago)
Author:
sgupta
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  • HardwareUsersGuides/FPGABoard_v2.2/Memory

    v4 v5  
    44
    55=== On-Chip Memory ===
    6 The V4 FX100 FPGA provides 376 18kb RAM blocks (6.7Mb total). Logic slices can also be used as RAM (what XIlinx calls ''distributed memory''); the FX100 provides up to 659kb of distributed memory.
     6The V4 FX100 FPGA provides 376 18kb RAM blocks (6.7Mb total) on-chip. Logic slices can also be used as RAM (Xilinx calls this ''distributed memory''); the FX100 provides up to 659kb of distributed memory.
    77
    88=== DDR2 SO-DIMM ===
     
    1212[[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:FPGABoard_Memory.jpg, width=300)]]
    1313
    14 In order to use the SO-DIMM, the user FPGA design must include a DDR2 memory controller. Thankfully, Xilinx provides (and maintains) a high performance controller as part of their Multi-Port Memory Controller (MPMC).
     14In order to use the SO-DIMM, the user FPGA design must include a DDR2 memory controller. Xilinx provides (and maintains) a high performance controller as part of their Multi-Port Memory Controller (MPMC).
    1515
    1616We have verified the MPMC in EDK 10.1.03 and 11.3 using a 2GB SO-DIMM from Crucial (part [http://www.crucial.com/store/partspecs.aspx?imodule=CT25664AC667 CT25664AC667]). Other modules should be compatible, but may require customization of the MPMC parameters.
     
    1818There are a large number of pins and parameters involved in instantiating the MPMC in a design. We strongly recommend using Base System builder and our [source:/PlatformSupport/XBD/boards/Rice_University_WARP_FPGA_V4FX100_v22_ClkBoard/data XBD file] to generate MPMC designs. The MHS snippet below is an example instantiation (for EDK 10.1.03).
    1919
     20The base system builder always instantiates a 2GB memory. This uses half the address space of the PowerPC core. If address space is needed for other peripherals, the user can simply reduce the address space of the MPMC without changing any other parameters of the IP core.
     21
    2022{{{
    2123#!sh
    22 EGIN mpmc
     24BEGIN mpmc
    2325 PARAMETER INSTANCE = DDR2_SDRAM_2GB
    2426 PARAMETER HW_VER = 4.03.a