| | 1 | [[TracNav(HardwareUsersGuides/UserIOBoard_v1.0/TOC)]] |
| | 2 | == [wiki:HardwareUsersGuides/UserIOBoard_v1.0 WARP User I/O Board] Trackball & Buttons == |
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| | 4 | The user I/O board provides three kinds of input- a trackball, push buttons and a DIP switch. These components are shown here and described in detail below. |
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| | 6 | [[Image(HardwareUsersGuides/UserIOBoard_v1.0/Files:UserIO_Inputs.png)]] |
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| | 9 | === Trackball === |
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| | 11 | The trackball is supplied by [http://www.sparkfun.com/commerce/product_info.php?products_id=755 SparkFun Electronics]. SparkFun also hosts a copy of the original [http://www.sparkfun.com/datasheets/Components/Trackball.pdf datasheet]. |
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| | 13 | The trackball contains five mechanical switches and has 8 pins tied to FPGA I/O via the daughtercard headers. The switches and their corresponding pins are illustrated below. |
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| | 15 | [[Image(HardwareUsersGuides/UserIOBoard_v1.0/Files:TrackballSch.png)]] |
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| | 17 | When the user scrolls the trackball up/down/left/right, the corresponding direction's switch alternates between closed and open. The switches for each axis (X and Y) share a common pin (XSCN and YSCN). The FPGA should drive these common pins high. The other pins are pulled low by discrete resistors on the User I/O Board. The FPGA can monitor these pins for a logic 1 to detect scrolling. |
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| | 19 | The trackball also has a switch to detect when the ball is pushed. This switch is normally open; when closed, it shorts pins SEL1 and SEL2. SEL1 should be driven high by the FGPA. SEL2 is pulled low and will show a logic 1 when the trackball is pushed. |
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| | 21 | The trackball input signals are debounced in hardware with simple RC circuits. It is recommended that user designs employ digital debouncing as well. |
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| | 23 | === Push Buttons === |
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| | 25 | There are 8 discrete push buttons on the User I/O Board. Six are miniture buttons along the left edge of the LCD screen. These buttons are ideal for applications where the LCD is used interactively. Two larger push buttons are provided for general use. All 8 buttons are tied to dedicated FPGA I/O via the daughtercard headers. |
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| | 27 | Each button is debounced in hardware with a simple RC circuit. It is recommended that user designs employ digital debouncing as well. |
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