Changes between Version 5 and Version 6 of HardwareUsersGuides/WARPv3/RF

Timestamp:

Aug 12, 2012, 10:48:08 PM (12 years ago)

Author:

murphpo

Comment:

--

HardwareUsersGuides/WARPv3/RF

@@ -5 +5 @@
 
 [[Image(wiki:HardwareUsersGuides/WARPv3/files:w3_RF_blkDiag.png, nolink)]]
+
+On the WARP v3 board and in our reference designs, these interfaces are labeled RF A and RF B, where RF A is nearer the top edge of the board (closer to the hex displays).
 
 == AD9963 ADC/DAC ==
@@ -14 +16 @@
 The digital I/Q ports on the AD9963 operate at double data rate, with I/Q interleaved. We have designed the [wiki:/cores/w3_ad_bridge w3_ad_bridge] core to connect these DDR ports to separate internal I/Q busses in user designs.
 
+=== Tx Data Path ===
+The AD9963 integrates 3 stages of digital interpolation filters. These filters can be en/disabled at run time via SPI register writes. By cascading the filters the AD9963 can apply interpolation of 1x, 2x, 4x or 8x.
+
+A single AD9963 Tx data path is illustrated below. Identical data paths are implemented for both DACs (I and Q).
+
+[[Image(HardwareUsersGuides/WARPv3/files:w3_AD_Tx.png, nolink)]]
+
+||= Int Rate =||= Enabled Filters =||
+|| 1 || None ||
+|| 2 || INT0 ||
+|| 4 || INT0, INT1 ||
+|| 8 || INT0, INT1, SRRC ||
+
+The figures below show the effective frequency response of the Tx path for interpolation rates 2, 4, and 8. The frequency axis is normalized to the DAC sampling rate. These figures come from pg. 38 of the AD9963 datasheet.
+||= 2x Interpolation =||= 4x Interpolation =||= 8x Interpolation =||
+|| [[Image(HardwareUsersGuides/WARPv3/files:w3_AD_TxFreqResp_Int2.png)]] || [[Image(HardwareUsersGuides/WARPv3/files:w3_AD_TxFreqResp_Int4.png)]] || [[Image(HardwareUsersGuides/WARPv3/files:w3_AD_TxFreqResp_Int8.png)]] ||
+
+
+=== Clocking ===
+The clocking configuration of the AD9963 is flexible and, as a result, complicated. There are to main clock domains in the AD9963: data clocks, connected to the FPGA, and converter clocks, used by the ADC/DAC cores.
+
+The converter clocks are illustrated below.
+
+[[Image(HardwareUsersGuides/WARPv3/files:w3_AD_clks.png, nolink)]]
+
+Notice that the DAC and ADC clocks are always derived from the AD9963 reference clock input, not the data clock inputs. The data clocks must be synchronous to the converter clocks, but by separating these domains the low jitter of the original reference clock is preserved. 
+
+The DLL parameters (M/N), ADC clock divider and mux selects are all configured via SPI register writes.
+
+
+----
 == MAX2829 Transceiver ==
 
@@ -33 +66 @@
 
 The performance of the MAX2829 RF inputs are specified for input powers below approximately -10dBm. To connect two WARP v3 kits via a coax cable, ensure there is at lest 40dB series attenuation.
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