Changes between Version 6 and Version 7 of HardwareUsersGuides/WARPv3/RF


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Timestamp:
Aug 13, 2012, 12:03:26 AM (12 years ago)
Author:
murphpo
Comment:

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  • HardwareUsersGuides/WARPv3/RF

    v6 v7  
    2929|| 8 || INT0, INT1, SRRC ||
    3030
    31 The figures below show the effective frequency response of the Tx path for interpolation rates 2, 4, and 8. The frequency axis is normalized to the DAC sampling rate. These figures come from pg. 38 of the AD9963 datasheet.
     31The figures below show the effective frequency response of the Tx path for interpolation rates 2, 4, and 8. The frequency axis is normalized to the DAC sampling rate. Click each figure for the full-resolution. These figures come from pg. 38 of the AD9963 datasheet.
    3232||= 2x Interpolation =||= 4x Interpolation =||= 8x Interpolation =||
    33 || [[Image(HardwareUsersGuides/WARPv3/files:w3_AD_TxFreqResp_Int2.png)]] || [[Image(HardwareUsersGuides/WARPv3/files:w3_AD_TxFreqResp_Int4.png)]] || [[Image(HardwareUsersGuides/WARPv3/files:w3_AD_TxFreqResp_Int8.png)]] ||
     33|| [[Image(HardwareUsersGuides/WARPv3/files:w3_AD_TxFreqResp_Int2.png,width=300)]] || [[Image(HardwareUsersGuides/WARPv3/files:w3_AD_TxFreqResp_Int4.png,width=300)]] || [[Image(HardwareUsersGuides/WARPv3/files:w3_AD_TxFreqResp_Int8.png,width=300)]] ||
    3434
     35Refer to the AD9963 datasheet for the coefficients used in each interpolation filter.
     36
     37Note that when the interpolation filters are enabled, the user-supplied Tx I/Q samples and the DAC sampling clock run at different frequencies. The user design must ensure the data clock (TXCLK) frequency, DAC clock frequency and interpolation filter settings are in agreement.
     38
     39=== Rx Data Path ===
     40The AD9963 integrates a digital 2x decimation filter. This filter can be en/disabled at run time via an SPI register write. A single Rx data path is illustrated below. Identical data paths are implemented for both ADCs (I and Q).
     41
     42[[Image(HardwareUsersGuides/WARPv3/files:w3_AD_Rx.png, nolink)]]
     43
     44The effective frequency response when the decimation filter is enabled is shown below. This figure comes from pg. 37 of the AD9963 datasheet. Refer to the datasheet for the actual coefficients used in the decimation filter.
     45
     46||= 2x Decimation =||
     47|| [[Image(HardwareUsersGuides/WARPv3/files:w3_AD_RxFreqResp_Dec2.png,width=300)]] ||
     48
     49Note that when the decimation filter is enabled, the Rx I/Q samples and TRXCLK signal will run at a different rate than the ADC sampling clock. The user design must ensure the FPGA clock design and AD9963 filter/clock settings are in agreement.
    3550
    3651=== Clocking ===
    … …  
    4156[[Image(HardwareUsersGuides/WARPv3/files:w3_AD_clks.png, nolink)]]
    4257
    43 Notice that the DAC and ADC clocks are always derived from the AD9963 reference clock input, not the data clock inputs. The data clocks must be synchronous to the converter clocks, but by separating these domains the low jitter of the original reference clock is preserved.
     58Notice that the DAC and ADC clocks are always derived from the AD9963 reference clock input, not the data clock inputs. The data clocks must be synchronous to the converter clocks, but by separating these domains preserves the low jitter of the original reference clock.
    4459
    45 The DLL parameters (M/N), ADC clock divider and mux selects are all configured via SPI register writes.
     60The DLL parameters (M/N), ADC clock divider and mux selects are all configured via SPI register writes. The correct settings depend on the desired sampling rate, the Tx and Rx data rates at the FPGA and the AD9963 rate-change filter settings.
     61
     62Some examples of valid combinations of clock sources, clock frequencies and filter settings are listed below. Many other valid combinations are possible. Note that the w3_ad_bridge and w3_ad_controller do not enforce valid combinations, as these cores do not know what clocks are connected in hardware. The user design must ensure correct settings.
     63
     64{{{#!td
     65Example 1
     66 * Tx I/Q data rate = 40MHz (FPGA-generated TXCLK = 40MHz)
     67 * Interpolation: 1x (INT0, INT1, SRRC bypassed)
     68 * Rx I/Q data rate = 40MHz (AD9963 TRXCLK output = 40MHz)
     69 * Decimation: 1x (DEC bypassed)
     70 * REF_CLK = 40MHz (sampling clock buffer divider set to 2)
     71 * ADCDIV = 1
     72 * DAC_CLK = REF_CLK (40MSps)
     73 * ADC_CLK = REF_CLK (40MSps)
     74}}}
     75{{{#!td
     76Example 2
     77 * Tx I/Q data rate = 40MHz (FPGA-generated TXCLK = 40MHz)
     78 * Interpolation: 4x (INT0, INT1 enabled; SRRC bypassed)
     79 * Rx I/Q data rate = 40MHz (AD9963 TRXCLK output = 40MHz)
     80 * Decimation: 2x (DEC enabled)
     81 * REF_CLK = 80MHz (sampling clock buffer divider set to 1)
     82 * DLL M/N = 2/1 (DLL_CLK = 2*REF_CLK = 160MHz)
     83 * ADCDIV = 1
     84 * DAC_CLK = DLL_CLK (160MSps)
     85 * ADC_CLK = REF_CLK (80MSps)
     86}}}
     87|------------------
     88{{{#!td
     89Example 3
     90 * Tx I/Q data rate = 80MHz (FPGA-generated TXCLK = 80MHz)
     91 * Interpolation: 2x (INT0 enabled; INT1, SRRC bypassed)
     92 * Rx I/Q data rate = 80MHz (AD9963 TRXCLK output = 80MHz)
     93 * Decimation: 1x (DEC bypassed)
     94 * REF_CLK = 80MHz (sampling clock buffer divider set to 1)
     95 * DLL M/N = 2/1 (DLL_CLK = 2*REF_CLK = 160MHz)
     96 * ADCDIV = 1
     97 * DAC_CLK = DLL_CLK (160MSps)
     98 * ADC_CLK = REF_CLK (80MSps)
     99}}}
     100{{{#!td
     101Example 4
     102 * Tx I/Q data rate = 10MHz (FPGA-generated TXCLK = 10MHz)
     103 * Interpolation: 8x (INT0, INT1, SRCC enabled)
     104 * Rx I/Q data rate = 20MHz (AD9963 TRXCLK output = 20MHz)
     105 * Decimation: 2x (DEC bypassed)
     106 * REF_CLK = 80MHz (sampling clock buffer divider set to 1)
     107 * ADCDIV = 2
     108 * DAC_CLK = REF_CLK (80MSps)
     109 * ADC_CLK = REF_CLK (40MSps)
     110}}}
     111
    46112
    47113