Changes between Version 5 and Version 6 of OFDM/MIMO/Docs/ModelPorts
- Timestamp:
- Jan 26, 2008, 1:35:04 AM (16 years ago)
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OFDM/MIMO/Docs/ModelPorts
v5 v6 2 2 3 3 == Clocks == 4 The entire MIMO OFDM model is driven by a single clock and has one top-level clock enable. The clock signal connected to '''opb_clk''' must be the same clock which drives the ADC/DACs on the radio daughtercards .4 The entire MIMO OFDM model is driven by a single clock and has one top-level clock enable. The clock signal connected to '''opb_clk''' must be the same clock which drives the ADC/DACs on the radio daughtercards and the converter_clock_in port on the corresponding radio_bridge cores. 5 5 ||'''Port'''||'''Default'''||'''Direction'''||'''Width'''|| 6 6 ||opb_clk||sys_clk_s||Input||1|| … … 23 23 ||sgp_xferack||Sl_xferAck||Output||1|| 24 24 25 == BRAM Interface Ports == 26 The model includes a BRAM initiator interface, used to access the shared PLB_BRAM packet buffer. The packet buffer is not included in the OFDM design; it must be instantiated in the EDK project and connected to the OFDM core via these ports. 27 ||'''Port'''||'''Default'''||'''Direction'''||'''Width'''|| 28 ||bram_addr||BRAM_Addr||Output||32|| 29 ||bram_datain||BRAM_Din||Input||64|| 30 ||bram_dout||BRAM_Dout||Output||64|| 31 ||bram_reset||BRAM_Rst||Output||1|| 32 ||bram_wen||BRAM_WEN||Output||8|| 33 25 34 == OFDM Core == 26 35 The OFDM core uses dedicated top-level ports to interface with other peripheral cores. Some of these signals are connected to radio bridges, which route the signals off-chip to radio daughtercards. The rest connect to other custom cores for radio-specific PHY functions like AGC and packet detection. … … 33 42 ||rx_int_badpkt||||Output||1||Interrupt output signaling a received packet failed CRC|| 34 43 ||rx_int_goodpkt||||Output||1||Interrupt output signaling a received packet passed CRC and is ready for higher-layer processing|| 44 ||rx_int_goodheader|||Output||1||Interrupt output signaling a received packet's header was error-free; only asserts for packets with a payload beyond the header|| 35 45 ||rx_pktdetreset ||||Output||1||Active-high output indicating that packet detection events should be ignored while the PHY is busy|| 36 46 ||rx_reset ||||Input||1||Active-high global reset input; clears all internal state in the receiver model; does not clear register values|| 47 ||rx_anta_agc_done||||Input||1||Status signal from AGC core for antenna A; asserts high when AGC has settled|| 48 ||rx_anta_gainbb||||Input||5||Baseband gain value in [0...63] chosen by AGC on antenna A. Only valid after rx_antb_agc_done asserts|| 49 ||rx_anta_gainrf||||Input||2||RF gain value in [1,2,3] chosen by AGC on antenna A. Only valid after rx_antb_agc_done asserts|| 50 ||rx_antb_agc_done||||Input||1||Status signal from AGC core for antenna A; asserts high when AGC has settled|| 51 ||rx_antb_gainbb||||Input||5||Baseband gain value in [0...63] chosen by AGC on antenna B. Only valid after rx_antb_agc_done asserts|| 52 ||rx_antb_gainrf||||Input||2||RF gain value in [1,2,3] chosen by AGC on antenna B. Only valid after rx_antb_agc_done asserts|| 37 53 ||tx_anta_dac_i||||Output||16||I channel DAC output for antenna A; output runs at same rate as master clock|| 38 54 ||tx_anta_dac_q||||Output||16||Q channel DAC output for antenna A; output runs at same rate as master clock|| … … 50 66 ||rx_debug_pktdone ||||Output||1||Copy of receiver's !PktDone signal; indicates receiver has finished processing a packet|| 51 67 ||tx_debug_pktrunning ||||Output||1||Copy of transmitter's !PktRunning signal; indicates transmitter is actively transmitting a packet|| 68
