Clocks
The entire MIMO OFDM model is driven by a single clock and has one top-level clock enable. The clock signal connected to opb_clk must be the same clock which drives the ADC/DACs on the radio daughtercards.
Port | Default | Direction | Width
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opb_clk | sys_clk_s | Input | 1
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ce | net_vcc | Input | 1
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OPB Interface Ports
The model includes a standard OPB slave interface. This interface is used to connect the OFDM core to an embedded PowerPC or Microblaze processor in the FPGA. This interface must be connected to a processor in order to use the OFDM core in hardware.
Port | Default | Direction | Width
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opb_abus | OPB_ABus | Input | 32
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opb_be | OPB_BE | Input | 4
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opb_dbus | OPB_DBus | Input | 32
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opb_rnw | OPB_RNW | Input | 1
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opb_rst | OPB_Rst | Input | 1
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opb_select | OPB_select | Input | 1
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opb_seqaddr | OPB_seqAddr | Input | 1
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sgp_dbus | Sl_DBus | Output | 32
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sgp_errack | Sl_errAck | Output | 1
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sgp_retry | Sl_retry | Output | 1
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sgp_toutsup | Sl_toutSup | Output | 1
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sgp_xferack | Sl_xferAck | Output | 1
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OFDM Core
The OFDM core uses dedicated top-level ports to interface with other peripheral cores. Some of these signals are connected to radio bridges, which route the signals off-chip to radio daughtercards. The rest connect to other custom cores for radio-specific PHY functions like AGC and packet detection.
Port | Default | Direction | Width | Notes
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rx_anta_adci_dv4 | Input | 14 | I channel ADC input from antenna A; data must be donwsampled to 1/4 the master clock
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rx_anta_adcq_dv4 | Input | 14 | Q channel ADC input from antenna A; data must be donwsampled to 1/4 the master clock
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rx_antb_adci_dv4 | Input | 14 | I channel ADC input from antenna B; data must be donwsampled to 1/4 the master clock
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rx_antb_adcq_dv4 | Input | 14 | Q channel ADC input from antenna B; data must be donwsampled to 1/4 the master clock
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rx_extpktdet | Input | 1 | External packet detection input; high input indicates a probable arriving packet
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rx_int_badpkt | Output | 1 | Interrupt output signaling a received packet failed CRC
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rx_int_goodpkt | Output | 1 | Interrupt output signaling a received packet passed CRC and is ready for higher-layer processing
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rx_pktdetreset | Output | 1 | Active-high output indicating that packet detection events should be ignored while the PHY is busy
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rx_reset | Input | 1 | Active-high global reset input; clears all internal state in the receiver model; does not clear register values
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tx_anta_dac_i | Output | 16 | I channel DAC output for antenna A; output runs at same rate as master clock
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tx_anta_dac_q | Output | 16 | Q channel DAC output for antenna A; output runs at same rate as master clock
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tx_antb_dac_i | Output | 16 | I channel DAC output for antenna B; output runs at same rate as master clock
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tx_antb_dac_q | Output | 16 | Q channel DAC output for antenna B; output runs at same rate as master clock
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tx_reset | Input | 1 | Active-high global reset input; clears all internal state in the transmitter model; does not clear register values
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tx_starttransmit | Input | 1 | Active-high trigger to begin transmission of a packet; usually tied to one of the radio controller's TxStart outputs
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Debugging Ports
Port | Default | Direction | Width | Notes
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debug_chipscopetrig | Input | 1 | External active-high trigger for ChipScope ILA core in the receiver
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rx_debug_eq_i | Ouput | 14 | I channel of equalized symbols; usually tied to an analog daughtercard for real-time debugging
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rx_debug_eq_q | Ouput | 14 | Q channel of equalized symbols; usually tied to an analog daughtercard for real-time debugging
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rx_debug_payload | Output | 1 | Copy of receiver's Payload signal; indicates receiver is currently processing a packet
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rx_debug_pktdone | Output | 1 | Copy of receiver's PktDone signal; indicates receiver has finished processing a packet
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tx_debug_pktrunning | Output | 1 | Copy of transmitter's PktRunning signa; indicates transmitter is actively transmitting a packet
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