MIMO OFDM | Documentation? | OFDM Model Top-level Ports

Clocks

The entire MIMO OFDM model is driven by a single clock and has one top-level clock enable. The clock signal connected to opb_clk must be the same clock which drives the ADC/DACs on the radio daughtercards and the converter_clock_in port on the corresponding radio_bridge cores.

Port	Default	Direction	Width
opb_clk	sys_clk_s	Input	1
ce	net_vcc	Input	1

OPB Interface Ports

The model includes a standard OPB slave interface. This interface is used to connect the OFDM core to an embedded PowerPC or Microblaze processor in the FPGA. This interface must be connected to a processor in order to use the OFDM core in hardware.

Port	Default	Direction	Width
opb_abus	OPB_ABus	Input	32
opb_be	OPB_BE	Input	4
opb_dbus	OPB_DBus	Input	32
opb_rnw	OPB_RNW	Input	1
opb_rst	OPB_Rst	Input	1
opb_select	OPB_select	Input	1
opb_seqaddr	OPB_seqAddr	Input	1
sgp_dbus	Sl_DBus	Output	32
sgp_errack	Sl_errAck	Output	1
sgp_retry	Sl_retry	Output	1
sgp_toutsup	Sl_toutSup	Output	1
sgp_xferack	Sl_xferAck	Output	1

BRAM Interface Ports

The model includes a BRAM initiator interface, used to access the shared PLB_BRAM packet buffer. The packet buffer is not included in the OFDM design; it must be instantiated in the EDK project and connected to the OFDM core via these ports.

Port	Default	Direction	Width
bram_addr	BRAM_Addr	Output	32
bram_datain	BRAM_Din	Input	64
bram_dout	BRAM_Dout	Output	64
bram_reset	BRAM_Rst	Output	1
bram_wen	BRAM_WEN	Output	8

OFDM Core

The OFDM core uses dedicated top-level ports to interface with other peripheral cores. Some of these signals are connected to radio bridges, which route the signals off-chip to radio daughtercards. The rest connect to other custom cores for radio-specific PHY functions like AGC and packet detection.

Port	Default	Direction	Width	Notes
rx_anta_adci_dv4	Input		14	I channel ADC input from antenna A; data must be donwsampled to 1/4 the master clock
rx_anta_adcq_dv4	Input		14	Q channel ADC input from antenna A; data must be donwsampled to 1/4 the master clock
rx_antb_adci_dv4	Input		14	I channel ADC input from antenna B; data must be donwsampled to 1/4 the master clock
rx_antb_adcq_dv4	Input		14	Q channel ADC input from antenna B; data must be donwsampled to 1/4 the master clock
rx_extpktdet	Input		1	External packet detection input; high input indicates a probable arriving packet
rx_int_badpkt	Output		1	Interrupt output signaling a received packet failed CRC
rx_int_goodpkt	Output		1	Interrupt output signaling a received packet passed CRC and is ready for higher-layer processing
rx_int_goodheader	Output		1	Interrupt output signaling a received packet's header was error-free; only asserts for packets with a payload beyond the header
rx_pktdetreset	Output		1	Active-high output indicating that packet detection events should be ignored while the PHY is busy
rx_reset	Input		1	Active-high global reset input; clears all internal state in the receiver model; does not clear register values
rx_anta_agc_done	Input		1	Status signal from AGC core for antenna A; asserts high when AGC has settled
rx_anta_gainbb	Input		5	Baseband gain value in [0...63] chosen by AGC on antenna A. Only valid after rx_antb_agc_done asserts
rx_anta_gainrf	Input		2	RF gain value in [1,2,3] chosen by AGC on antenna A. Only valid after rx_antb_agc_done asserts
rx_antb_agc_done	Input		1	Status signal from AGC core for antenna A; asserts high when AGC has settled
rx_antb_gainbb	Input		5	Baseband gain value in [0...63] chosen by AGC on antenna B. Only valid after rx_antb_agc_done asserts
rx_antb_gainrf	Input		2	RF gain value in [1,2,3] chosen by AGC on antenna B. Only valid after rx_antb_agc_done asserts
tx_anta_dac_i	Output		16	I channel DAC output for antenna A; output runs at same rate as master clock
tx_anta_dac_q	Output		16	Q channel DAC output for antenna A; output runs at same rate as master clock
tx_antb_dac_i	Output		16	I channel DAC output for antenna B; output runs at same rate as master clock
tx_antb_dac_q	Output		16	Q channel DAC output for antenna B; output runs at same rate as master clock
tx_reset	Input		1	Active-high global reset input; clears all internal state in the transmitter model; does not clear register values
tx_starttransmit	Input		1	Active-high trigger to begin transmission of a packet; usually tied to one of the radio controller's TxStart outputs

Debugging Ports

These ports are provided for real-time debugging of the PHY. The multi-bit ports are intended for use with a WARP analog board. Single-bit ports are usually routed to the 16-bit digital debug header on the WARP FPGA board for observation on an oscilloscope. Some version of the OFDM core will include additional debug ports which may be removed later, depending on our requirements during development.

Port	Default	Direction	Width	Notes
debug_chipscopetrig	Input		1	External active-high trigger for ChipScope ILA core in the receiver
rx_debug_eq_i	Ouput		14	I channel of equalized symbols; usually tied to an analog daughtercard for real-time debugging
rx_debug_eq_q	Ouput		14	Q channel of equalized symbols; usually tied to an analog daughtercard for real-time debugging
rx_debug_payload	Output		1	Copy of receiver's Payload signal; indicates receiver is currently processing a packet
rx_debug_pktdone	Output		1	Copy of receiver's PktDone signal; indicates receiver has finished processing a packet
tx_debug_pktrunning	Output		1	Copy of transmitter's PktRunning signal; indicates transmitter is actively transmitting a packet