Changes between Version 17 and Version 18 of OFDM/MIMO/Docs/ModelRegisters
- Timestamp:
- Sep 26, 2007, 3:10:28 PM (17 years ago)
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OFDM/MIMO/Docs/ModelRegisters
v17 v18 445 445 </table> 446 446 }}} 447 448 447 ---- 449 448 == Rx_ControlBits == 450 === Address: 0x0 === 451 === Dir: Read/Write === 452 === Fields: === 449 === Dir: Read/Write === 450 === Fields: === 451 ==== SISO_ON_ANTB ==== 452 ''(Bit 18)'' Use antenna B when in SISO mode; ignored when in MIMO mode. 453 ==== SWITCHING_DIV_EN ==== 454 ''(Bit 17)'' Enables switching diversity between antenna A and B in SISO mode; ingored when in MIMO mode. The Rx PHY chooses the antenna with the lower AGC-set gains per packet when enabled. 455 ==== SIMPLE_DYN_MOD_EN ==== 456 ''(Bit 16)'' Enables dynamic modulation support, which reads payload modulation information from the received header. 457 ==== EQ_BYPASS_DIVISION ==== 458 ''(Bit 14)'' Bypasses the complex divider in the equalizer, resulting in phase-only equalization. This is useful only when using BPSK or QPSK modulation schemes. 459 ==== USE_PILOT_ARCTAN ==== 460 ''(Bit 13)'' Enables the CORDIC arctangent calculation in the pilot phase estimator. This should be enabled for normal operation. 453 461 ==== CFO_USE_LONGCORR ==== 454 462 ''(Bit 12)'' Enables the use of the long correlator to control the timing of the carrier frequency offset estimation based on the long training symbols. This must be set to 1 for normal operation. 455 ==== CFO_USE_STS ====456 ''(Bit 11)'' Enables carrier frequency offset estimation based on the preamble's short training symbols. When using high-quality oscillators, this can be disabled to improve CFO estimation performance.457 463 ==== CFO_USE_LTS ==== 458 464 ''(Bit 10)'' Enables carrier frequency offset estimation based on the preamble's long training symbols. Must be set to 1 for normal operation. 459 ==== CFO_BYPASS====465 ==== BYPASS_CARR_REC ==== 460 466 ''(Bit 9)'' When set to 1, CFO correction is bypassed. This should only be used when driving two nodes from a common reference clock during PHY debugging. 461 ==== INT_PKT DET_EN====467 ==== INT_PKT_DETECT ==== 462 468 ''(Bit 8)'' Enables the internal packet detection block. This should only be used when debugging the PHY over a wire when the external packet detector is not being used. 463 ==== EXT_PKT DET_EN====469 ==== EXT_PKT_DETECT ==== 464 470 ''(Bit 7)'' Enables external packet detection via the ''[wiki:OFDM/MIMO/Docs/ModelPorts#OFDMCore rx_extpktdet]'' top-level port 465 471 ==== REQ_SHORT_CORR ==== … … 477 483 478 484 ---- 479 == Rx_GlobalReset ==480 === Address: 0x4 ===481 === Dir: Read/Write ===482 === Fields: ===483 ==== RX_RESET ====484 ''(Bit 0)'' Global reset for the receiver state machines. When set to 1, all state in the packet detection, PHY processing, packet construction and interrupt blocks is cleared. This reset does not clear the values of OPB regsters.485 486 ----487 485 == Rx_OFDM_SymbolCounts == 488 === Address: 0x8 ===489 486 === Dir: Read/Write === 490 487 === Fields: === … … 496 493 ---- 497 494 == Rx_PktDet_Delay == 498 === Address: 0xC === 499 === Dir: Read/Write === 500 === Fields: === 495 === Dir: Read/Write === 496 === Fields: === 497 ==== PKT_DET_DELAY ==== 498 ''(Bits 21:16 - UFix6_0)'' This integer sets the delay (in samples) between a long correlation threshold crossing and the start of coarse carrier frequency offset calculation. 499 ==== SYMBOM_TIMING_OFFSET ==== 500 ''(Bits 12:7 - UFix6_0)'' This integer sets the nominal symbol timing offset. This value is used as the starting index for the FFT calculation of each received OFDM symbol. This value must be less than the cyclic prefix length. 501 501 ==== PKT_DET_DELAY ==== 502 502 ''(Bits 6:0 - UFix7_0)'' This integer sets the delay inserted between the course packet detection signal and the start of receiver processing. This delay should correspond to the time difference between packet detection and the start of the preamble's fourth short training symbol. … … 504 504 ---- 505 505 == Rx_PktDet_LongCorr_Params == 506 === Address: 0x10 ===507 506 === Dir: Read/Write === 508 507 === Fields: === … … 514 513 ---- 515 514 == Rx_PktDone_Reset == 516 === Address: 0x14 === 517 === Dir: Read/Write === 518 === Fields: === 515 === Dir: Read/Write === 516 === Fields: === 517 ==== PLBPKTBUF_RX_OFFSET ==== 518 ''(Bits 11:10 - UFix2_0)'' This integer selects the sub-packet-buffer for received packets in the PLB BRAM. The Rx PHY will write incoming packet payloads to this sub-buffer. 519 ==== PLBPKTBUF_TX_OFFSET ==== 520 ''(Bits 9:8 - UFix2_0)'' This integer selects the sub-packet-buffer for transmitted packets in the PLB BRAM. The Tx PHY will read packet payload for transmission from this sub-buffer. 519 521 ==== EN_BADPKT_INT ==== 520 522 ''(Bit 5)'' Enables the bad packet interrupt output. The interrupt is raised via the top-level output ''[wiki:OFDM/MIMO/Docs/ModelPorts#OFDMCore rx_int_badpkt]''. Bad packets are defined as packets which fail the CRC checksum calculation. … … 527 529 528 530 ---- 529 == Rx_symbolTimingOffset == 530 === Address: 0x18 === 531 === Dir: Read/Write === 532 === Fields: === 533 ==== SYMBOL_TIMING_OFFSET ==== 534 ''(Bits 5:0 - UFix6_0)'' This integer sets the nominal symbol timing offset. This value is used as the starting index for the FFT calculation of each received OFDM symbol. This value must be less than the cyclic prefix length. 535 536 ---- 537 == Rx_FreqOffFilt_KI == 538 === Address: 0x1C === 539 === Dir: Read/Write === 540 === Fields: === 541 ==== CFO_FILT_COEF_I ==== 542 ''(Bits 31:0 - UFix32_32)'' Integral path coefficient for the loop filter in the carrier frequency offset pilot phase tracking system. 543 544 545 ---- 546 == Rx_FreqOffFilt_KP == 547 === Address: 0x20 === 548 === Dir: Read/Write === 549 === Fields: === 550 ==== CFO_FILT_COEF_P ==== 551 ''(Bits 31:0 - UFix32_32)'' Proportional path coefficient for the loop filter in the carrier frequency offset pilot phase tracking system. 552 553 ---- 554 == Rx_Constellation_Scaling == 555 === Address: 0x24 === 556 === Dir: Read/Write === 557 === Fields: === 558 ==== ANT_B_SCALING ==== 559 ''(Bits 31:16 - UFix16_11)'' This fixed-point value is used to scale the output of the equalizer for antenna B before symbols are detected. This scaling is used to fit the received constellation to the pre-defined hard decision boundaries used during symbol detection. 560 ==== ANT_A_SCALING ==== 561 ''(Bits 15:0 - UFix16_11)'' This fixed-point value is used to scale the output of the equalizer for antenna A before symbols are detected. This scaling is used to fit the received constellation to the pre-defined hard decision boundaries used during symbol detection. 562 563 ---- 564 == Rx_FFT_Scaling == 565 === Address: 0x28 === 566 === Dir: Read/Write === 567 === Fields: === 568 ==== RX_FFT_SCALING_0 ==== 569 ''(Bits 5:4 - UFix2_0)'' This integer sets the scaling after the first stage of the FFT calculation. 570 ==== RX_FFT_SCALING_1 ==== 571 ''(Bits 3:2 - UFix2_0)'' This integer sets the scaling after the middle stage of the FFT calculation. 572 ==== RX_FFT_SCALING_2 ==== 573 ''(Bits 1:0 - UFix2_0)'' This integer sets the scaling after the last stage of the FFT calculation. 574 575 ---- 576 == Rx_pktDet_Corr_Thresh == 577 === Address: 0x2C === 578 === Dir: Read/Write === 579 === Fields: === 531 == Rx_pktByteNums == 532 === Dir: Read/Write === 533 === Fields: === 534 ==== PKT_BYTENUM_NUMBYTES_LSB ==== 535 ''(Bits 15:8 - UFix8_0)'' Recevied header byte index for lower 8 bits of numPayloadBytes value 536 ==== PKT_BYTENUM_NUMBYTES_MSB ==== 537 ''(Bits 23:16 - UFix8_0)'' Recevied header byte index for upper 8 bits of numPayloadBytes value 538 ==== PKT_BYTENUM_MODMASKS ==== 539 ''(Bits 31:24 - UFix8_0)'' Recevied header byte index for dynamic modulation modMasks value 540 541 ---- 542 == Rx_pktDet_Tresholds == 543 === Dir: Read/Write === 544 === Fields: === 545 ==== PKTDET_ENERGY_THRESH ==== 546 ''(Bits 19:8 - UFix12_5)'' This fixed-point value is the energy threshold used for the internal packetion system. 580 547 ==== PKTDET_CORR_THRESH ==== 581 548 ''(Bits 7:0 - UFix8_7)'' This fixed-point value is the correlation threshold used for the internal packetion system. 582 549 583 550 ---- 584 == Rx_pktDet_Energy_Thresh == 585 === Address: 0x30 === 586 === Dir: Read/Write === 587 === Fields: === 588 ==== PKTDET_ENERGY_THRESH ==== 589 ''(Bits 11:0 - UFix12_5)'' This fixed-point value is the energy threshold used for the internal packetion system. 590 591 ---- 592 == Tx_FFT_Scaling == 593 === Address: 0x34 === 594 === Dir: Read/Write === 595 === Fields: === 551 == TxRx_FFT_Scaling == 552 === Dir: Read/Write === 553 === Fields: === 554 ==== RX_FFT_SCALING_0 ==== 555 ''(Bits 11:10 - UFix2_0)'' This integer sets the scaling after the first stage of the FFT calculation. 556 ==== RX_FFT_SCALING_1 ==== 557 ''(Bits 9:8 - UFix2_0)'' This integer sets the scaling after the middle stage of the FFT calculation. 558 ==== RX_FFT_SCALING_2 ==== 559 ''(Bits 7:6 - UFix2_0)'' This integer sets the scaling after the last stage of the FFT calculation. 596 560 ==== TX_FFT_SCALING_0 ==== 597 561 ''(Bits 5:4 - UFix2_0)'' This integer sets the scaling after the first stage of the IFFT calculation. … … 602 566 603 567 ---- 568 == Rx_FreqOffFilt_KI == 569 === Dir: Read/Write === 570 === Fields: === 571 ==== CFO_FILT_COEF_I ==== 572 ''(Bits 31:0 - UFix32_32)'' Integral path coefficient for the loop filter in the carrier frequency offset pilot phase tracking system. 573 574 ---- 575 == Rx_FreqOffFilt_KP == 576 === Dir: Read/Write === 577 === Fields: === 578 ==== CFO_FILT_COEF_P ==== 579 ''(Bits 31:0 - UFix32_32)'' Proportional path coefficient for the loop filter in the carrier frequency offset pilot phase tracking system. 580 581 ---- 582 == Rx_PhaseNoiseTrack_K == 583 === Dir: Read/Write === 584 === Fields: === 585 ==== Rx_PhaseNoiseTrack_K ==== 586 ''(Bits 31:0 - UFix32_32)'' Scaling constant for phase noise tracking system; should be 0.0095215 (0x2700000) for normal operation. 587 588 ---- 589 == Rx_PhaseNoiseTrack_Kalpha == 590 === Dir: Read/Write === 591 === Fields: === 592 ==== Rx_PhaseNoiseTrack_Kalpha ==== 593 ''(Bits 31:0 - UFix32_32)'' Scaling constant for phase noise tracking system; should be 0.5 (0x40000000) for normal operation. This register will be removed in a future PHY revision. 594 595 ---- 596 == Rx_PhaseNoiseTrack_Kbeta == 597 === Dir: Read/Write === 598 === Fields: === 599 ==== Rx_PhaseNoiseTrack_Kbeta ==== 600 ''(Bits 31:0 - UFix32_32)'' Scaling constant for phase noise tracking system; should be 0.5 (0x40000000) for normal operation. This register will be removed in a future PHY revision. 601 602 ---- 603 == Rx_PhaseNoiseTrack_Kgamma == 604 === Dir: Read/Write === 605 === Fields: === 606 ==== Rx_PhaseNoiseTrack_Kgamma ==== 607 ''(Bits 31:0 - UFix32_32)'' Scaling constant for phase noise tracking system; should be 0.5 (0x40000000) for normal operation. This register will be removed in a future PHY revision. 608 609 ---- 610 == Rx_Constellation_Scaling == 611 === Dir: Read/Write === 612 === Fields: === 613 ==== ANT_B_SCALING ==== 614 ''(Bits 31:16 - UFix16_11)'' This fixed-point value is used to scale the output of the equalizer for antenna B before symbols are detected. This scaling is used to fit the received constellation to the pre-defined hard decision boundaries used during symbol detection. 615 ==== ANT_A_SCALING ==== 616 ''(Bits 15:0 - UFix16_11)'' This fixed-point value is used to scale the output of the equalizer for antenna A before symbols are detected. This scaling is used to fit the received constellation to the pre-defined hard decision boundaries used during symbol detection. 617 618 ---- 604 619 == Tx_PreambleScaling == 605 === Address: 0x38 ===606 620 === Dir: Read/Write === 607 621 === Fields: === … … 610 624 611 625 ---- 612 == Tx_NumPayloadBytes ==613 === Address: 0x3C ===614 === Dir: Read/Write ===615 === Fields: ===616 ==== NUM_BYTES ====617 ''(Bits 11:0 - UFix12_0)'' This integer is the number of payload bytes present in the packet being prepared for transmission. This value must be updated before the transmitter is started. The application must assure that this value agrees with [wiki:OFDM/MIMO/Docs/ModelRegisters#NUM_PYLD_SYMS NUM_PYLD_SYMS] and the selected modulation scheme.618 619 ----620 == Tx_RandomPayload_ModSel ==621 === Address: 0x40 ===622 === Dir: Read/Write ===623 === Fields: ===624 ==== RAND_PLD_MOD_SEL ====625 ''(Bits 1:0 - UFix2_0)'' This integer selects the modulation scheme used when random payload mode in the transmitter is enabled. The mapping is [0,1,2,3] = [0, QPSK, 16-QAM, 64-QAM].626 627 ----628 626 == Tx_Pilots_Index1 == 629 === Address: 0x44 ===630 627 === Dir: Read/Write === 631 628 === Fields: === … … 637 634 ---- 638 635 == Tx_Pilots_Index2 == 639 === Address: 0x48 ===640 636 === Dir: Read/Write === 641 637 === Fields: === … … 647 643 ---- 648 644 == Tx_Pilots_Value1 == 649 === Address: 0x4C ===650 645 === Dir: Read/Write === 651 646 === Fields: === … … 657 652 ---- 658 653 == Tx_Pilots_Value2 == 659 === Address: 0x50 ===660 654 === Dir: Read/Write === 661 655 === Fields: === … … 667 661 ---- 668 662 == Tx_OFDM_SymCounts == 669 === Address: 0x54 ===670 663 === Dir: Read/Write === 671 664 === Fields: === … … 679 672 ---- 680 673 == Tx_Start_Reset_Control == 681 === Address: 0x58 ===682 674 === Dir: Read/Write === 683 675 === Fields: === 684 676 ==== TX_RESET ==== 685 ''(Bit s 1:0 - UFix1_0)'' Global active-high reset for the transmitter subsystem. When asserted, all internal state in the transmitter will be cleared, except the register bank.677 ''(Bit 0 - UFix1_0)'' Global active-high reset for the transmitter subsystem. When asserted, all internal state in the transmitter will be cleared, except the register bank. 686 678 ==== TX_START ==== 687 ''(Bit s 2:1 - UFix1_0)'' Trigger for beginning a packet transmission. This register bit acts exactly like the ''[wiki:OFDM/MIMO/Docs/ModelPorts#OFDMCore tx_starttransmit]'' input port. Only one trigger option (port or register) should be used per packet.679 ''(Bit 1 - UFix1_0)'' Trigger for beginning a packet transmission. This register bit acts exactly like the ''[wiki:OFDM/MIMO/Docs/ModelPorts#OFDMCore tx_starttransmit]'' input port. Only one trigger option (port or register) should be used per packet. 688 680 ==== TX_PKTDONE_RESET ==== 689 ''(Bit s 3:2 - UFix1_0)'' Clears the state of the Tx_PktDone register. User code should toggle this register high/low after each packet transmission.681 ''(Bit 2 - UFix1_0)'' Clears the state of the Tx_PktDone register. User code should toggle this register high/low after each packet transmission. 690 682 691 683 ---- 692 684 == Tx_ControlBits == 693 === Address: 0x5C ===694 685 === Dir: Read/Write === 695 686 === Fields: === 696 687 ==== SISO_MODE ==== 697 ''(Bits 1:0 - UFix1_0)'' Enables SISO mode in the transmitter. This option can be enabled per packet and will only function correctly when used with a receiver in SISO mode. 698 ==== RANDOM_PYLD ==== 699 ''(Bits 2:1 - UFix1_0)'' Enables random payload mode, which transmits random symbols in every subcarrier. The modulation scheme used is configured in the [wiki:OFDM/MIMO/Docs/ModelRegisters#RAND_PLD_MOD_SEL RAND_PLD_MOD_SEL] field. 688 ''(Bit 0)'' Enables SISO mode in the transmitter. This option can be enabled per packet and will only function correctly when used with a receiver in SISO mode. 700 689 ==== DISABLE_ANTB_PREAMBLE ==== 701 ''(Bit s 3:2 - UFix1_0)'' When asserted, disables the transmission of a preamble from antenna B.690 ''(Bit 2)'' When asserted, disables the transmission of a preamble from antenna B. 702 691 ==== EN_PILOT_SCRAMBLING ==== 703 ''(Bits 4:3 - UFix1_0)'' Enables 802.11-style pilot tone scrambling. When used, pseudo-random sign changes will be applied per OFDM symbol. 692 ''(Bit 3)'' Enables 802.11-style pilot tone scrambling. When used, pseudo-random sign changes will be applied per OFDM symbol. 693 ==== ANTB_PREAMBLE_SHIFT ==== 694 ''(Bits 7:4 - UFix4_0)'' Integer number of samples to shift antenna B's preamble; the shift is circular over the full preamble. 695 ==== TX_SISO_ANTB ==== 696 ''(Bit 8)'' Uses antenna B when in SISO mode; ignored when in MIMO mode. 697 698 ---- 699 == Rx_Gains == 700 === Dir: Read/Write === 701 === Fields: === 702 ==== RX_GAINS_ANTA_BB ==== 703 ''(Bits 4:0 - UFix5_0)'' Antenna A baseband gain, as set by AGC after packet detection. 704 ==== RX_GAINS_ANTA_RF ==== 705 ''(Bits 6:5 - UFix1_0)'' Antenna A RF gain, as set by AGC after packet detection. 706 ==== RX_GAINS_ANTB_BB ==== 707 ''(Bits 12:8 - UFix5_0)'' Antenna B baseband gain, as set by AGC after packet detection. 708 ==== RX_GAINS_ANTB_RF ==== 709 ''(Bits 14:13 - UFix1_0)'' Antenna B RF gain, as set by AGC after packet detection. 704 710 705 711 ---- 706 712 == Rx_BER_Errors == 707 === Address: 0x60 ===708 713 === Dir: Read-only === 709 714 === Fields: === … … 713 718 ---- 714 719 == Rx_BER_TotalBits == 715 === Address: 0x64 ===716 720 === Dir: Read-only === 717 721 === Fields: === … … 721 725 ---- 722 726 == Rx_packet_done == 723 === Address: 0x68 ===724 727 === Dir: Read-only === 725 728 === Fields: === 726 729 ==== RX_GOODPKT ==== 727 ''(Bit s 1:0 - UFix1_0)'' Active high when a good packet is received. This field will only go high when [wiki:OFDM/MIMO/Docs/ModelRegisters#EN_GOODPKT_INT EN_GOODPKT_INT] is enabled and must be cleared by asserting [wiki:OFDM/MIMO/Docs/ModelRegisters#RST_GOODPKT_INT RST_GOODPKT_INT].730 ''(Bit 0 - UFix1_0)'' Active high when a good packet is received. This field will only go high when [wiki:OFDM/MIMO/Docs/ModelRegisters#EN_GOODPKT_INT EN_GOODPKT_INT] is enabled and must be cleared by asserting [wiki:OFDM/MIMO/Docs/ModelRegisters#RST_GOODPKT_INT RST_GOODPKT_INT]. 728 731 ==== RX_BADPKT ==== 729 ''(Bit s 2:1 - UFix1_0)'' Active high when a bad packet is received. This field will only go high when [wiki:OFDM/MIMO/Docs/ModelRegisters#EN_BADPKT_INT EN_BADPKT_INT] is enabled and must be cleared by asserting [wiki:OFDM/MIMO/Docs/ModelRegisters#RST_BADPKT_INT RST_BADPKT_INT].732 ''(Bit 1 - UFix1_0)'' Active high when a bad packet is received. This field will only go high when [wiki:OFDM/MIMO/Docs/ModelRegisters#EN_BADPKT_INT EN_BADPKT_INT] is enabled and must be cleared by asserting [wiki:OFDM/MIMO/Docs/ModelRegisters#RST_BADPKT_INT RST_BADPKT_INT]. 730 733 731 734 ---- 732 735 == Tx_PktDone == 733 === Address: 0x6C ===734 736 === Dir: Read-only === 735 737 ==== TX_PKT_DONE ==== 736 ''(Bit s 1:0 - UFix1_0)'' Active high when a packet transmission is complete. This field can be cleared by toggling [wiki:OFDM/MIMO/Docs/ModelRegisters#TX_PKTDONE_RESET TX_PKTDONE_RESET].738 ''(Bit 0 - UFix1_0)'' Active high when a packet transmission is complete. This field can be cleared by toggling [wiki:OFDM/MIMO/Docs/ModelRegisters#TX_PKTDONE_RESET TX_PKTDONE_RESET].
