wiki:OFDM/MIMO/Docs/ModelSharedMem

MIMO OFDM | Documentation? | Shared Memory Spaces

The WARP MIMO OFDM core is an OPB-compliant peripheral core, created using our sysgen2opb tool. The core utilizes sysgen2opb's shared memory block support, which creates memory blocks in the core which are directly mapped into the address space of the host processor. The OFDM core has three of these shared memory blocks, which are desribed in detail below.

Programmable Modulation Schemes

The second pair of shared memory blocks is used for programming the OFDM core's modulation settings. The WARP MIMO OFDM core implements a flexible modulation scheme. The core allows any combination of modulation schemes across subcarriers and antennas to be used in a given packet. The schemes are programmed by writing a modulation selection for each subcarrier to a shared memory block in the core. Unique schemes can be programmed for the full-rate symbols at antennas A and B and for the base-rate symbols; see OFDM Frame Format for more details about base- and full-rate symbols.

The current version of the OFDM core requires the modulation schemes to be pre-programmed at both the transmitterand receiver. A future revision will include the ability to communicate this information with the header of each packet.

The transmitter and receiver sections of the core have separate modulation selection memory blocks. The organization of these two memory blocks are identical. The C-code below illustrates the memory organization and how user-code can write to these memory blocks. The macros ofdm_TxRx_mimo_SMWO_TxModulation_OFFSET and ofdm_TxRx_mimo_SMWO_TxModulation_OFFSET represent the address offsets (relative to the OFDM core's base address) for the two memory blocks. These macros are defined in the OFDM core's header file, generated by sysgen2opb.

Refer to the warpphy_set_modulation() function in PlatformSupport/WARPMAC/warpphy.c for the C code which writes modulation values to these shared memory blocks.

BER Testing

The OFDM model includes a real-time bit-error rate (BER) testing subsystem. In order to test BER, two nodes must both know the payload of a packet ahead of time. When this packet is received, the Rx PHY compares the received bytes to a stored copy of the known packet. The running count of total bits and bits in error are both available via registers. The known packet payload is stored in a write-only dual-port RAM in the Rx PHY.

Last modified 13 years ago Last modified on Jan 26, 2008, 1:50:46 AM