MIMO OFDM | Documentation? | Shared Memory Spaces

The WARP MIMO OFDM core is an OPB-compliant peripheral core, created using our sysgen2opb tool. The core utilizes sysgen2opb's shared memory block support, which creates memory blocks in the core which are directly mapped into the address space of the host processor. The OFDM core has four of these shared memory blocks, which are desribed in detail below.

Packet Buffers

The first two shared memory blocks function as packet buffers. The OFDM core uses separate buffers for the transmit and receive paths.

Transmit Packet Buffer

The transmit packet buffer is the memory block used for a packet which the user application needs to send over the air. This memory space is a write-only memory block with 4096 bytes of storage (0x1000 bytes). The user application must write an integral number of 32-bit words comprising a packet before enabling transmission. The memory block is accessed by directly writing to the base address of the block's address space. The OFDM core's driver provides a C macro (ofdm_TxRx_mimo_SMWO_TxPktBuffer_OFFSET) which specifies this address relative to the core's base address. The core's base address is provided as a C macro by the EDK during compilation and will usually be named XPAR_OFDM_TXRX_MIMO_OPBW_0_BASEADDR.

This C-code example below illustrates one way of interfacing to the transmit packet buffer. This code is adapted from the OFDM core's driver (ofdm_Tx_mimo.h).

memcpy (
    (unsigned int*)(XPAR_OFDM_TXRX_MIMO_OPBW_0_BASEADDR + ofdm_TxRx_mimo_SMWO_TxPktBuffer_OFFSET),
    (unsigned int*)myPacketPointer,
    myPacketLength
);

Receive Packet Buffer

The receive packet buffer is the memory block used by the user application for reading a packet which which has been received over the air. This memory space is a read-only memory block with 4096 bytes of storage (0x1000 bytes). The user application must read an integral number of 32-bit words comprising a packet. The memory block is accessed by directly read the base address of the block's address space. The OFDM core's driver provides a C macro (ofdm_TxRx_mimo_SMRO_RxPktBuffer_OFFSET) which specifies this address relative to the core's base address. The core's base address is provided as a C macro by the EDK during compilation and will usually be named XPAR_OFDM_TXRX_MIMO_OPBW_0_BASEADDR.

This C-code example below illustrates one way of interfacing to the receive packet buffer. This code is adapted from the OFDM core's driver (ofdm_Rx_mimo.h).

memcpy (
    (unsigned int*)myPacketPointer,
    (unsigned int*)(XPAR_OFDM_TXRX_MIMO_OPBW_0_BASEADDR + ofdm_TxRx_mimo_SMRO_RxPktBuffer_OFFSET),
    myPacketLength
);

Programmable Modulation Schemes

The second pair of shared memory blocks is used for programming the OFDM core's modulation settings. The WARP MIMO OFDM core implements a flexible modulation scheme. The core allows any combination of modulation schemes across subcarriers and antennas to be used in a given packet. The schemes are programmed by writing a modulation selection for each subcarrier to a shared memory block in the core. Unique schemes can be programmed for the full-rate symbols at antennas A and B and for the base-rate symbols; see OFDM Frame Format for more details about base- and full-rate symbols.

The current version of the OFDM core requires the modulation schemes to be pre-programmed at both the transmitterand receiver. A future revision will include the ability to communicate this information with the header of each packet.

The transmitter and receiver sections of the core have separate modulation selection memory blocks. The organization of these two memory blocks are identical. The C-code below illustrates the memory organization and how user-code can write to these memory blocks. The macros ofdm_TxRx_mimo_SMWO_TxModulation_OFFSET and ofdm_TxRx_mimo_SMWO_TxModulation_OFFSET represent the address offsets (relative to the OFDM core's base address) for the two memory blocks. These macros are defined in the OFDM core's driver (ofdm_TxRx_mimo.h).

void setModuation()
{
    //The following modulation schemes match the 802.11a/g standard
    // Each places data on 48 subcarriers
    // Zeros are inserted at the remaining 16 subcarriers:
    //   Subcarrier 0 (DC) must always be zero
    //   Subcarriers 7, 21, -7, -21 are used for pilot tones (i.e. zero data)
    //   Subcarriers [27:31] and [-32:-27] are zero to meet spectral mask requirements

    //The modulation is specified as a vector with 192 4-bit elements
    //The indicies below represent the subcarrier index:
    // x[0:63] specify the full-rate modulation for antenna A
    // x[64:127] specify the full-rate modulation for antenna B
    // x[128:191] specify the base-rate modulation

    //When re-cast as a vector of unsigned ints, the subcarrier indicies are mapped like:
    // [ [7 6 5 4 3 2 1 0] [15 14 13 12 11 10 9 8] [23 22 21 20 19 18 17 16] ...]
    //Thus, 
    //  unsigned int modMasks_qpsk[24] = {0x02222220, 0x22222222, 0x22022222 ...
    //results in zeros at subcarriers 0, 7 and 21...

    //QPSK modulation on 48 subcarriers
    unsigned int modMasks_qpsk[24] = {0x02222220, 0x22222222, 0x22022222, 0x00000222, 0x22000000, 0x22220222, 0x22222222, 0x22222202, 0x02222220, 0x22222222, 0x22022222, 0x00000222, 0x22000000, 0x22220222, 0x22222222, 0x22222202, 0x02222220, 0x22222222, 0x22022222, 0x00000222, 0x22000000, 0x22220222, 0x22222222, 0x22222202};

    //16-QAM on 48 subcarriers
    unsigned int modMasks_16qam[24] = {0x04444440, 0x44444444, 0x44044444, 0x00000444, 0x44000000, 0x44440444, 0x44444444, 0x44444404, 0x04444440, 0x44444444, 0x44044444, 0x00000444, 0x44000000, 0x44440444, 0x44444444, 0x44444404, 0x04444440, 0x44444444, 0x44044444, 0x00000444, 0x44000000, 0x44440444, 0x44444444, 0x44444404};

    //64-QAM on 48 subcarriers
    unsigned int modMasks_64qam[24] = {0x06666660, 0x66666666, 0x66066666, 0x00000666, 0x66000000, 0x66660666, 0x66666666, 0x66666606, 0x06666660, 0x66666666, 0x66066666, 0x00000666, 0x66000000, 0x66660666, 0x66666666, 0x66666606, 0x06666660, 0x66666666, 0x66066666, 0x00000666, 0x66000000, 0x66660666, 0x66666666, 0x66666606};

    unsigned char i;

    for(i=0; i<24; i++)
    {
        //Uncomment one of the following lines to select the modulation scheme at the Transmitter
        *((volatile unsigned int*)(XPAR_OFDM_TXRX_MIMO_OPBW_0_BASEADDR+ofdm_TxRx_mimo_SMWO_TxModulation_OFFSET+i*sizeof(int))) = modMasks_qpsk[i];
        //*((volatile unsigned int*)(XPAR_OFDM_TXRX_MIMO_OPBW_0_BASEADDR+ofdm_TxRx_mimo_SMWO_TxModulation_OFFSET+i*sizeof(int))) = modMasks_16qam[i];
        //*((volatile unsigned int*)(XPAR_OFDM_TXRX_MIMO_OPBW_0_BASEADDR+ofdm_TxRx_mimo_SMWO_TxModulation_OFFSET+i*sizeof(int))) = modMasks_64qam[i];
    }

    for(i=0; i<24; i++)
    {
        //Uncomment one of the following lines to select the modulation scheme at the Receiver
        *((volatile unsigned int*)(XPAR_OFDM_TXRX_MIMO_OPBW_0_BASEADDR+ofdm_TxRx_mimo_SMWO_RxModulation_OFFSET+i*sizeof(int))) = modMasks_qpsk[i];
        //*((volatile unsigned int*)(XPAR_OFDM_TXRX_MIMO_OPBW_0_BASEADDR+ofdm_TxRx_mimo_SMWO_RxModulation_OFFSET+i*sizeof(int))) = modMasks_16qam[i];
        //*((volatile unsigned int*)(XPAR_OFDM_TXRX_MIMO_OPBW_0_BASEADDR+ofdm_TxRx_mimo_SMWO_RxModulation_OFFSET+i*sizeof(int))) = modMasks_64qam[i];
    }
}