Changes between Version 58 and Version 59 of OFDMReferenceDesign/Changelog


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Timestamp:
Nov 16, 2009, 10:22:06 AM (14 years ago)
Author:
murphpo
Comment:

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  • OFDMReferenceDesign/Changelog

    v58 v59  
    99
    1010Download the full XPS project:
    11  * Virtex-II Pro (WARP FPGA Board v1.2): [http://warp.rice.edu/bigFiles/OFDM_ReferenceDesign_FPGAv1_v14.0_public.zip OFDM_ReferenceDesign_FPGAv1_v14.0_public.zip] (12 MB)
    12  * Virtex-4 (WARP FPGA Board v2.2): (coming soon!)
     11 * Virtex-II Pro (WARP FPGA Board v1.2): [http://warp.rice.edu/bigFiles/OFDM_ReferenceDesign_FPGAv1_v14.0_public.zip OFDM_ReferenceDesign_FPGAv1_v14.0_public.zip] (88 MB)
     12 * Virtex-4 (WARP FPGA Board v2.2): [http://warp.rice.edu/bigFiles/OFDM_ReferenceDesign_FPGAv2_v14.0_public.zip OFDM_ReferenceDesign_FPGAv2_v14.0_public.zip] (89MB .zip)
     13
     14'''FPGA Board Version Notes''' [[BR]]
     15The OFDM Reference Design uses very similar hardware designs for the two versions of the WARP FPGA Board (v1 and v2). The primary difference is the use of a soft Ethernet MAC in the Virtex-II Pro FPGA and hard TEMAC in the Virtex-4. The custom WARP peripherals (OFDM transceiver, AGC, timer, radio controller, etc.) are identical in both projects.
     16
     17The software projects are also very similar across boards. The same source files are used for both versions. A few {{{#ifdef}}} statements are used in WARPMAC to include/exclude board-specific code at compile time. The primary difference is support for user I/O. The project for the FPGA Board v1 uses an xps_gpio core as an interface to the LEDs, hex displays, buttons and switches. The FPGA Board v2 project uses the custom [wiki:HardwareUsersGuides/FPGABoard_v2.2/UserIO/warp_v4_userio warp_v4_userio] core and driver for the user I/O. WARPMAC provides a single API for user I/O, so MAC-level code can be fully portable between FPGA Board versions.
     18
     19[[BR]]
     20
     21'''Hardware Changes'''
     22 * Fixed phase tracking bug in the PHY; the bug caused packet errors when imperfect phase estimates were used mid-packet
     23 * Switched to TEMAC + LL_FIFO for the Ethernet interface (replacing ethernet_lite). This hardware design works on both FPGA Board v1 and v2, using a soft TEMAC for v1 and hard TEMAC for v2. The TEMAC and LL_FIFO together provide storage for 4 received packets, which improves the overall performance in systems where many packets may be received at once (like TCP).
     24
     25'''Software Changes'''
     26 * Updated WARPMAC to use new Ethernet hardware
     27 * Updated WARPMAC with new user I/O code for FPGA Board v2. One code file works for both versions, using just a few !#ifdef to compile the correct code.
    1328
    1429'''Using the Design'''
    … …  
    2641 * The four user LEDs are programmed by default to toggle based on packet receptions. The top two LEDs will toggle for each good packet received. The bottom two LEDs will toggle for each bad header or bad payload received.
    2742 * The right seven-segment display is programmed to show the node's ID on boot (set by the DIP switch); the left displays shows the sequence number of received packets.
    28 [[BR]]
    29 
    30 '''Hardware Changes'''
    31  * Fixed phase tracking bug in the PHY; the bug caused packet errors when imperfect phase estimates were used mid-packet
    32  * Switched to TEMAC + LL_FIFO for the Ethernet interface (replacing ethernet_lite). This hardware design works on both FPGA Board v1 and v2, using a soft TEMAC for v1 and hard TEMAC for v2. The TEMAC and LL_FIFO together provide storage for 4 received packets, which improves the overall performance in systems where many packets may be received at once (like TCP).
    33 
    34 '''Software Changes'''
    35  * Updated WARPMAC to use new Ethernet hardware
    36  * Updated WARPMAC with new user I/O code for FPGA Board v2. One code file works for both versions, using just a few !#ifdef to compile the correct code.
    3743
    3844----