Changes between Version 64 and Version 65 of OFDMReferenceDesign/Changelog
- Timestamp:
- Jan 8, 2010, 2:18:03 PM (14 years ago)
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OFDMReferenceDesign/Changelog
v64 v65 8 8 This project requires the latest versions of the 10.1 release of the Xilinx tools (ISE 10.1.03 + IP2, EDK 10.1.03, Sysgen 10.1.3.1386). 9 9 10 '''Minor Revision:''' The Virtex-4 design has been updated to include the MGT Protector Core. 10 Download the full XPS project: 11 * Virtex-II Pro (WARP FPGA Board v1.2): [http://warp.rice.edu/bigFiles/OFDM_ReferenceDesign_FPGAv1_v14.1_public.zip OFDM_ReferenceDesign_FPGAv1_v14.1_public.zip] (86 MB) 12 * Virtex-4 (WARP FPGA Board v2.2): [http://warp.rice.edu/bigFiles/OFDM_ReferenceDesign_FPGAv2_v14.1_public.zip OFDM_ReferenceDesign_FPGAv2_v14.1_public.zip] (87MB) 13 14 '''Hardware Changes''' 15 * Updated the version of the Radio Bridge and Radio Controller cores to v1.22.a 16 * Added the MGT Protector core to the Virtex-4 design to make sure the MGT tiles are always powered on. This is a requirement of the Virtex-4 (see 'Designing with MGTs' in [wiki:HardwareUsersGuides/FPGABoard_v2.2/MGTs Virtex-4 User Guide). 17 18 '''Software Changes''' 19 * No software changes 20 21 '''Using the Design''' 22 * Same as v14.0. See below. 23 24 25 == OFDM Reference Design v14.0 (2009-Nov-15) == 26 The code and models for this design correspond to [source:/@1400 svn rev 1400]. 27 [[BR]] 28 This project requires the latest versions of the 10.1 release of the Xilinx tools (ISE 10.1.03 + IP2, EDK 10.1.03, Sysgen 10.1.3.1386). 11 29 12 30 Download the full XPS project: 13 31 * Virtex-II Pro (WARP FPGA Board v1.2): [http://warp.rice.edu/bigFiles/OFDM_ReferenceDesign_FPGAv1_v14.0_public.zip OFDM_ReferenceDesign_FPGAv1_v14.0_public.zip] (88 MB) 14 * Virtex-4 (WARP FPGA Board v2.2): [http://warp.rice.edu/bigFiles/OFDM_ReferenceDesign_FPGAv2_v14. 1_public.zip OFDM_ReferenceDesign_FPGAv2_v14.1_public.zip] (89MB)32 * Virtex-4 (WARP FPGA Board v2.2): [http://warp.rice.edu/bigFiles/OFDM_ReferenceDesign_FPGAv2_v14.0_public.zip OFDM_ReferenceDesign_FPGAv2_v14.0_public.zip] (89MB) 15 33 16 34 [[BR]] … … 24 42 * Fixed phase tracking bug in the PHY; the bug caused packet errors when imperfect phase estimates were used mid-packet 25 43 * Switched to TEMAC + LL_FIFO for the Ethernet interface (replacing ethernet_lite). This hardware design works on both FPGA Board v1 and v2, using a soft TEMAC for v1 and hard TEMAC for v2. The TEMAC and LL_FIFO together provide storage for 4 received packets, which improves the overall performance in systems where many packets may be received at once (like TCP). 26 * '''Version 14.1:''' Upgraded Radio Bridge and Radio Controller to version 1.22. Added MGT Protector cores for Virtex-4 MGTs.27 44 28 45 '''Software Changes'''