| | 4 | |
| | 5 | == OFDM Reference Design v15.0 (2010-Aug-11) == |
| | 6 | The code and models for this design correspond to [source:/@1580 svn rev 1580]. |
| | 7 | [[BR]] |
| | 8 | This project requires at least the latest versions of the 10.1 release of the Xilinx tools (ISE 10.1.03 + IP3, EDK 10.1.03, Sysgen 10.1.3.1386). |
| | 9 | |
| | 10 | Download the full XPS project: |
| | 11 | * Virtex-II Pro (WARP FPGA Board v1.2): [http://warp.rice.edu/bigFiles/OFDM_ReferenceDesign_FPGAv1_public_v15.0.zip OFDM_ReferenceDesign_FPGAv1_public_v15.0.zip] (100MB) |
| | 12 | * Virtex-4 (WARP FPGA Board v2.2): Coming Soon! (100MB) |
| | 13 | |
| | 14 | '''Hardware Changes''' |
| | 15 | * Rebuilt the Tx pilot insertion logic, to interleave pilots in time and space for Alamouti mode. |
| | 16 | * Rebuilt the Rx phase estimation and tracking systems to improve phase error and CFO performance. |
| | 17 | * Rebuilt the Rx correlator to improve packet detection performance, especially in Alamouti mode with two Tx antennas |
| | 18 | * Fixed random payload generator (it previously results in invalid checksums) |
| | 19 | * Added random payload capture logic, to write random payloads to a packet buffer for offloading via Ethernet for BER processing |
| | 20 | * Built a real CRC-16 calculator for the header checksums (reduces chances of checksum collisions) |
| | 21 | * Fixed bug in AGC core, which (very rarely) resulted in bogus DC offset correction values being applied for many packets in a row |
| | 22 | * Upgraded to clock_board_config_v1_05_a, adding support for run-time selection of local or off board clock sources. |
| | 23 | |
| | 24 | '''Software Changes''' |
| | 25 | * Added support for the [wiki:WARPnet WARPnet Measurement Framework], including a new top-level application (WARPNET_EXAMPLE) |
| | 26 | * Updated warpphy/warpmac to reflect changes to registers in the PHY |
| | 27 | |
| | 28 | '''Using the Design''' |
| | 29 | * Same as v14.0. See below. |
| | 30 | |
| | 31 | ---- |
