| | 4 | == OFDM Reference Design v16.1 (2011-Apr-26) == |
| | 5 | The code and models for this design correspond to [source:/@1663 svn rev 1663]. |
| | 6 | |
| | 7 | Download the full XPS projects: |
| | 8 | * Virtex-II Pro (WARP FPGA Board v1.2): [http://warp.rice.edu/bigFiles/OFDM_ReferenceDesign_FPGAv1_v16.1.zip OFDM_ReferenceDesign_FPGAv1_v16.01.zip] (100MB) |
| | 9 | * Virtex-4 (WARP FPGA Board v2.2): [http://warp.rice.edu/bigFiles/OFDM_ReferenceDesign_FPGAv2_v16.1.zip OFDM_ReferenceDesign_FPGAv2_v16.01.zip] (100MB) |
| | 10 | |
| | 11 | Both projects were built using the latest versions of the 10.1 release of the Xilinx tools (ISE 10.1.03 + IP3, EDK 10.1.03, Sysgen 10.1.3.1386). |
| | 12 | |
| | 13 | '''Hardware Changes''' |
| | 14 | * Added new packet detection subsystem, based on the standard Schmidl/Cox preamble auto-correlation algorithm. This subsystem operates in parallel to the existing RSSI-based detector. The auto-correlation detector cannot detect high-SNR receptions, due to corruption of I/Q pre-AGC, but works well for low-SNR receptions. |
| | 15 | * Fixed random payload capture bug (used for WARPnet BER testing) |
| | 16 | |
| | 17 | '''Software Changes''' |
| | 18 | * Updated warpphy/warpmac to reflect changes to registers in the PHY |
| | 19 | |
| | 20 | |
| | 21 | '''Using the Design''' |
| | 22 | * Same as v16.0 below |
| | 23 | |
| | 24 | ---- |
| 50 | | == OFDM Reference Design v15.0 (2010-Aug-11) == |
| 51 | | The code and models for this design correspond to [source:/@1580 svn rev 1580] for the FPGA v1 design and [source:/@1585 svn rev 1585] for the FPGA v2 design. |
| 52 | | |
| 53 | | Note: The PHY is functionally identical for FPGA v1 and v2. The v2 design uses HDL for 10 multipliers (in the Tx scaling and Rx coarse CFO correction blocks) instead of DSP48's. The V2Pro version of the PHY uses too many multipliers for the V4FX100 FPGA, but the V4 FPGA has more than enough logic to realize the extra multiplications in fabric. |
| 54 | | |
| 55 | | Download the full XPS projects: |
| 56 | | * Virtex-II Pro (WARP FPGA Board v1.2): [http://warp.rice.edu/bigFiles/OFDM_ReferenceDesign_FPGAv1_public_v15.0.zip OFDM_ReferenceDesign_FPGAv1_public_v15.0.zip] (100MB) |
| 57 | | * Virtex-4 (WARP FPGA Board v2.2): [http://warp.rice.edu/bigFiles/OFDM_ReferenceDesign_FPGAv2_public_v15.0.zip OFDM_ReferenceDesign_FPGAv2_public_v15.0.zip] (100MB) |
| 58 | | |
| 59 | | Both projects were built using the latest versions of the 10.1 release of the Xilinx tools (ISE 10.1.03 + IP3, EDK 10.1.03, Sysgen 10.1.3.1386). |
| 60 | | |
| 61 | | |
| 62 | | '''Hardware Changes''' |
| 63 | | * Rebuilt the Tx pilot insertion logic, to interleave pilots in time and space for Alamouti mode. |
| 64 | | * Rebuilt the Rx phase estimation and tracking systems to improve phase error and CFO performance. |
| 65 | | * Rebuilt the Rx correlator to improve packet detection performance, especially in Alamouti mode with two Tx antennas |
| 66 | | * Fixed random payload generator (it previously results in invalid checksums) |
| 67 | | * Added random payload capture logic, to write random payloads to a packet buffer for offloading via Ethernet for BER processing |
| 68 | | * Built a real CRC-16 calculator for the header checksums (reduces chances of checksum collisions) |
| 69 | | * Fixed bug in AGC core, which (very rarely) resulted in bogus DC offset correction values being applied for many packets in a row |
| 70 | | * Upgraded to clock_board_config_v1_05_a, adding support for run-time selection of local or off board clock sources. |
| 71 | | |
| 72 | | '''Software Changes''' |
| 73 | | * Added support for the [wiki:WARPnet WARPnet Measurement Framework], including a new top-level application (WARPNET_EXAMPLE). |
| 74 | | * Updated warpphy/warpmac to reflect changes to registers in the PHY. |
| 75 | | |
| 76 | | '''Using the Design''' |
| 77 | | * Same as v14.0 (see below). |
