| | 1 | [[TracNav(WARPLab/TOC)]] |
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| | 3 | = WARPLab 7.3.0 FPGA Architecture for WARP v3 Hardware = |
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| | 5 | The WARPLab 7.3.0 design for WARP v3 makes changes to the underlying FPGA architecture in order to improve performance for Read / Write IQ. This includes: |
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| | 7 | * Updates to the WARPLab Buffers core to move the Read / Write IQ memories out to the AXI interconnect |
| | 8 | * Updates to the AXI Interconnect to allow DMA access to all the WARPLab Buffers |
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| | 10 | == Interconnect Architecture == |
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| | 12 | [[Image(WARPLab_7_3_0_interconnect_architecture.png)]] |
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| | 15 | == Address Map == |
