Changes between Initial Version and Version 1 of WARPLab/FPGAArchitecture/WARPLAB_7_5_0


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Timestamp:
Feb 6, 2015, 6:07:56 PM (9 years ago)
Author:
welsh
Comment:

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  • WARPLab/FPGAArchitecture/WARPLAB_7_5_0

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     1[[TracNav(WARPLab/TOC)]]
     2
     3= WARPLab 7.5.0 FPGA Architecture for WARP v3 Hardware =
     4
     5The WARPLab 7.5.0 design for WARP v3 makes changes to the underlying FPGA architecture in order to increase the buffer sizes for Read / Write IQ.  This includes:
     6
     7  * Updates to the WARPLab Buffers core to allow for larger Read / Write IQ indexing
     8  * Updates to the WARPLab Buffers core to allow DMA access to RSSI buffers
     9  * Updates to the Trigger Manager core to allow for Ethernet triggers on Eth B
     10  * Updates to the AGC core (slight modification of the 802.11 AGC core)
     11  * Updates to Ethernet B so that it has the same capabilities as Ethernet A
     12  * Updates to the AXI Interconnect to address all 2GB of DDR
     13
     14== Interconnect Architecture ==
     15
     16[[Image(WARPLab_7_5_0_interconnect_architecture.png)]]
     17
     18
     19== Address Map ==
     20
     21  Please review the XPS project for the latest information. 
     22
     23
     24=== Microblaze Address Map ===
     25
     26'''NOTE:  All Address not explicitly defined are reserved.'''
     27
     28||= '''IP Instance''' =||= '''Base Address''' =||= '''High Address''' =||= '''Size''' =||
     29|| DLMB || 0x0000_0000 || 0x0001_FFFF || 128K ||
     30|| ILMB || 0x0000_0000 || 0x0001_FFFF || 128K ||
     31|| Interrupt Controller || 0x1000_0000 || 0x1000_FFFF || 64K ||
     32|| WARPLab Trigger Proc || 0x1010_0000 || 0x1010_FFFF || 64K ||
     33|| WARPLab AGC || 0x1020_0000 || 0x1020_FFFF || 64K ||
     34|| WARPLab Buffers || 0x1030_0000 || 0x1030_FFFF || 64K ||
     35|| ETH A MAC || 0x1100_0000 || 0x1103_FFFF || 256K ||
     36|| ETH B MAC || 0x1110_0000 || 0x1113_FFFF || 256K ||
     37|| AXI DMA (ETH A) || 0x1120_0000 || 0x1120_FFFF || 64K ||
     38|| AXI DMA (ETH B) || 0x1130_0000 || 0x1130_FFFF || 64K ||
     39|| CDMA || 0x1200_0000 || 0x1200_FFFF || 64K ||
     40|| W3 Clock Controller || 0x2010_0000 || 0x2010_FFFF || 64K ||
     41|| W3 User IO || 0x2020_0000 || 0x2020_FFFF || 64K ||
     42|| Radio Controller || 0x2030_0000 || 0x2030_FFFF || 64K ||
     43|| W3 AD Controller || 0x2040_0000 || 0x2040_FFFF || 64K ||
     44|| AXI GPIO || 0x2050_0000 || 0x2050_FFFF || 64K ||
     45|| AXI SYSMON ADC || 0x2060_0000 || 0x2060_FFFF || 64K ||
     46|| AXI Timer || 0x2070_0000 || 0x2070_FFFF || 64K ||
     47|| USB UART || 0x2080_0000 || 0x2080_FFFF || 64K ||
     48|| W3 I2C EEPROM On Board || 0x2090_0000 || 0x2090_FFFF || 64K ||
     49|| W3 I2C EEPROM FMC || 0x20A0_0000 || 0x20A0_FFFF || 64K ||
     50|| RFA RX CTL || 0x4100_0000 || 0x4101_FFFF || 128K ||
     51|| RFA RSSI CTL || 0x4102_0000 || 0x4102_3FFF || 16K ||
     52|| RFA TX CTL || 0x4104_0000 || 0x4105_FFFF || 128K ||
     53|| RFB RX CTL || 0x4108_0000 || 0x4109_FFFF || 128K ||
     54|| RFB RSSI CTL || 0x410A_0000 || 0x410A_3FFF || 16K ||
     55|| RFB TX CTL || 0x410C_0000 || 0x410D_FFFF || 128K ||
     56|| RFC RX CTL || 0x4110_0000 || 0x4111_FFFF || 128K ||
     57|| RFC RSSI CTL || 0x4112_0000 || 0x4112_3FFF || 16K ||
     58|| RFC TX CTL || 0x4114_0000 || 0x4115_FFFF || 128K ||
     59|| RFD RX CTL || 0x4118_0000 || 0x4119_FFFF || 128K ||
     60|| RFD RSSI CTL || 0x411A_0000 || 0x411A_3FFF || 16K ||
     61|| RFD TX CTL || 0x411C_0000 || 0x411D_FFFF || 128K ||
     62|| BRAM || 0x5000_0000 || 0x5001_FFFF || 128K ||
     63|| DDR ||  0x8000_0000 || 0xFFFF_FFFF || 2G ||
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