Changes between Version 2 and Version 3 of cores/fmc_bb_4da_bridge


Ignore:
Timestamp:
Feb 18, 2013, 10:35:45 PM (11 years ago)
Author:
murphpo
Comment:

--

Legend:

Unmodified
Added
Removed
Modified

  • cores/fmc_bb_4da_bridge

    v2 v3  
    11= FMC-BB-4DA Bridge (fmc_bb_4da_bridge) =
    2 
    3 The latest revision of the core is v1.00.a, available in the repository: [source:/PlatformSupport/CustomPeripherals/pcores/fmc_bb_4da_bridge_v1_00_a fmc_bb_4da_bridge_v1_00_a].
    42
    53The fmc_bb_4da_bridge core implements the output logic for interfacing user designs with the digital interfaces of the AD9116 DACs on the FMC-BB-4DA module. The AD9116 digital ports are double data rate (DDR) interfaces with interleaved I/Q. The fmc_bb_4da_bridge core uses ODDR primitives in the FPGA IOBs to efficiently translate between the external interleaved ports and internal separate busses. One fmc_bb_4da_bridge instance implements the digital interfaces for both AD9116 devices on the FMC-BB-4DA module.
    … …  
    75The fmc_bb_4da_bridge core is packaged as a pcore to be instantiated in an XPS project. The design has been tested in hardware using Xilinx ISE 13.4. The fmc_bb_4da_bridge core does not attach to a processor bus, so there is no driver.
    86
    9 The current version of the fmc_bb_4da_bridge core is [source:/PlatformSupport/CustomPeripherals/pcores/fmc_bb_4da_bridge fmc_bb_4da_bridge v1_00_a].
     7The latest revision of the core is v1.00.b, available in the repository: [source:/PlatformSupport/CustomPeripherals/pcores/fmc_bb_4da_bridge_v1_00_b fmc_bb_4da_bridge_v1_00_b].
    108
    119----
    … …  
    4947== Source ==
    5048
    51 The full hardware and software source code is available in the repository: source:/PlatformSupport/CustomPeripherals/pcores/fmc_bb_4da_bridge_v1_00_a]. The Verilog source code is made available under the [wiki:/license WARP license].
     49The full hardware and software source code is available in the repository: source:/PlatformSupport/CustomPeripherals/pcores/fmc_bb_4da_bridge_v1_00_b]. The Verilog source code is made available under the [wiki:/license WARP license].
    5250