Changes between Version 1 and Version 2 of cores/w3_ad_bridge


Ignore:
Timestamp:
Aug 12, 2012, 2:57:53 PM (12 years ago)
Author:
murphpo
Comment:

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  • cores/w3_ad_bridge

    v1 v2  
    88
    99== Tx Path ==
     10The w3_ad_bridge Tx path is illustrated below. The logic depicted here is replicated for each RF interface.
    1011
     12[[Image(wiki:cores/w3_ad_bridge/files:w3_adBridge_Tx.png, nolink)]]
     13
     14'''External Ports:'''
     15||= Port =||= Direction =||= Width =||= Connection =||= Description =||
     16|| ad_RFA_TXD || Output || 12 || AD9963 TXD || RF A Tx data (DDR, I/Q interleaved) ||
     17|| ad_RFA_TXCLK || Output || 1 || AD9963 TXCLK || RF A Tx data clock ||
     18|| ad_RFA_TXIQ || Output || 1 || AD9963 TXIQ || RF A Tx data select ||
     19|| ad_RFB_TXD || Output || 12 || AD9963 TXD || RF B Tx data (DDR, I/Q interleaved) ||
     20|| ad_RFB_TXCLK || Output || 1 || AD9963 TXCLK || RF B Tx data clock ||
     21|| ad_RFB_TXIQ || Output || 1 || AD9963 TXIQ || RF B Tx data select ||
     22
     23
     24'''Internal Ports:'''
     25||= Port =||= Direction =||= Width =||= Description =||
     26|| user_RFA_TXD_I || Input || 12 || Tx I samples from user design ||
     27|| user_RFA_TXD_Q|| Input || 12 || Tx I samples from user design ||
     28|| sys_samp_clk_Tx || Input || 1 || Clock for user-supplied TXD signals ||
     29|| sys_samp_clk_Tx_90 || Input || 1 || 90 degree phase shifted version of sys_samp_clk_Tx ||
     30
     31
     32== Rx Path ==
     33
     34[[Image(wiki:cores/w3_ad_bridge/files:w3_adBridge_Rx.png, nolink)]]
    1135
    1236== Hardware ==
    … …  
    2953 * Created w3_ad_bridge_v3_00_g, branched from w3_ad_bridge_v3_00_f
    3054  * Separate sys_samp_clk ports for Tx/Rx paths, to enable different ADC/DAC data rates
    31