Changes between Version 2 and Version 3 of cores/w3_ad_bridge

Timestamp:

Aug 12, 2012, 3:02:14 PM (12 years ago)

Author:

murphpo

Comment:

--

cores/w3_ad_bridge

@@ -16 +16 @@
 || ad_RFA_TXD || Output || 12 || AD9963 TXD || RF A Tx data (DDR, I/Q interleaved) ||
 || ad_RFA_TXCLK || Output || 1 || AD9963 TXCLK || RF A Tx data clock ||
-|| ad_RFA_TXIQ || Output || 1 || AD9963 TXIQ || RF A Tx data select ||
+|| ad_RFA_TXIQ || Output || 1 || AD9963 TXIQ || RF A Tx data select (not used) ||
 || ad_RFB_TXD || Output || 12 || AD9963 TXD || RF B Tx data (DDR, I/Q interleaved) ||
 || ad_RFB_TXCLK || Output || 1 || AD9963 TXCLK || RF B Tx data clock ||
-|| ad_RFB_TXIQ || Output || 1 || AD9963 TXIQ || RF B Tx data select ||
+|| ad_RFB_TXIQ || Output || 1 || AD9963 TXIQ || RF B Tx data select  (not used) ||
 
 
 '''Internal Ports:'''
 ||= Port =||= Direction =||= Width =||= Description =||
-|| user_RFA_TXD_I || Input || 12 || Tx I samples from user design ||
-|| user_RFA_TXD_Q|| Input || 12 || Tx I samples from user design ||
 || sys_samp_clk_Tx || Input || 1 || Clock for user-supplied TXD signals ||
 || sys_samp_clk_Tx_90 || Input || 1 || 90 degree phase shifted version of sys_samp_clk_Tx ||
+|| user_RFA_TXD_I || Input || 12 || RF A Tx I samples from user design ||
+|| user_RFA_TXD_Q|| Input || 12 || RF A Tx Q samples from user design ||
+|| user_RFA_TXIQ || Input || 1 || RF A Tx I/Q select (not used) ||
+|| user_RFB_TXD_I || Input || 12 || RF B Tx I samples from user design ||
+|| user_RFB_TXD_Q|| Input || 12 || RF B Tx Q samples from user design ||
+|| user_RFB_TXIQ || Input || 1 || RF B Tx I/Q select (not used) ||