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Hello. I want to connect an external clock to WARP through the clock module header. But I am not sure whether my clock is compatible with the WARP circuit. I have gone though some related post in this forum. But they are about older version of WARP board or older version of reference design; so I am afraid those post may not apply to my case.
I am using WARP v3 and running my experiment based on the 802.11 reference design v1.3.0. The frequency of my clock is 20MHz. The voltage is 3.3V. The pulse is rectangular. I want to supply this clock to both the sampling clock and RF reference clock of WARP.
Question 1 (voltage compatibility): I think the frequency and the pulse are OK with WARP. But I am not sure whether WARP clock module header can accept 3.3V clock input. According to the Mango_CM-MMCX_rev1.0_schematic, the signal RFCLKBUF_CLK2IN_N is connected to pin 38 of the LSHM-120 strip. According to WARP v3 User Guide: Clocking, the pin 38 of the LSHM-120 strip requires 2.5V input. Therefore, I think I need to have 2.5V at RFCLKBUF_CLK2IN_N. I notice that there is a AC coupling cap MC_TC1-1T between the MMCX clock input RF_CLK_IN and the RFCLKBUF_CLK2IN_N. I cannot find the datasheet of the AC coupling cap MC_TC1-1T. So, when my clock is 3.3V, what will the output be? I guess the output will be less than 3.3V but still higher than 2.5V. Is it OK?
Question 2 (one clock driving both RF and sampling clock): I want to supply my clock to both the sampling clock and RF reference clock of WARP. But I have some doubts about how to connect my clock and the clock module header with MMCX cables. If I connect my clock output to the 'RF ref in' (J2) of the clock module header, will there be a clock output the same as my clock at the 'RF ref out' (J1)? If so, can I connect 'RF ref out' (J1) and 'Samp in' (J4) to realize driving both the RF reference clock and the sampling clock simultaneously with my clock?
However, I notice that there is a resistor 'R5' between the SAMP_CLK_IN and RF_CLK_IN. How large is the resistance? If the resistance is small, I think I can just connect my clock to J2 (without connecting J1 and J4), and then both the RF reference clock and the sampling clock will be driven by my clock. Am I right?
Question 3 (required modifications to the UCF and C program). Since my clock is 20MHz, which parts of the UCF file and the C program should I make changes to, such that both the RF reference clock and the sampling clock can have the correct frequency?
Thanks a lot.
Last edited by adherentx (2016-Jan-07 08:15:03)
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A few things:
-Using a 20MHz clock will require a re-design of clocking throughout the 802.11 Reference Design. The design assumes an 80MHz reference clock. The 80MHz is divided to 40MHz for the ADCs/DACs and to 20MHz for the RF reference. The 80MHz clock is also routed to the FPGA where it drives MMCMs to generate all the logic clocks (160 / 80 / 20 MHz). If you must use a 20MHz external clock, the CM-PLL would be a better option. The CM-PLL uses the off-board clock is a frequency reference (10MHz by default, 20MHz would also work) to discipline an 80MHz VCO.
-The ref design assumes valid clocks are driven to both CM-MMCX inputs. In theory you could connect one CM-MMCX output to the other CM-MMCX input, but this is not a configuration we have tested. It is also possible to use the on-board oscillator for one clock and the CM-MMCX input for the other. This would require modifying the clock_controller config.
Perhaps you can describe what kind of synchronization you're trying to achieve? There might be an easier way that the processes above.
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In my experiment, I want everything on the WARP board to be driven by the same source clock (with PLLs in between). And I want to test the performance when using different source clocks. I want to use GPSDO to have better synchronization than the clock on WARP. The CM-PLL seems to be convenient, but I am worried that the 80MHz VCO may not be as accurate as the GPSDO.
1. Suppose I have clocks of any frequencies, then what frequencies should I input to the 'RF ref in' and 'Samp in' of the CM-MMCX clock module header, such that the software does not require any changes? Both the two should be 80MHz?
2. I can also use a 40MHz external GPSDO clock. Then I think the CM-MMCX clock module header can also work, since the 40MHz can be divided by 1 before supplying to ADC/DAC. Am I right?
3. By the way, please also answer my Question 1 above about the voltage. Thanks.
4. From my understanding, after I input 40MHz to both the RF ref clock and sampling clock through the CM-MMCX clock module header, I can configure the frequency dividers for the RF and sampling clocks in the following way. Please point out whether I am wrong. Also, could you please give me some tips on how to change any parts of the program such that the FPGA work at 160MHz as before?
In wlan_phy_util.c:
void wlan_radio_init() {
clk_config_dividers(CLK_BASEADDR, 1, (CLK_SAMP_OUTSEL_AD_RFA | CLK_SAMP_OUTSEL_AD_RFB));
clk_config_dividers(CLK_BASEADDR, 1, (CLK_RFREF_OUTSEL_RFAB | CLK_RFREF_OUTSEL_FMC | CLK_RFREF_OUTSEL_CLKMODHDR));
ad_config_clocks(AD_BASEADDR, AD_ALL_RF, AD_DACCLKSRC_EXT, AD_ADCCLKSRC_EXT, AD_ADCCLKDIV_1, AD_DCS_OFF);
ad_config_filters(AD_BASEADDR, AD_ALL_RF, 2, 2);
}In radio_controller_basic.c:
void WarpRadio_v1_Reset(unsigned int* baseaddress, unsigned int clkRatio) {
// Setup for 40MHz radio reference clock
transmit(0x18245);
REG_RAD1_BAND_SELECT = (short)0x1824;
REG_RAD2_BAND_SELECT = (short)0x1824;
REG_RAD3_BAND_SELECT = (short)0x1824;
REG_RAD4_BAND_SELECT = (short)0x1824;
}murphpo wrote:
A few things:
-Using a 20MHz clock will require a re-design of clocking throughout the 802.11 Reference Design. The design assumes an 80MHz reference clock. The 80MHz is divided to 40MHz for the ADCs/DACs and to 20MHz for the RF reference. The 80MHz clock is also routed to the FPGA where it drives MMCMs to generate all the logic clocks (160 / 80 / 20 MHz). If you must use a 20MHz external clock, the CM-PLL would be a better option. The CM-PLL uses the off-board clock is a frequency reference (10MHz by default, 20MHz would also work) to discipline an 80MHz VCO.
-The ref design assumes valid clocks are driven to both CM-MMCX inputs. In theory you could connect one CM-MMCX output to the other CM-MMCX input, but this is not a configuration we have tested. It is also possible to use the on-board oscillator for one clock and the CM-MMCX input for the other. This would require modifying the clock_controller config.
Perhaps you can describe what kind of synchronization you're trying to achieve? There might be an easier way that the processes above.
Last edited by adherentx (2016-Jan-07 23:23:11)
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The CM-PLL seems to be convenient, but I am worried that the 80MHz VCO may not be as accurate as the GPSDO.
The CM-PLL implements a PLL+VCO circuit. The frequency of the VCO will follow the frequency of the reference clock you provide. If you drive a common 10MHz reference clock to two CM-PLL modules, the two VCOs will operate at exactly the same frequency, but will filter out most of the phase noise from the reference clock.
1. Suppose I have clocks of any frequencies, then what frequencies should I input to the 'RF ref in' and 'Samp in' of the CM-MMCX clock module header, such that the software does not require any changes? Both the two should be 80MHz?
If you drive 80MHz clocks to the CM-MMCX you could use the 802.11 and WARPLab ref designs without modifying the FPGA designs. The ref designs support synchronized WARP v3 nodes where the CM-MMCX outputs of one node are connected directly to the CM-MMCX inputs of another node.
2. I can also use a 40MHz external GPSDO clock. Then I think the CM-MMCX clock module header can also work, since the 40MHz can be divided by 1 before supplying to ADC/DAC. Am I right?
Yes, however this would still require modfiying the FPGA design. The WARPLab and 802.11 designs assume an 80MHz clock at the FPGA input pins. This 80MHz clock is multiplied/divided by MMCMs (inside the clock_generator cores in the XPS project) to generate all the on-chip clocks. The clock_generator core is parameterized with the input and output frequencies. In the 802.11 system.mhs, for example, the ad_refclk_in net represents the 80MHz clock input. The 80MHz value is set for the top-level PORTs (samp_clk_p and samp_clk_n) and for the C_CLKIN_FREQ param of the clk_gen_proc_bus_clks core.
3. By the way, please also answer my Question 1 above about the voltage. Thanks.
Sorry, I missed this before. The CM-MMCX inputs are converted to differential signals via the T1/T2 transformers, then driven directly into the AD9512 inputs on the WARP v3 board. A 3.3v input won't damage the input circuits, but (depending on the driver and frequency) might exceed the AD9512's recommended 2Vp-p max input level. I would suggest attenuating the 3.3v level down to ~2v or so to avoid the jitter implications of exceeding the AD9512's 2Vp-p recommendation.
4. From my understanding, after I input 40MHz to both the RF ref clock and sampling clock through the CM-MMCX clock module header, I can configure the frequency dividers for the RF and sampling clocks in the following way. Please point out whether I am wrong. Also, could you please give me some tips on how to change any parts of the program such that the FPGA work at 160MHz as before?
The change to wlan_phy_util.c (setting divide=1 for the sampling clock buffer -> AD/DA) is right, assuming a 40MHz input.
You do not need to modify the radio_controller driver (in fact, the code you posted above is from the old radio_controller for WARP v1/v2).
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I used an oscilloscope to test the output of my clock. The voltage is 2V-pp, and the frequency is 80MHz. The clock is fine, and the accuracy will not be a problem. I used two cables to connect the clock output to the two inputs on the CM-MMCX header. In w3_node_init(), I configure by
clk_config_input_rf_ref(CLK_BASEADDR, CLK_INSEL_CLKMOD);
to select my external clock as the RF clock source.
It works. My two WARPs can get associated.
However, there is a lot of decoding error, and the CFO values (retrieved from PHY) are also very weird, jumping from -10kHz to +10kHz. There must be something wrong with the clock configuration. I have tried putting the switch on the CM-MMCX header to all directions, but the problem is still the same as long as I select my external clock as the RF clock source. Any ideas?
Last edited by adherentx (2016-Jan-17 08:55:42)
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Can you clarify your hardware setup? Are you driving both inputs (Sampling & RF Ref) of CM-MMCX modules on two nodes? Or just the RF Ref inputs on two nodes?
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murphpo wrote:
Can you clarify your hardware setup? Are you driving both inputs (Sampling & RF Ref) of CM-MMCX modules on two nodes? Or just the RF Ref inputs on two nodes?
I have tried the following different settings. All of them have the same problem (many decoding error, large and random CFO values).
1. Drive both sampling and RF ref with my external clocks (an independent one for each of A and B) through the CM-MMCX modules on both WARP nodes A and B.
2. Drive both sampling and RF ref with my external clock through the CM-MMCX module on WARP node A; drive both sampling and RF ref with the on-board clock on WARP node B.
3. Drive the sampling with the on-board clocks on both WARP nodes A and B; drive the RF ref with my external clock through the CM-MMCX modules on both WARP nodes A and B.
4. Drive both the sampling and RF ref with the on-board clock on WARP node A; drive the sampling with the on-board clock and the RF ref with my external clock on WARP node B.
However, when I tried the following, the communications worked normally.
5. Drive the RF ref with the same external clock to both WARP nodes A and B. The clock source of the sampling does not matter.
Last edited by adherentx (2016-Jan-18 10:09:00)
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The 802.11 ref design implements the same clock module modes as the WARPLab Reference design, documented in the WARPLab user guide.
If you drive 80MHz clocks to both CM-MMCX inputs, you can use the "Daisy Chain: Last" configuration (CM-MMCX switches down/down). You must ensure the clock signals are stable before configuring the FPGA with the 802.11 Reference Design bitstream. Immediately after the FPGA is configured the UART will print the clock module configuration. You may need to scroll up in your UART terminal to see this. You should verify that this UART output matches your expected configuration (CM-MMCX "Configuration C", as described in the w3_clock_controller docs).
Other combinations of clock inputs / switch settings may result in good Tx/Rx, though with sampling/carrier frequency offsets.
I would suggest starting with two nodes using the local clocks and verify the Tx/Rx works normally. Then try clocking one node using your external clock source. Again, the nodes should communicate normally. Then try clocking both nodes with your external clock.
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murphpo wrote:
The 802.11 ref design implements the same clock module modes as the WARPLab Reference design, documented in the WARPLab user guide.
If you drive 80MHz clocks to both CM-MMCX inputs, you can use the "Daisy Chain: Last" configuration (CM-MMCX switches down/down). You must ensure the clock signals are stable before configuring the FPGA with the 802.11 Reference Design bitstream. Immediately after the FPGA is configured the UART will print the clock module configuration. You may need to scroll up in your UART terminal to see this. You should verify that this UART output matches your expected configuration (CM-MMCX "Configuration C", as described in the w3_clock_controller docs).
Other combinations of clock inputs / switch settings may result in good Tx/Rx, though with sampling/carrier frequency offsets.
I would suggest starting with two nodes using the local clocks and verify the Tx/Rx works normally. Then try clocking one node using your external clock source. Again, the nodes should communicate normally. Then try clocking both nodes with your external clock.
I am suspecting the problem may lie in the AC coupling with the transformers. My external clock is 80MHz square wave. The clock signal may not pass the transformer well. Can you provide me with the datasheet or some parameters of the transformers? Thanks.
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The CM-MMCX clock inputs use Minicircuits TC1-1TG2+ transformers, both to ac-couple the input and to convert the single-ended input to a differential signal for driving the AD9512 clock inputs. The transformers should pass an 80MHz clock ok. The transformer presents a 50-ohm load to the circuit driving the input. Is your input 2V into 50 ohms? Or 2V unterminated?
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murphpo wrote:
The CM-MMCX clock inputs use Minicircuits TC1-1TG2+ transformers, both to ac-couple the input and to convert the single-ended input to a differential signal for driving the AD9512 clock inputs. The transformers should pass an 80MHz clock ok. The transformer presents a 50-ohm load to the circuit driving the input. Is your input 2V into 50 ohms? Or 2V unterminated?
After testing the clock output with a good scope, I am not almost sure that the problem should be the my clock. The clock is an OCXO + a frequency converter. It turns out that the frequency converter is lousy. I am now thinking about purchasing your PLL clock module.
Have you done any tests on the accuracy of the CM-PLL module? I want to make sure the output will not be worse than the input by too much.
Last edited by adherentx (2016-Jan-19 09:23:54)
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