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I am trying to integrate the files of WARPLAB (that you put in the repository) in XPS and I ran into some problems.
First, after using sysgen2opb and WARP OPB Export tool, I compared the generated header file with the one in your xps project and found the following lines missing:
//Shared Memory Address #define warplab_mimo_2x2_SMRO_RSSIBuff_Radio2_OFFSET (WARPLAB_MIMO_2X2_OFFSET+0x10000) #define warplab_mimo_2x2_SMRO_RxBuff_Radio2_OFFSET (WARPLAB_MIMO_2X2_OFFSET+0x20000) #define warplab_mimo_2x2_SMRO_RSSIBuff_Radio3_OFFSET (WARPLAB_MIMO_2X2_OFFSET+0x30000) #define warplab_mimo_2x2_SMRO_RxBuff_Radio3_OFFSET (WARPLAB_MIMO_2X2_OFFSET+0x40000) #define warplab_mimo_2x2_SMWO_TxBuff_Radio2_OFFSET (WARPLAB_MIMO_2X2_OFFSET+0x50000) #define warplab_mimo_2x2_SMWO_TxBuff_Radio3_OFFSET (WARPLAB_MIMO_2X2_OFFSET+0x60000) //Write Reg Macro #define warplab_mimo_2x2_WriteReg_SMRO_RSSIBuff_Radio2(BaseAddress, Value) \ XIo_Out32((BaseAddress) + (warplab_mimo_2x2_SMRO_RSSIBuff_Radio2_OFFSET), (Xuint32)(Value)) #define warplab_mimo_2x2_WriteReg_SMRO_RxBuff_Radio2(BaseAddress, Value) \ XIo_Out32((BaseAddress) + (warplab_mimo_2x2_SMRO_RxBuff_Radio2_OFFSET), (Xuint32)(Value)) #define warplab_mimo_2x2_WriteReg_SMWO_TxBuff_Radio2(BaseAddress, Value) \ XIo_Out32((BaseAddress) + (warplab_mimo_2x2_SMWO_TxBuff_Radio2_OFFSET), (Xuint32)(Value)) #define warplab_mimo_2x2_WriteReg_SMRO_RSSIBuff_Radio3(BaseAddress, Value) \ XIo_Out32((BaseAddress) + (warplab_mimo_2x2_SMRO_RSSIBuff_Radio3_OFFSET), (Xuint32)(Value)) #define warplab_mimo_2x2_WriteReg_SMRO_RxBuff_Radio3(BaseAddress, Value) \ XIo_Out32((BaseAddress) + (warplab_mimo_2x2_SMRO_RxBuff_Radio3_OFFSET), (Xuint32)(Value)) #define warplab_mimo_2x2_WriteReg_SMWO_TxBuff_Radio3(BaseAddress, Value) \ XIo_Out32((BaseAddress) + (warplab_mimo_2x2_SMWO_TxBuff_Radio3_OFFSET), (Xuint32)(Value)) //Read Reg Macro #define warplab_mimo_2x2_ReadReg_SMRO_RSSIBuff_Radio2(BaseAddress) \ XIo_In32((BaseAddress) + (warplab_mimo_2x2_SMRO_RSSIBuff_Radio2_OFFSET)) #define warplab_mimo_2x2_ReadReg_SMRO_RxBuff_Radio2(BaseAddress) \ XIo_In32((BaseAddress) + (warplab_mimo_2x2_SMRO_RxBuff_Radio2_OFFSET)) #define warplab_mimo_2x2_ReadReg_SMWO_TxBuff_Radio2(BaseAddress) \ XIo_In32((BaseAddress) + (warplab_mimo_2x2_SMWO_TxBuff_Radio2_OFFSET)) #define warplab_mimo_2x2_ReadReg_SMRO_RSSIBuff_Radio3(BaseAddress) \ XIo_In32((BaseAddress) + (warplab_mimo_2x2_SMRO_RSSIBuff_Radio3_OFFSET)) #define warplab_mimo_2x2_ReadReg_SMRO_RxBuff_Radio3(BaseAddress) \ XIo_In32((BaseAddress) + (warplab_mimo_2x2_SMRO_RxBuff_Radio3_OFFSET)) #define warplab_mimo_2x2_ReadReg_SMWO_TxBuff_Radio3(BaseAddress) \ XIo_In32((BaseAddress) + (warplab_mimo_2x2_SMWO_TxBuff_Radio3_OFFSET))
Have you added them manually?
Another matter, the generated warplab_mimo_2x2_opbw core shows more ports in xps than your core does in your xps project. Here are the lines of my MPD file that shows the extra ports:
PORT smroaddr_rssibuff_radio2 = "", DIR = I, VEC = [0:10] PORT smroaddr_rssibuff_radio3 = "", DIR = I, VEC = [0:10] PORT smroaddr_rxbuff_radio2 = "", DIR = I, VEC = [0:13] PORT smroaddr_rxbuff_radio3 = "", DIR = I, VEC = [0:13] PORT smwoaddr_txbuff_radio2 = "", DIR = I, VEC = [0:13] PORT smwoaddr_txbuff_radio3 = "", DIR = I, VEC = [0:13] PORT smwodatai_txbuff_radio2 = "", DIR = I, VEC = [0:31] PORT smwodatai_txbuff_radio3 = "", DIR = I, VEC = [0:31] PORT smwowe_txbuff_radio2 = "", DIR = I PORT smwowe_txbuff_radio3 = "", DIR = I PORT smrodatao_rssibuff_radio2 = "", DIR = O, VEC = [0:31] PORT smrodatao_rssibuff_radio3 = "", DIR = O, VEC = [0:31] PORT smrodatao_rxbuff_radio2 = "", DIR = O, VEC = [0:31] PORT smrodatao_rxbuff_radio3 = "", DIR = O, VEC = [0:31]
What could have been gone wrong? Do I just delete these lines?
Finally, I would like to know how to change the hardware version of a core (e.g. use radio_controller v1.09.a instead of radio_controller v1.10.a). Do I just change the HW_VER paramter in the MHS file and regenerate the bitstream?
I am using XPS9.1, Sysgen 9.1 and MATLAB 2006b.
Thanks
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The missing #define statements and ports correspond to the shared memory blocks in the Sysgen model. You have to pass an extra parameter to sysgen2opb to enable the shared memory mode.
>> sysgen2opb('myModel', 'smon')See sysgen2opb's documentation for details.
Also, a word of warning- there's a known bug in the header file generation code for shared memory blocks. If you re-generate the WARPLab sysgen core, you'll notice that the auto-generated address offsets for the shared memory blocks differ from the ones in the WARPLab reference design. We corrected the header file by hand so the offsets matched the actual address decoding logic.
hassan.ghozlan wrote:
Finally, I would like to know how to change the hardware version of a core (e.g. use radio_controller v1.09.a instead of radio_controller v1.10.a). Do I just change the HW_VER paramter in the MHS file and regenerate the bitstream?
The HW_VER parameter in the MHS is all you have to change. You probably want to update the DRIVER_VER parameter for the corresponding driver in the MSS file as well.
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