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Hi there,
I've changed the mdl file to add a small module on the lts correlation output that extends a pulse into square wave. The width of the wave is determined by a counter with a threshold of 200. In the simulation, the width of the square wave is around 20 samples, assuming the two lts correlation peaks are 64 samples apart. The question is:
1. Generally, is the simulation a precise description of what's happening in the real design when receiving the same signals?
2. What clock does the simulation use? Is it the same as the board uses such that the counter will determine a same amount of time on the board as in the simulation?
3. In the mdl file, do you have any other "time aware" design that i can refer to?
Many thanks
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The System Sample Period is the relative sample period of the fastest clock in the design. I'd suggest studying the Sysgen users guide's section on clocking, which explains the overall clocking model in the Sysgen design flow. In some places Simulink uses the unit 'seconds' for the system sample period. This does not represent real time. I prefer to think of the sample periods in Simulink as relative to 1, where 1 is the fastest clock (lowest period) and slower logic runs at multiples of this period (T=2 -> half of the fastest clock, etc.).
In the 802.11 Tx and Rx PHY models the fastest sample period is 1. In hardware this corresponds to a 160MHz clock. This is achieved by tying the 'sysgen_clk' port of the Tx/Rx PHY cores to a 160MHz clock signal in the XPS design.
System Generator guarantees bit and cycle accurate simulations of the eventual hardware design. If your logic changes state after 20 ticks in simulation, it will do the same in hardware.
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