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#1 2015-Nov-24 20:27:49

wenchao88
Member
Registered: 2015-Aug-22
Posts: 26

FPGA pin and reference design

Hi,

I am running WARP reference design. In the reference design, can we use the 16 FGPA pin in the user I/O area to know when a WARP beacon is transmitted? I heard that there will be a trigger in the FPGA pin when a beacon is transmitted. I do not know whether that is true and how to set. Thank you.

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#2 2015-Nov-24 22:51:07

welsh
Administrator
From: Mango Communications
Registered: 2013-May-15
Posts: 612

Re: FPGA pin and reference design

By default, the 802.11 reference design does not signal when a beacon is transmitted on the User I/O.  However, it is pretty straight-forward to add.

You can see the current mapping of the debug header pins here.

To look at events in software on the debug header, you can set and clear the SW debug pins with the wlan_mac_high_set_debug_gpio() and wlan_mac_high_clear_debug_gpio() functions.

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#3 2015-Nov-25 05:54:30

murphpo
Administrator
From: Mango Communications
Registered: 2006-Jul-03
Posts: 5159

Re: FPGA pin and reference design

The 802.11 ref design does assert a debug output whenever the Tx PHY is transmitting. This assertion will include any beacon transmissions. This is the "Tx PHY Active" signal in the pin map Erik linked to above. Using a software-controlled GPIO is the best option if you require an output that only asserts for beacon transmissions.

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#4 2015-Nov-25 09:28:36

zhimeng
Member
Registered: 2015-Sep-30
Posts: 47

Re: FPGA pin and reference design

I also a question here.
If I want to change the debug output to another channel
XGpio_DiscreteWrite(&Gpio, GPIO_OUTPUT_CHANNEL, debug_gpio_state);
I need to change the GPIO_OUTPUT_CHANNEL to another value between 0-15.
Is this correct?

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#5 2015-Nov-25 09:57:16

welsh
Administrator
From: Mango Communications
Registered: 2013-May-15
Posts: 612

Re: FPGA pin and reference design

The GPIO_OUTPUT_CHANNEL is part of the axi_gpio configuration.  It should not be changed.

To change the state of the GPIO outputs on the debug header, you need to update the debug_gpio_state.  While there are 4 GPIOs configured in the axi_gpio, only the first three are mapped to the debug header (i.e. bits 0, 1, and 2 are mapped to pins 12, 13, 14, respectively, to be used for "SW debug").  Therefore, you can pass a value between 0 - 15 to the functions I referenced, but only values of 0 - 7 will cause the GPIOs on the debug header to change state.  You should use the wrapper function instead of trying to access the GPIO directly since they will make for cleaner code. 

Also, please note that the SW GPIO can only be accessed by CPU High so you should not try to access it from CPU Low code.

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#6 2015-Nov-25 11:04:45

zhimeng
Member
Registered: 2015-Sep-30
Posts: 47

Re: FPGA pin and reference design

Thanks for your information. I will do some tests on that

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