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I am using ISE Design Suite 14.4 to try to add interpolation and decimation in the module "RFX outputs" and "RFX inputs" respectively in module "w3_warplab_buffers.mdl".
If I only add interpolation and decimation in RFA and RFB, it works fine.
RFA outputs: interpoloation RFA inputs: decimation RFB outputs: interpoloation RFB inputs: decimation RFC outputs: unchangeable RFC inputs: unchangeable RFD outputs: unchangeable RFD inputs: unchangeable
All the timing met the requirements.
However, if I add these two functions in all the four antennas. there will be setup timing violations.
RFA outputs: interpoloation RFA inputs: decimation RFB outputs: interpoloation RFB inputs: decimation RFC outputs: interpoloation RFC inputs: decimation RFD outputs: interpoloation RFD inputs: decimation
After I run timing analyzer, I found that the violation lies in module "w3_warplab_trigger_proc". My logic has nothing to do with it.
Timing constraint: TS_clock_generator_ProcBusSamp_Clocks_clock_generator_ProcBusSamp_Clocks_SIG_MMCM0_CLKOUT1 = PERIOD TIMEGRP "clock_generator_ProcBusSamp_Clocks_clock_generator_ProcBusSamp_Clocks_SIG_MMCM0_CLKOUT1" TS_samp_clk * 2 HIGH 50%;
For more information, see Period Analysis in the Timing Closure User Guide (UG612).
3713452 paths analyzed, 306314 endpoints analyzed, 1 failing endpoint
1 timing error detected. (1 setup error, 0 hold errors, 0 component switching limit errors)
Minimum period is 6.295ns.
--------------------------------------------------------------------------------
Slack (setup path): -0.045ns (requirement - (data path - clock path skew + uncertainty))
Source: warplab_trigger_proc/warplab_trigger_proc/sysgen_dut/w3_warplab_trigger_proc_x0/addressable_shift_register_3/comp2.core_instance2/blk00000001/blk00000002/blk00000003 (FF)
Destination: warplab_trigger_proc/warplab_trigger_proc/sysgen_dut/w3_warplab_trigger_proc_x0/register2/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp (FF)
Requirement: 6.250ns
Data Path Delay: 6.421ns (Levels of Logic = 0)
Clock Path Skew: 0.184ns (1.605 - 1.421)
Source Clock: axi_bram_ctrl_0_BRAM_PORTA_0_BRAM_Clk rising at 0.000ns
Destination Clock: axi_bram_ctrl_0_BRAM_PORTA_0_BRAM_Clk rising at 6.250ns
Clock Uncertainty: 0.058ns
Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Discrete Jitter (DJ): 0.092ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: warplab_trigger_proc/warplab_trigger_proc/sysgen_dut/w3_warplab_trigger_proc_x0/addressable_shift_register_3/comp2.core_instance2/blk00000001/blk00000002/blk00000003 to warplab_trigger_proc/warplab_trigger_proc/sysgen_dut/w3_warplab_trigger_proc_x0/register2/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X48Y158.B Treg 1.292 warplab_trigger_proc/warplab_trigger_proc/sysgen_dut/w3_warplab_trigger_proc_x0/addressable_shift_register_3_q_net
warplab_trigger_proc/warplab_trigger_proc/sysgen_dut/w3_warplab_trigger_proc_x0/addressable_shift_register_3/comp2.core_instance2/blk00000001/blk00000002/blk00000003
OLOGIC_X0Y20.D1 net (fanout=3) 4.633 warplab_trigger_proc/warplab_trigger_proc/sysgen_dut/w3_warplab_trigger_proc_x0/addressable_shift_register_3_q_net
OLOGIC_X0Y20.CLK Todck 0.496 trigger_0_out_0_OBUF
warplab_trigger_proc/warplab_trigger_proc/sysgen_dut/w3_warplab_trigger_proc_x0/register2/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp
------------------------------------------------- ---------------------------
Total 6.421ns (1.788ns logic, 4.633ns route)
(27.8% logic, 72.2% route)Logic Utilization: Number of Slice Registers: 82,368 out of 301,440 27 Number used as Flip Flops: 82,181 Number used as Latches: 3 Number used as Latch-thrus: 0 Number used as AND/OR logics: 184 Number of Slice LUTs: 64,671 out of 150,720 42 Number used as logic: 51,567 out of 150,720 34 Number using O6 output only: 35,690 Number using O5 output only: 972 Number using O5 and O6: 14,905 Number used as ROM: 0 Number used as Memory: 9,069 out of 58,400 15 Number used as Dual Port RAM: 1,930 Number using O6 output only: 1,066 Number using O5 output only: 24 Number using O5 and O6: 840 Number used as Single Port RAM: 24 Number using O6 output only: 16 Number using O5 output only: 0 Number using O5 and O6: 8 Number used as Shift Register: 7,115 Number using O6 output only: 5,207 Number using O5 output only: 456 Number using O5 and O6: 1,452 Number used exclusively as route-thrus: 4,035 Number with same-slice register load: 3,857 Number with same-slice carry load: 158 Number with other load: 20
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In order to optimize the timing in module "RFX outputs", I add several registers to separate some combination logic. Unfortunately, the timing is worse than before.
Timing constraint: TS_clock_generator_ProcBusSamp_Clocks_clock_generator_ProcBusSamp_Clocks_SIG_MMCM0_CLKOUT1 = PERIOD TIMEGRP "clock_generator_ProcBusSamp_Clocks_clock_generator_ProcBusSamp_Clocks_SIG_MMCM0_CLKOUT1" TS_samp_clk * 2 HIGH 50%;
For more information, see Period Analysis in the Timing Closure User Guide (UG612).
3713452 paths analyzed, 306345 endpoints analyzed, 37 failing endpoints
37 timing errors detected. (37 setup errors, 0 hold errors, 0 component switching limit errors)
Minimum period is 6.503ns.
--------------------------------------------------------------------------------
Slack (setup path): -0.253ns (requirement - (data path - clock path skew + uncertainty))
Source: microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Use_DBUS.Using_D_AXI.DAXI_Interface_I1/M_AXI_DP_WVALID_i (FF)
Destination: warplab_trigger_proc/warplab_trigger_proc/sysgen_dut/w3_warplab_trigger_proc_x0/edk_processor_0c95cfea2c/memmap/shmem_bank_out_i_9 (FF)
Requirement: 6.250ns
Data Path Delay: 6.237ns (Levels of Logic = 3)
Clock Path Skew: -0.208ns (1.385 - 1.593)
Source Clock: axi_bram_ctrl_0_BRAM_PORTA_0_BRAM_Clk rising at 0.000ns
Destination Clock: axi_bram_ctrl_0_BRAM_PORTA_0_BRAM_Clk rising at 6.250ns
Clock Uncertainty: 0.058ns
Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Discrete Jitter (DJ): 0.092ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Use_DBUS.Using_D_AXI.DAXI_Interface_I1/M_AXI_DP_WVALID_i to warplab_trigger_proc/warplab_trigger_proc/sysgen_dut/w3_warplab_trigger_proc_x0/edk_processor_0c95cfea2c/memmap/shmem_bank_out_i_9
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X86Y163.AQ Tcko 0.283 axi_interconnect_periph_160_S_WVALID
microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Use_DBUS.Using_D_AXI.DAXI_Interface_I1/M_AXI_DP_WVALID_i
SLICE_X63Y105.B6 net (fanout=9) 2.337 axi_interconnect_periph_160_S_WVALID
SLICE_X63Y105.B Tilo 0.061 axi_intc_0/axi_intc_0/INTC_CORE_I/isr_8
axi_interconnect_periph_160/axi_interconnect_periph_160/crossbar_samd/gen_sasd.crossbar_sasd_0/mi_wvalid<0>1
SLICE_X37Y93.B6 net (fanout=3) 1.284 axi_interconnect_periph_160_M_wvalid<0>
SLICE_X37Y93.B Tilo 0.061 axi_interconnect_periph_160_M_rdata<19>
warplab_trigger_proc/warplab_trigger_proc/sysgen_dut/w3_warplab_trigger_proc_x0/edk_processor_0c95cfea2c/memmap/Mmux_s_shram_en11
SLICE_X36Y56.D5 net (fanout=41) 1.486 warplab_trigger_proc/warplab_trigger_proc/sysgen_dut/PktOps0_reg_ce
SLICE_X36Y56.DMUX Tilo 0.173 warplab_trigger_proc/N22
warplab_trigger_proc/warplab_trigger_proc/sysgen_dut/w3_warplab_trigger_proc_x0/edk_processor_0c95cfea2c/memmap/_n3106_inv11
SLICE_X38Y57.CE net (fanout=9) 0.339 warplab_trigger_proc/warplab_trigger_proc/sysgen_dut/w3_warplab_trigger_proc_x0/edk_processor_0c95cfea2c/memmap/_n3106_inv1
SLICE_X38Y57.CLK Tceck 0.213 warplab_trigger_proc/warplab_trigger_proc/sysgen_dut/w3_warplab_trigger_proc_x0/edk_processor_0c95cfea2c/memmap/shmem_bank_out_i<9>
warplab_trigger_proc/warplab_trigger_proc/sysgen_dut/w3_warplab_trigger_proc_x0/edk_processor_0c95cfea2c/memmap/shmem_bank_out_i_9
------------------------------------------------- ---------------------------
Total 6.237ns (0.791ns logic, 5.446ns route)
(12.7% logic, 87.3% route)
--------------------------------------------------------------------------------
Slack (setup path): -0.253ns (requirement - (data path - clock path skew + uncertainty))
Source: microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Use_DBUS.Using_D_AXI.DAXI_Interface_I1/M_AXI_DP_WVALID_i (FF)
Destination: warplab_trigger_proc/warplab_trigger_proc/sysgen_dut/w3_warplab_trigger_proc_x0/edk_processor_0c95cfea2c/memmap/shmem_bank_out_i_8 (FF)
Requirement: 6.250ns
Data Path Delay: 6.237ns (Levels of Logic = 3)
Clock Path Skew: -0.208ns (1.385 - 1.593)
Source Clock: axi_bram_ctrl_0_BRAM_PORTA_0_BRAM_Clk rising at 0.000ns
Destination Clock: axi_bram_ctrl_0_BRAM_PORTA_0_BRAM_Clk rising at 6.250ns
Clock Uncertainty: 0.058ns
Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Discrete Jitter (DJ): 0.092ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Use_DBUS.Using_D_AXI.DAXI_Interface_I1/M_AXI_DP_WVALID_i to warplab_trigger_proc/warplab_trigger_proc/sysgen_dut/w3_warplab_trigger_proc_x0/edk_processor_0c95cfea2c/memmap/shmem_bank_out_i_8
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X86Y163.AQ Tcko 0.283 axi_interconnect_periph_160_S_WVALID
microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Use_DBUS.Using_D_AXI.DAXI_Interface_I1/M_AXI_DP_WVALID_i
SLICE_X63Y105.B6 net (fanout=9) 2.337 axi_interconnect_periph_160_S_WVALID
SLICE_X63Y105.B Tilo 0.061 axi_intc_0/axi_intc_0/INTC_CORE_I/isr_8
axi_interconnect_periph_160/axi_interconnect_periph_160/crossbar_samd/gen_sasd.crossbar_sasd_0/mi_wvalid<0>1
SLICE_X37Y93.B6 net (fanout=3) 1.284 axi_interconnect_periph_160_M_wvalid<0>
SLICE_X37Y93.B Tilo 0.061 axi_interconnect_periph_160_M_rdata<19>
warplab_trigger_proc/warplab_trigger_proc/sysgen_dut/w3_warplab_trigger_proc_x0/edk_processor_0c95cfea2c/memmap/Mmux_s_shram_en11
SLICE_X36Y56.D5 net (fanout=41) 1.486 warplab_trigger_proc/warplab_trigger_proc/sysgen_dut/PktOps0_reg_ce
SLICE_X36Y56.DMUX Tilo 0.173 warplab_trigger_proc/N22
warplab_trigger_proc/warplab_trigger_proc/sysgen_dut/w3_warplab_trigger_proc_x0/edk_processor_0c95cfea2c/memmap/_n3106_inv11
SLICE_X38Y57.CE net (fanout=9) 0.339 warplab_trigger_proc/warplab_trigger_proc/sysgen_dut/w3_warplab_trigger_proc_x0/edk_processor_0c95cfea2c/memmap/_n3106_inv1
SLICE_X38Y57.CLK Tceck 0.213 warplab_trigger_proc/warplab_trigger_proc/sysgen_dut/w3_warplab_trigger_proc_x0/edk_processor_0c95cfea2c/memmap/shmem_bank_out_i<9>
warplab_trigger_proc/warplab_trigger_proc/sysgen_dut/w3_warplab_trigger_proc_x0/edk_processor_0c95cfea2c/memmap/shmem_bank_out_i_8
------------------------------------------------- ---------------------------
Total 6.237ns (0.791ns logic, 5.446ns route)
(12.7% logic, 87.3% route)
--------------------------------------------------------------------------------
Slack (setup path): -0.246ns (requirement - (data path - clock path skew + uncertainty))
Source: microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Use_DBUS.Using_D_AXI.DAXI_Interface_I1/M_AXI_DP_WVALID_i (FF)
Destination: warplab_trigger_proc/warplab_trigger_proc/sysgen_dut/w3_warplab_trigger_proc_x0/edk_processor_0c95cfea2c/memmap/shmem_bank_out_i_28 (FF)
Requirement: 6.250ns
Data Path Delay: 6.233ns (Levels of Logic = 3)
Clock Path Skew: -0.205ns (1.388 - 1.593)
Source Clock: axi_bram_ctrl_0_BRAM_PORTA_0_BRAM_Clk rising at 0.000ns
Destination Clock: axi_bram_ctrl_0_BRAM_PORTA_0_BRAM_Clk rising at 6.250ns
Clock Uncertainty: 0.058ns
Clock Uncertainty: 0.058ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Discrete Jitter (DJ): 0.092ns
Phase Error (PE): 0.000ns
Maximum Data Path at Slow Process Corner: microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Use_DBUS.Using_D_AXI.DAXI_Interface_I1/M_AXI_DP_WVALID_i to warplab_trigger_proc/warplab_trigger_proc/sysgen_dut/w3_warplab_trigger_proc_x0/edk_processor_0c95cfea2c/memmap/shmem_bank_out_i_28
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X86Y163.AQ Tcko 0.283 axi_interconnect_periph_160_S_WVALID
microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Use_DBUS.Using_D_AXI.DAXI_Interface_I1/M_AXI_DP_WVALID_i
SLICE_X63Y105.B6 net (fanout=9) 2.337 axi_interconnect_periph_160_S_WVALID
SLICE_X63Y105.B Tilo 0.061 axi_intc_0/axi_intc_0/INTC_CORE_I/isr_8
axi_interconnect_periph_160/axi_interconnect_periph_160/crossbar_samd/gen_sasd.crossbar_sasd_0/mi_wvalid<0>1
SLICE_X37Y93.B6 net (fanout=3) 1.284 axi_interconnect_periph_160_M_wvalid<0>
SLICE_X37Y93.B Tilo 0.061 axi_interconnect_periph_160_M_rdata<19>
warplab_trigger_proc/warplab_trigger_proc/sysgen_dut/w3_warplab_trigger_proc_x0/edk_processor_0c95cfea2c/memmap/Mmux_s_shram_en11
SLICE_X36Y56.D5 net (fanout=41) 1.486 warplab_trigger_proc/warplab_trigger_proc/sysgen_dut/PktOps0_reg_ce
SLICE_X36Y56.DMUX Tilo 0.173 warplab_trigger_proc/N22
warplab_trigger_proc/warplab_trigger_proc/sysgen_dut/w3_warplab_trigger_proc_x0/edk_processor_0c95cfea2c/memmap/_n3106_inv11
SLICE_X38Y55.CE net (fanout=9) 0.335 warplab_trigger_proc/warplab_trigger_proc/sysgen_dut/w3_warplab_trigger_proc_x0/edk_processor_0c95cfea2c/memmap/_n3106_inv1
SLICE_X38Y55.CLK Tceck 0.213 warplab_trigger_proc/warplab_trigger_proc/sysgen_dut/w3_warplab_trigger_proc_x0/edk_processor_0c95cfea2c/memmap/shmem_bank_out_i<11>
warplab_trigger_proc/warplab_trigger_proc/sysgen_dut/w3_warplab_trigger_proc_x0/edk_processor_0c95cfea2c/memmap/shmem_bank_out_i_28
------------------------------------------------- ---------------------------
Total 6.233ns (0.791ns logic, 5.442ns route)
(12.7% logic, 87.3% route)Offline
It's not unusual that changes in one part of the design will induce timing errors in other blocks. For example, the implementation flow might have achieved timing on your modified blocks at the expense of timing elsewhere in the design. The best next step is to reduce the fanout and levels of logic along any of the critical paths in the design, starting with your modified blocks. For example, if you used a mux to select between the filtered and unfiltered signal paths, ensure there's a DFF (System Generator "Register" block) at the mux inputs and outputs.
Another step is to enable "Register Slices" on the AXI bus interface signals for pcores. The easiest way to do this is via the XPS GUI. In the System Assembly View Bus Interfaces tap, double-click on a pcore, click on the "Interconnect Settings for BUSIF" tab and select "LIGHT_WEIGHT" or "FULLY_REGISTERED" for the various "Use register slice" options. This will consume many extra DFFs, so you should only do this on bus interfaces that are prone to timing failures.
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