WARP Project Forums - Wireless Open-Access Research Platform

As a baseline, you can think of the WARP v3 node as an FPGA development board with various peripherals, including two RF interfaces. You can program the FPGA with whatever waveform and protocol processing is required for your research application.

We recommend a design flow that combines Xilinx System Generator cores with an embedded MicroBlaze processor. The Sysgen cores implement the real-time waveform processing, and the MicroBlaze runs C code for protocol implementations and peripheral I/O. We use this design flow for our reference designs (described below). The design flow is introduced in our Getting Started tutorials.

System Generator cores are designed in Simulink. The output of a Sysgen model is a pcore (peripheral core), bundling the HDL and cores which implement the logic design. The MicroBlaze CPU, Sysgen cores, and other peripheral controllers (Ethernet, UART, memory, etc) are integrated into one FPGA design using Xilinx XPS. The MicroBlaze C code is compiled using the Xilinx SDK.

Building a complete FPGA design from scratch is a big project. Recognizing this, we (i.e. the Mango team) maintain two complete reference designs you can use as starting points for your project.

The WARPLab Reference Design implements a PHY prototyping framework that uses WARP hardware for waveform Tx/Rx and MATLAB for waveform processing. In WARPLab the hardware buffers Tx and Rx waveforms, transmitting and receiving them in real time at 40MSps. The raw waveforms are transferred via Ethernet between the hardware and MATLAB. With WARPLab you can define custom Tx signals and implement any Rx waveform processing you need, all in m code. We provide a few example scripts, including  SISO OFDM and MIMO OFDM Tx/Rx examples.

The 802.11 Reference Design implements the MAC and PHY from IEEE 802.11. The MAC and PHY implementations run entirely in the FPGA in real time, enabling interaction among both WARP v3 nodes and commercial Wi-Fi devices. The full source code for the MAC and PHY are included. You can use the 802.11 Ref Design to explore a wide variety of real-time MAC/PHY extensions. We also provide a Python framework (wlan_exp) for running experiments with the 802.11 Ref Design. Python scripts can configure many WARP v3 nodes, execute experiments and retrieve results, all in real time.

We're happy to make suggestions on how to apply these designs  if you can describe your project in more detail.

So, I read up a little more about the general code architecture. I now have a better understanding about WARP.
Here is what i have understood.
There is an FPGA code that implements the Microblaze processor on the FPGA complete with peripheral cores and instruction and data memory.
The cores are peripherals to the processors. much like device controllers , they help emulate PHY .
The micro-blaze processor runs the MAC state machine.
The Matlab Simulink models are converted to the C code and this C code is then used to program the pheripheral cores and the processor. This results in a bit file that is uploaded on to the FPGA.

My next question is : Is the filter that is responsible for clearing out the noise, implemented on the RF Frontend or its implemented in the RX chain ? I basically want to transmit/receive 5MHz bandwidth signals rather than the usual 20 MHz bandwidth signals. My guess is its implemented in the RF Frontend, it is possible for me to alter the bandwidth and the central frequency of the filter.

Thanks in advance !

Last edited by jadonabhinav (2016-Jan-18 10:23:34)

Regarding the details of my application . My application for now is pretty simple, I need to count the number of samples above a preset RSSI value. For this I was looking at the simulink model you have for the Rx chain. The first block in the chain outputs the value of RSSI, RX_I and RX_Q among other things. How do i go about changing the code now for my application  ?