WARP Project Forums - Wireless Open-Access Research Platform

Amir · 2008-Nov-06 12:07:11

We have extended the reference design v08 to support four beamforming RX antennas by extending the ofdm core and instantiating a second AGC core. AGC0 and AGC1 cores are connected to radio slots 1&2 and 3&4 respectively, with the following connections in the MHS file:

Code:

 BEGIN ofdm_agc_mimo_opbw
 PARAMETER INSTANCE = ofdm_AGC_mimo_opbw_0
 PARAMETER HW_VER = 1.03.a
 PARAMETER C_BASEADDR = 0x74020000
 PARAMETER C_HIGHADDR = 0x7402ffff
 BUS_INTERFACE SOPB = opb
 PORT opb_clk = sys_clk_OPB
 PORT i_in_a = radio_bridge_slot_1_user_ADC_I
 PORT q_in_a = radio_bridge_slot_1_user_ADC_Q
 PORT i_in_b = radio_bridge_slot_2_user_ADC_I
 PORT q_in_b = radio_bridge_slot_2_user_ADC_Q
 PORT i_out_a = ofdmRx_antA_ADC_I
 PORT q_out_a = ofdmRx_antA_ADC_Q
 PORT i_out_b = ofdmRx_antB_ADC_I
 PORT q_out_b = ofdmRx_antB_ADC_Q
 PORT packet_in = rssi_pkt_detect_opbw_0_rssi_pkt_det_out
 PORT rssi_in_a = radio_bridge_slot_1_user_RSSI_ADC_D
 PORT rssi_in_b = radio_bridge_slot_2_user_RSSI_ADC_D
 PORT rxhp_a = agc_rxhp_a
 PORT rxhp_b = agc_rxhp_b
 PORT g_bb_a = agc_g_bb_a
 PORT g_rf_a = agc_g_rf_a
 PORT g_bb_b = agc_g_bb_b
 PORT g_rf_b = agc_g_rf_b
 PORT reset_in = rx_pktdetreset
 PORT done_a = agc_done_a
 PORT done_b = agc_done_b
END

BEGIN ofdm_agc_mimo_opbw
 PARAMETER INSTANCE = ofdm_AGC_mimo_opbw_1
 PARAMETER HW_VER = 1.03.a
 PARAMETER C_BASEADDR = 0x74000000
 PARAMETER C_HIGHADDR = 0x7400ffff
 BUS_INTERFACE SOPB = opb
 PORT opb_clk = sys_clk_OPB
 PORT i_in_a = radio_bridge_slot_3_user_ADC_I
 PORT q_in_a = radio_bridge_slot_3_user_ADC_Q
 PORT i_in_b = radio_bridge_slot_4_user_ADC_I
 PORT q_in_b = radio_bridge_slot_4_user_ADC_Q
 PORT i_out_a = ofdmRx_antC_ADC_I
 PORT q_out_a = ofdmRx_antC_ADC_Q
 PORT i_out_b = ofdmRx_antD_ADC_I
 PORT q_out_b = ofdmRx_antD_ADC_Q
 PORT packet_in = rssi_pkt_detect_opbw_0_rssi_pkt_det_out
 PORT rssi_in_a = radio_bridge_slot_3_user_RSSI_ADC_D
 PORT rssi_in_b = radio_bridge_slot_4_user_RSSI_ADC_D
 PORT rxhp_a = agc_rxhp_c
 PORT rxhp_b = agc_rxhp_d
 PORT g_bb_a = agc_g_bb_c
 PORT g_rf_a = agc_g_rf_c
 PORT g_bb_b = agc_g_bb_d
 PORT g_rf_b = agc_g_rf_d
 PORT reset_in = rx_pktdetreset
 PORT done_a = agc_done_c
 PORT done_b = agc_done_d
END

We also modified the AGC driver to simultaneously initialize/reset/operate both AGCs. Running the bit-stream, we observed inconsistent reception quality and some weird outcomes:

- with all 4 antennas RX-enabled, the reception is poor.

- with antennas 3&4 RX-disabled (i.e. 2-antenna beamforming) we have perfect reception. using chipscope, we verified that the I & Q values of antennas 3 & 4 delivered to the ofdm core ports are zero. also the total (bb & rf) AGC gains of both antennas 3 and 4 are 92.

- with only antenna 3 RX-disabled, the reception is again poor. with further debugging this seemed to be due to the fact that with only "Ant3" disabled, the I channel of "Ant4" at the input port of ofdm core is also zero (but not its Q channel).

Is there anything in the AGC core that makes the two antennas output dependent? i.e. why should the Ant4 I&Q outputs depend on the status of Ant3 (i.e. Ant3 being en/disabled) ? moreover, why should the Ant4's I channel be zero while its Q channel is not.

p.s. We have verified all the radio bridge pin connections with the FPGA pin-out spreadsheet and also against the 4x4 WARPLAB UCF file. We also tried different radio cards, MMCX and twisted pair cables, and fpga board, but have seen the same result.

murphpo · 2008-Nov-06 15:10:07

-What version of the clock_board_config pcore are you using? It will need to be configured to drive all 8 outputs (4 sampling + 4 radio reference) for a 4x4 node. The latest pcore (v1.04) makes this easy, using just top-level parameters in XPS. Earlier versions required Verilog changes to select active outputs.

-Can you clarify the mapping of the daughtercard slots to the antenna numbers you mentioned? Is "antenna 3" mapped to a radio in daughtercard slot 3?

Amir · 2008-Nov-10 09:05:22

- we were using version 1.02 that came with the ref. design v08. I switched to v1.04 and enabled all 8 outputs by modifying the MPD file. The new bit-stream still has the same problem.

- yes. antenna X is in daughtercard slot X.

murphpo · 2008-Nov-10 10:57:43

The AGC core is built as two parallel pipelines; the only thing shared between channels are common control registers. But the pipeline keeps running even if the radio board isn't in Rx mode, so I'm not surprised the core's outputs were non-zero for an inactive radio.

One suggestion- extend the PHY to explicitly ignore inputs you know are inactive. The easiest way is to add input registers to your PHY model between the gateways in (for the Rx ADCs) and the logic and tie the reset inputs of these registers to an OPB register. Then, when your code disables a radio receiver, you can also disable the PHY's input to be sure it's receiving digital zero.

Amir · 2008-Nov-11 12:43:50

That's a good suggestion but our primary interest is to run the PHY with all four rx antennas and we only disabled some antennas to pinpoint the problem.

- To further debug the issue, I changed the MHS file to rearrange the AGC connections by having radios 2&3 on AGC0 and radios 1&4 on AGC1. To my surprise, removing radio 3 still made the "I" channel of radio 4 go to zero despite the fact that these radios are connected to two different AGCs.

- Another strange observation was that with all four radios RX enabled, commenting out the following line in warpphy.c noticeably improved the performance.

WarpRadio_v1_RxHpSoftControlDisable(allRadios); //with allRadios being the address mask for all four radios.

Is this high pass filter for removing the DC offset from the incoming signal? What would be the consequence of removing the above line from the code given that we don't control RxHP bit anywhere else in the software. Any idea why this would improve the reception?

murphpo · 2008-Nov-11 13:44:57

How are you disabling individual radios- with WarpRadio_v1_TxRxDisable(RADIO3_ADDR)?

RxHP is a signal on the MAX2829 that controls a high-pass filter. The signal needs to be asserted (logic 1) whenever gains are changing. The radio controller has two modes for controlling RxHP- hardware and software. The hardware mode passes the signal through to a port for control by the AGC core. The software mode ignores the AGC port and uses a software-writable register bit to control the RxHP signal. You definitely want the AGC cores controlling the RxHP signals on all the radios.

When you see the I channel of radio 4 go to zero, is it digital zero for all time, or just a very small signal?

Amir · 2008-Nov-11 15:34:39

- yes, I use WarpRadio_v1_TxRxDisable to disable any individual radio. I also omit that radio's address mask from any WarpRadio_v1_TxEnable or WarpRadio_v1_RxEnable within warpphy.c.

- As soon as radio 3 is disabled, the I channel of both radio 3 and 4 becomes very small, in the order of 10^(-4) as opposed to its normal range of +- 0.1 during pkt reception. If both radios 3 & 4 are disabled, everything works perfectly with radios 1 & 2. Surprisingly, disabling only radio 4 has no tangible effect on its "I" channel delivered to input port of phy.

Here is a summary of the results I got with radios 1 & 4 on AGC0 and radios 2 & 3 on AGC1.

radio 2 disabled: only the "I" channel of radio 2 becomes negligible.
radio 3 disabled: the "I" channels of both radios 3 & 4 become negligible.
radio 4 disabled: the "I" channel of all radios including radio 4 are unaffected and in the order of +-0.1.

Last edited by Amir (2008-Nov-12 08:32:26)

murphpo · 2008-Nov-11 16:24:02

That really sounds like signals got crossed, either inside the radio controller or in the MHS interconnect between cores. Can you post your full MHS file?

Amir · 2008-Nov-12 07:59:51

We are using the following version of pcores that come with ref. design v8:

AGC: v1.03a
Radio controller: v1.10a
Radio bridge: v1.08a

Here's the first part of our full MHS file:

Code:

# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 9.1.02 Build EDK_J_SP2.4
# Wed Jul 11 12:11:54 2007
# Target Board:  Rice University - WARP Project WARP FPGA and Radio Boards Rev FPGA 1.2 / Radio 1.4 / Clock 1.0
# Family:    virtex2p
# Device:    XC2VP70
# Package:   FF1517
# Speed Grade:   -6
# Processor: PPC 405
# Processor clock frequency: 160.000000 MHz
# Bus clock frequency: 80.000000 MHz
# Debug interface: FPGA JTAG
# On Chip Memory : 320 KB
# Total Off Chip Memory :   4 MB
# - SRAM_256Kx32 =   2 MB
# - SRAM_256Kx32 =   2 MB
# ##############################################################################


PARAMETER VERSION = 2.1.0


# Clock Board
 PORT fpga_0_clk_board_config_sys_clk_pin = fpga_0_clk_board_config_sys_clk, DIR = I
 PORT fpga_0_clk_board_config_cfg_radio_dat_out_pin = fpga_0_clk_board_config_cfg_radio_dat_out, DIR = O
 PORT fpga_0_clk_board_config_cfg_radio_csb_out_pin = fpga_0_clk_board_config_cfg_radio_csb_out, DIR = O
 PORT fpga_0_clk_board_config_cfg_radio_en_out_pin = fpga_0_clk_board_config_cfg_radio_en_out, DIR = O
 PORT fpga_0_clk_board_config_cfg_radio_clk_out_pin = fpga_0_clk_board_config_cfg_radio_clk_out, DIR = O
 PORT fpga_0_clk_board_config_cfg_logic_dat_out_pin = fpga_0_clk_board_config_cfg_logic_dat_out, DIR = O
 PORT fpga_0_clk_board_config_cfg_logic_csb_out_pin = fpga_0_clk_board_config_cfg_logic_csb_out, DIR = O
 PORT fpga_0_clk_board_config_cfg_logic_en_out_pin = fpga_0_clk_board_config_cfg_logic_en_out, DIR = O
 PORT fpga_0_clk_board_config_cfg_logic_clk_out_pin = fpga_0_clk_board_config_cfg_logic_clk_out, DIR = O
 PORT fpga_0_radio_bridge_slot_1_converter_clock_out_pin = fpga_0_radio_bridge_slot_1_converter_clock_out, DIR = O
 PORT fpga_0_radio_bridge_slot_1_radio_EEPROM_IO = fpga_0_radio_bridge_slot_1_radio_EEPROM_IO, DIR = IO
 PORT fpga_0_radio_bridge_slot_1_dac_spi_clk_pin = fpga_0_radio_bridge_slot_1_dac_spi_clk, DIR = O
 PORT fpga_0_radio_bridge_slot_1_dac_spi_cs_pin = fpga_0_radio_bridge_slot_1_dac_spi_cs, DIR = O
 PORT fpga_0_radio_bridge_slot_1_dac_spi_data_pin = fpga_0_radio_bridge_slot_1_dac_spi_data, DIR = O
 PORT fpga_0_radio_bridge_slot_1_radio_24PA_pin = fpga_0_radio_bridge_slot_1_radio_24PA, DIR = O
 PORT fpga_0_radio_bridge_slot_1_radio_5PA_pin = fpga_0_radio_bridge_slot_1_radio_5PA, DIR = O
 PORT fpga_0_radio_bridge_slot_1_radio_ANTSW_pin = fpga_0_radio_bridge_slot_1_radio_ANTSW, DIR = O, VEC = [1:0]
 PORT fpga_0_radio_bridge_slot_1_radio_dac_PLL_LOCK_pin = fpga_0_radio_bridge_slot_1_radio_dac_PLL_LOCK, DIR = I
 PORT fpga_0_radio_bridge_slot_1_radio_dac_RESET_pin = fpga_0_radio_bridge_slot_1_radio_dac_RESET, DIR = O
 PORT fpga_0_radio_bridge_slot_1_radio_DIPSW_pin = fpga_0_radio_bridge_slot_1_radio_DIPSW, DIR = I, VEC = [3:0]
 PORT fpga_0_radio_bridge_slot_1_radio_LD_pin = fpga_0_radio_bridge_slot_1_radio_LD, DIR = I
 PORT fpga_0_radio_bridge_slot_1_radio_LED_pin = fpga_0_radio_bridge_slot_1_radio_LED, DIR = O, VEC = [2:0]
 PORT fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_clk_pin = fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_clk, DIR = O
 PORT fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_CLAMP_pin = fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_CLAMP, DIR = O
 PORT fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin = fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D, DIR = I, VEC = [9:0]
 PORT fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_HIZ_pin = fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_HIZ, DIR = O
 PORT fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_OTR_pin = fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_OTR, DIR = I
 PORT fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_SLEEP_pin = fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_SLEEP, DIR = O
 PORT fpga_0_radio_bridge_slot_1_radio_RX_ADC_DCS_pin = fpga_0_radio_bridge_slot_1_radio_RX_ADC_DCS, DIR = O
 PORT fpga_0_radio_bridge_slot_1_radio_RX_ADC_DFS_pin = fpga_0_radio_bridge_slot_1_radio_RX_ADC_DFS, DIR = O
 PORT fpga_0_radio_bridge_slot_1_radio_RX_ADC_OTRA_pin = fpga_0_radio_bridge_slot_1_radio_RX_ADC_OTRA, DIR = I
 PORT fpga_0_radio_bridge_slot_1_radio_RX_ADC_OTRB_pin = fpga_0_radio_bridge_slot_1_radio_RX_ADC_OTRB, DIR = I
 PORT fpga_0_radio_bridge_slot_1_radio_RX_ADC_PWDNA_pin = fpga_0_radio_bridge_slot_1_radio_RX_ADC_PWDNA, DIR = O
 PORT fpga_0_radio_bridge_slot_1_radio_RX_ADC_PWDNB_pin = fpga_0_radio_bridge_slot_1_radio_RX_ADC_PWDNB, DIR = O
 PORT fpga_0_radio_bridge_slot_1_radio_TxEn_pin = fpga_0_radio_bridge_slot_1_radio_TxEn, DIR = O
 PORT fpga_0_radio_bridge_slot_1_radio_RxEn_pin = fpga_0_radio_bridge_slot_1_radio_RxEn, DIR = O
 PORT fpga_0_radio_bridge_slot_1_radio_RxHP_pin = fpga_0_radio_bridge_slot_1_radio_RxHP, DIR = O
 PORT fpga_0_radio_bridge_slot_1_radio_SHDN_pin = fpga_0_radio_bridge_slot_1_radio_SHDN, DIR = O
 PORT fpga_0_radio_bridge_slot_1_radio_spi_clk_pin = fpga_0_radio_bridge_slot_1_radio_spi_clk, DIR = O
 PORT fpga_0_radio_bridge_slot_1_radio_spi_cs_pin = fpga_0_radio_bridge_slot_1_radio_spi_cs, DIR = O
 PORT fpga_0_radio_bridge_slot_1_radio_spi_data_pin = fpga_0_radio_bridge_slot_1_radio_spi_data, DIR = O
 PORT fpga_0_radio_bridge_slot_1_radio_B_pin = fpga_0_radio_bridge_slot_1_radio_B, DIR = O, VEC = [6:0]
 PORT fpga_0_radio_bridge_slot_1_radio_DAC_I_pin = fpga_0_radio_bridge_slot_1_radio_DAC_I, DIR = O, VEC = [15:0]
 PORT fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin = fpga_0_radio_bridge_slot_1_radio_DAC_Q, DIR = O, VEC = [15:0]
 PORT fpga_0_radio_bridge_slot_1_radio_ADC_I_pin = fpga_0_radio_bridge_slot_1_radio_ADC_I, DIR = I, VEC = [13:0]
 PORT fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin = fpga_0_radio_bridge_slot_1_radio_ADC_Q, DIR = I, VEC = [13:0]
 PORT fpga_0_radio_bridge_slot_2_converter_clock_out_pin = fpga_0_radio_bridge_slot_2_converter_clock_out, DIR = O
 PORT fpga_0_radio_bridge_slot_2_radio_EEPROM_IO = fpga_0_radio_bridge_slot_2_radio_EEPROM_IO, DIR = IO
 PORT fpga_0_radio_bridge_slot_2_dac_spi_clk_pin = fpga_0_radio_bridge_slot_2_dac_spi_clk, DIR = O
 PORT fpga_0_radio_bridge_slot_2_dac_spi_cs_pin = fpga_0_radio_bridge_slot_2_dac_spi_cs, DIR = O
 PORT fpga_0_radio_bridge_slot_2_dac_spi_data_pin = fpga_0_radio_bridge_slot_2_dac_spi_data, DIR = O
 PORT fpga_0_radio_bridge_slot_2_radio_24PA_pin = fpga_0_radio_bridge_slot_2_radio_24PA, DIR = O
 PORT fpga_0_radio_bridge_slot_2_radio_5PA_pin = fpga_0_radio_bridge_slot_2_radio_5PA, DIR = O
 PORT fpga_0_radio_bridge_slot_2_radio_ANTSW_pin = fpga_0_radio_bridge_slot_2_radio_ANTSW, DIR = O, VEC = [1:0]
 PORT fpga_0_radio_bridge_slot_2_radio_dac_PLL_LOCK_pin = fpga_0_radio_bridge_slot_2_radio_dac_PLL_LOCK, DIR = I
 PORT fpga_0_radio_bridge_slot_2_radio_dac_RESET_pin = fpga_0_radio_bridge_slot_2_radio_dac_RESET, DIR = O
 PORT fpga_0_radio_bridge_slot_2_radio_DIPSW_pin = fpga_0_radio_bridge_slot_2_radio_DIPSW, DIR = I, VEC = [3:0]
 PORT fpga_0_radio_bridge_slot_2_radio_LD_pin = fpga_0_radio_bridge_slot_2_radio_LD, DIR = I
 PORT fpga_0_radio_bridge_slot_2_radio_LED_pin = fpga_0_radio_bridge_slot_2_radio_LED, DIR = O, VEC = [2:0]
 PORT fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_clk_pin = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_clk, DIR = O
 PORT fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_CLAMP_pin = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_CLAMP, DIR = O
 PORT fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D, DIR = I, VEC = [9:0]
 PORT fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_HIZ_pin = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_HIZ, DIR = O
 PORT fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_OTR_pin = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_OTR, DIR = I
 PORT fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_SLEEP_pin = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_SLEEP, DIR = O
 PORT fpga_0_radio_bridge_slot_2_radio_RX_ADC_DCS_pin = fpga_0_radio_bridge_slot_2_radio_RX_ADC_DCS, DIR = O
 PORT fpga_0_radio_bridge_slot_2_radio_RX_ADC_DFS_pin = fpga_0_radio_bridge_slot_2_radio_RX_ADC_DFS, DIR = O
 PORT fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRA_pin = fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRA, DIR = I
 PORT fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRB_pin = fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRB, DIR = I
 PORT fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNA_pin = fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNA, DIR = O
 PORT fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNB_pin = fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNB, DIR = O
 PORT fpga_0_radio_bridge_slot_2_radio_TxEn_pin = fpga_0_radio_bridge_slot_2_radio_TxEn, DIR = O
 PORT fpga_0_radio_bridge_slot_2_radio_RxEn_pin = fpga_0_radio_bridge_slot_2_radio_RxEn, DIR = O
 PORT fpga_0_radio_bridge_slot_2_radio_RxHP_pin = fpga_0_radio_bridge_slot_2_radio_RxHP, DIR = O
 PORT fpga_0_radio_bridge_slot_2_radio_SHDN_pin = fpga_0_radio_bridge_slot_2_radio_SHDN, DIR = O
 PORT fpga_0_radio_bridge_slot_2_radio_spi_clk_pin = fpga_0_radio_bridge_slot_2_radio_spi_clk, DIR = O
 PORT fpga_0_radio_bridge_slot_2_radio_spi_cs_pin = fpga_0_radio_bridge_slot_2_radio_spi_cs, DIR = O
 PORT fpga_0_radio_bridge_slot_2_radio_spi_data_pin = fpga_0_radio_bridge_slot_2_radio_spi_data, DIR = O
 PORT fpga_0_radio_bridge_slot_2_radio_B_pin = fpga_0_radio_bridge_slot_2_radio_B, DIR = O, VEC = [6:0]
 PORT fpga_0_radio_bridge_slot_2_radio_DAC_I_pin = fpga_0_radio_bridge_slot_2_radio_DAC_I, DIR = O, VEC = [15:0]
 PORT fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin = fpga_0_radio_bridge_slot_2_radio_DAC_Q, DIR = O, VEC = [15:0]
 PORT fpga_0_radio_bridge_slot_2_radio_ADC_I_pin = fpga_0_radio_bridge_slot_2_radio_ADC_I, DIR = I, VEC = [13:0]
 PORT fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin = fpga_0_radio_bridge_slot_2_radio_ADC_Q, DIR = I, VEC = [13:0]
 PORT fpga_0_radio_bridge_slot_3_converter_clock_out_pin = fpga_0_radio_bridge_slot_3_converter_clock_out, DIR = O
 PORT fpga_0_radio_bridge_slot_3_radio_EEPROM_IO = fpga_0_radio_bridge_slot_3_radio_EEPROM_IO, DIR = IO
 PORT fpga_0_radio_bridge_slot_3_dac_spi_clk_pin = fpga_0_radio_bridge_slot_3_dac_spi_clk, DIR = O
 PORT fpga_0_radio_bridge_slot_3_dac_spi_cs_pin = fpga_0_radio_bridge_slot_3_dac_spi_cs, DIR = O
 PORT fpga_0_radio_bridge_slot_3_dac_spi_data_pin = fpga_0_radio_bridge_slot_3_dac_spi_data, DIR = O
 PORT fpga_0_radio_bridge_slot_3_radio_24PA_pin = fpga_0_radio_bridge_slot_3_radio_24PA, DIR = O
 PORT fpga_0_radio_bridge_slot_3_radio_5PA_pin = fpga_0_radio_bridge_slot_3_radio_5PA, DIR = O
 PORT fpga_0_radio_bridge_slot_3_radio_ANTSW_pin = fpga_0_radio_bridge_slot_3_radio_ANTSW, DIR = O, VEC = [1:0]
 PORT fpga_0_radio_bridge_slot_3_radio_dac_PLL_LOCK_pin = fpga_0_radio_bridge_slot_3_radio_dac_PLL_LOCK, DIR = I
 PORT fpga_0_radio_bridge_slot_3_radio_dac_RESET_pin = fpga_0_radio_bridge_slot_3_radio_dac_RESET, DIR = O
 PORT fpga_0_radio_bridge_slot_3_radio_DIPSW_pin = fpga_0_radio_bridge_slot_3_radio_DIPSW, DIR = I, VEC = [3:0]
 PORT fpga_0_radio_bridge_slot_3_radio_LD_pin = fpga_0_radio_bridge_slot_3_radio_LD, DIR = I
 PORT fpga_0_radio_bridge_slot_3_radio_LED_pin = fpga_0_radio_bridge_slot_3_radio_LED, DIR = O, VEC = [2:0]
 PORT fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_clk_pin = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_clk, DIR = O
 PORT fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_CLAMP_pin = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_CLAMP, DIR = O
 PORT fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D, DIR = I, VEC = [9:0]
 PORT fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_HIZ_pin = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_HIZ, DIR = O
 PORT fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_OTR_pin = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_OTR, DIR = I
 PORT fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_SLEEP_pin = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_SLEEP, DIR = O
 PORT fpga_0_radio_bridge_slot_3_radio_RX_ADC_DCS_pin = fpga_0_radio_bridge_slot_3_radio_RX_ADC_DCS, DIR = O
 PORT fpga_0_radio_bridge_slot_3_radio_RX_ADC_DFS_pin = fpga_0_radio_bridge_slot_3_radio_RX_ADC_DFS, DIR = O
 PORT fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRA_pin = fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRA, DIR = I
 PORT fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRB_pin = fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRB, DIR = I
 PORT fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNA_pin = fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNA, DIR = O
 PORT fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNB_pin = fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNB, DIR = O
 PORT fpga_0_radio_bridge_slot_3_radio_TxEn_pin = fpga_0_radio_bridge_slot_3_radio_TxEn, DIR = O
 PORT fpga_0_radio_bridge_slot_3_radio_RxEn_pin = fpga_0_radio_bridge_slot_3_radio_RxEn, DIR = O
 PORT fpga_0_radio_bridge_slot_3_radio_RxHP_pin = fpga_0_radio_bridge_slot_3_radio_RxHP, DIR = O
 PORT fpga_0_radio_bridge_slot_3_radio_SHDN_pin = fpga_0_radio_bridge_slot_3_radio_SHDN, DIR = O
 PORT fpga_0_radio_bridge_slot_3_radio_spi_clk_pin = fpga_0_radio_bridge_slot_3_radio_spi_clk, DIR = O
 PORT fpga_0_radio_bridge_slot_3_radio_spi_cs_pin = fpga_0_radio_bridge_slot_3_radio_spi_cs, DIR = O
 PORT fpga_0_radio_bridge_slot_3_radio_spi_data_pin = fpga_0_radio_bridge_slot_3_radio_spi_data, DIR = O
 PORT fpga_0_radio_bridge_slot_3_radio_B_pin = fpga_0_radio_bridge_slot_3_radio_B, DIR = O, VEC = [6:0]
 PORT fpga_0_radio_bridge_slot_3_radio_DAC_I_pin = fpga_0_radio_bridge_slot_3_radio_DAC_I, DIR = O, VEC = [15:0]
 PORT fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin = fpga_0_radio_bridge_slot_3_radio_DAC_Q, DIR = O, VEC = [15:0]
 PORT fpga_0_radio_bridge_slot_3_radio_ADC_I_pin = fpga_0_radio_bridge_slot_3_radio_ADC_I, DIR = I, VEC = [13:0]
 PORT fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin = fpga_0_radio_bridge_slot_3_radio_ADC_Q, DIR = I, VEC = [13:0]
 PORT fpga_0_radio_bridge_slot_4_converter_clock_out_pin = fpga_0_radio_bridge_slot_4_converter_clock_out, DIR = O
 PORT fpga_0_radio_bridge_slot_4_radio_EEPROM_IO = fpga_0_radio_bridge_slot_4_radio_EEPROM_IO, DIR = IO
 PORT fpga_0_radio_bridge_slot_4_dac_spi_clk_pin = fpga_0_radio_bridge_slot_4_dac_spi_clk, DIR = O
 PORT fpga_0_radio_bridge_slot_4_dac_spi_cs_pin = fpga_0_radio_bridge_slot_4_dac_spi_cs, DIR = O
 PORT fpga_0_radio_bridge_slot_4_dac_spi_data_pin = fpga_0_radio_bridge_slot_4_dac_spi_data, DIR = O
 PORT fpga_0_radio_bridge_slot_4_radio_24PA_pin = fpga_0_radio_bridge_slot_4_radio_24PA, DIR = O
 PORT fpga_0_radio_bridge_slot_4_radio_5PA_pin = fpga_0_radio_bridge_slot_4_radio_5PA, DIR = O
 PORT fpga_0_radio_bridge_slot_4_radio_ANTSW_pin = fpga_0_radio_bridge_slot_4_radio_ANTSW, DIR = O, VEC = [1:0]
 PORT fpga_0_radio_bridge_slot_4_radio_dac_PLL_LOCK_pin = fpga_0_radio_bridge_slot_4_radio_dac_PLL_LOCK, DIR = I
 PORT fpga_0_radio_bridge_slot_4_radio_dac_RESET_pin = fpga_0_radio_bridge_slot_4_radio_dac_RESET, DIR = O
 PORT fpga_0_radio_bridge_slot_4_radio_DIPSW_pin = fpga_0_radio_bridge_slot_4_radio_DIPSW, DIR = I, VEC = [3:0]
 PORT fpga_0_radio_bridge_slot_4_radio_LD_pin = fpga_0_radio_bridge_slot_4_radio_LD, DIR = I
 PORT fpga_0_radio_bridge_slot_4_radio_LED_pin = fpga_0_radio_bridge_slot_4_radio_LED, DIR = O, VEC = [2:0]
 PORT fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_clk_pin = fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_clk, DIR = O
 PORT fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_CLAMP_pin = fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_CLAMP, DIR = O
 PORT fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin = fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D, DIR = I, VEC = [9:0]
 PORT fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_HIZ_pin = fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_HIZ, DIR = O
 PORT fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_OTR_pin = fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_OTR, DIR = I
 PORT fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_SLEEP_pin = fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_SLEEP, DIR = O
 PORT fpga_0_radio_bridge_slot_4_radio_RX_ADC_DCS_pin = fpga_0_radio_bridge_slot_4_radio_RX_ADC_DCS, DIR = O
 PORT fpga_0_radio_bridge_slot_4_radio_RX_ADC_DFS_pin = fpga_0_radio_bridge_slot_4_radio_RX_ADC_DFS, DIR = O
 PORT fpga_0_radio_bridge_slot_4_radio_RX_ADC_OTRA_pin = fpga_0_radio_bridge_slot_4_radio_RX_ADC_OTRA, DIR = I
 PORT fpga_0_radio_bridge_slot_4_radio_RX_ADC_OTRB_pin = fpga_0_radio_bridge_slot_4_radio_RX_ADC_OTRB, DIR = I
 PORT fpga_0_radio_bridge_slot_4_radio_RX_ADC_PWDNA_pin = fpga_0_radio_bridge_slot_4_radio_RX_ADC_PWDNA, DIR = O
 PORT fpga_0_radio_bridge_slot_4_radio_RX_ADC_PWDNB_pin = fpga_0_radio_bridge_slot_4_radio_RX_ADC_PWDNB, DIR = O
 PORT fpga_0_radio_bridge_slot_4_radio_TxEn_pin = fpga_0_radio_bridge_slot_4_radio_TxEn, DIR = O
 PORT fpga_0_radio_bridge_slot_4_radio_RxEn_pin = fpga_0_radio_bridge_slot_4_radio_RxEn, DIR = O
 PORT fpga_0_radio_bridge_slot_4_radio_RxHP_pin = fpga_0_radio_bridge_slot_4_radio_RxHP, DIR = O
 PORT fpga_0_radio_bridge_slot_4_radio_SHDN_pin = fpga_0_radio_bridge_slot_4_radio_SHDN, DIR = O
 PORT fpga_0_radio_bridge_slot_4_radio_spi_clk_pin = fpga_0_radio_bridge_slot_4_radio_spi_clk, DIR = O
 PORT fpga_0_radio_bridge_slot_4_radio_spi_cs_pin = fpga_0_radio_bridge_slot_4_radio_spi_cs, DIR = O
 PORT fpga_0_radio_bridge_slot_4_radio_spi_data_pin = fpga_0_radio_bridge_slot_4_radio_spi_data, DIR = O
 PORT fpga_0_radio_bridge_slot_4_radio_B_pin = fpga_0_radio_bridge_slot_4_radio_B, DIR = O, VEC = [6:0]
 PORT fpga_0_radio_bridge_slot_4_radio_DAC_I_pin = fpga_0_radio_bridge_slot_4_radio_DAC_I, DIR = O, VEC = [15:0]
 PORT fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin = fpga_0_radio_bridge_slot_4_radio_DAC_Q, DIR = O, VEC = [15:0]
 PORT fpga_0_radio_bridge_slot_4_radio_ADC_I_pin = fpga_0_radio_bridge_slot_4_radio_ADC_I, DIR = I, VEC = [13:0]
 PORT fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin = fpga_0_radio_bridge_slot_4_radio_ADC_Q, DIR = I, VEC = [13:0]
 PORT fpga_0_LED_7SEGMENT_GPIO_d_out_pin = fpga_0_LED_7SEGMENT_GPIO_d_out, DIR = O, VEC = [0:6]
 PORT fpga_0_LED_7SEGMENT_1_GPIO_d_out_pin = fpga_0_LED_7SEGMENT_1_GPIO_d_out, DIR = O, VEC = [0:6]
 PORT fpga_0_LEDs_4Bit_GPIO_d_out_pin = fpga_0_LEDs_4Bit_GPIO_d_out, DIR = O, VEC = [0:3]
 PORT fpga_0_Push_Buttons_4bit_GPIO_in_pin = fpga_0_Push_Buttons_4bit_GPIO_in, DIR = I, VEC = [0:3]
 PORT fpga_0_rs232_RX_pin = fpga_0_rs232_RX, DIR = I
 PORT fpga_0_rs232_TX_pin = fpga_0_rs232_TX, DIR = O
 PORT fpga_0_eeprom_controller_DQ0_pin = fpga_0_eeprom_controller_DQ0, DIR = IO
 PORT fpga_0_Ethernet_MAC_slew1_pin = net_vcc, DIR = O
 PORT fpga_0_Ethernet_MAC_slew2_pin = net_vcc, DIR = O
 PORT fpga_0_Ethernet_MAC_PHY_rst_n_pin = fpga_0_Ethernet_MAC_PHY_rst_n, DIR = O
 PORT fpga_0_Ethernet_MAC_PHY_crs_pin = fpga_0_Ethernet_MAC_PHY_crs, DIR = I
 PORT fpga_0_Ethernet_MAC_PHY_col_pin = fpga_0_Ethernet_MAC_PHY_col, DIR = I
 PORT fpga_0_Ethernet_MAC_PHY_tx_data_pin = fpga_0_Ethernet_MAC_PHY_tx_data, DIR = O, VEC = [3:0]
 PORT fpga_0_Ethernet_MAC_PHY_tx_en_pin = fpga_0_Ethernet_MAC_PHY_tx_en, DIR = O
 PORT fpga_0_Ethernet_MAC_PHY_tx_clk_pin = fpga_0_Ethernet_MAC_PHY_tx_clk, DIR = I
 PORT fpga_0_Ethernet_MAC_PHY_tx_er_pin = fpga_0_Ethernet_MAC_PHY_tx_er, DIR = O
 PORT fpga_0_Ethernet_MAC_PHY_rx_er_pin = fpga_0_Ethernet_MAC_PHY_rx_er, DIR = I
 PORT fpga_0_Ethernet_MAC_PHY_rx_clk_pin = fpga_0_Ethernet_MAC_PHY_rx_clk, DIR = I
 PORT fpga_0_Ethernet_MAC_PHY_dv_pin = fpga_0_Ethernet_MAC_PHY_dv, DIR = I
 PORT fpga_0_Ethernet_MAC_PHY_rx_data_pin = fpga_0_Ethernet_MAC_PHY_rx_data, DIR = I, VEC = [3:0]
 PORT fpga_0_Ethernet_MAC_PHY_Mii_clk_pin = fpga_0_Ethernet_MAC_PHY_Mii_clk, DIR = IO
 PORT fpga_0_Ethernet_MAC_PHY_Mii_data_pin = fpga_0_Ethernet_MAC_PHY_Mii_data, DIR = IO
 PORT fpga_0_DIPSWs_4Bit_GPIO_in_pin = fpga_0_DIPSWs_4Bit_GPIO_in, DIR = I, VEC = [0:3]
 PORT fpga_0_SRAM0_ZBT_512Kx32_Mem_OEN_pin = fpga_0_SRAM0_ZBT_512Kx32_Mem_OEN, DIR = O, VEC = [0:0]
 PORT fpga_0_SRAM0_ZBT_512Kx32_Mem_ADV_LDN_pin = fpga_0_SRAM0_ZBT_512Kx32_Mem_ADV_LDN, DIR = O
 PORT fpga_0_SRAM0_ZBT_512Kx32_Mem_CKEN_pin = fpga_0_SRAM0_ZBT_512Kx32_Mem_CKEN, DIR = O
 PORT fpga_0_SRAM0_ZBT_512Kx32_Mem_CE_pin = fpga_0_SRAM0_ZBT_512Kx32_Mem_CE, DIR = O
 PORT fpga_0_SRAM0_ZBT_512Kx32_Mem_BEN_pin = fpga_0_SRAM0_ZBT_512Kx32_Mem_BEN, DIR = O, VEC = [0:3]
 PORT fpga_0_SRAM0_ZBT_512Kx32_Mem_WEN_pin = fpga_0_SRAM0_ZBT_512Kx32_Mem_WEN, DIR = O
 PORT fpga_0_SRAM0_ZBT_512Kx32_Mem_A_pin = fpga_0_SRAM0_ZBT_512Kx32_Mem_A, DIR = O, VEC = [11:29]
 PORT fpga_0_SRAM0_ZBT_512Kx32_Mem_DQ_pin = fpga_0_SRAM0_ZBT_512Kx32_Mem_DQ, DIR = IO, VEC = [0:31]
 PORT fpga_0_SRAM1_ZBT_512Kx32_Mem_OEN_pin = fpga_0_SRAM1_ZBT_512Kx32_Mem_OEN, DIR = O, VEC = [0:0]
 PORT fpga_0_SRAM1_ZBT_512Kx32_Mem_ADV_LDN_pin = fpga_0_SRAM1_ZBT_512Kx32_Mem_ADV_LDN, DIR = O
 PORT fpga_0_SRAM1_ZBT_512Kx32_Mem_CKEN_pin = fpga_0_SRAM1_ZBT_512Kx32_Mem_CKEN, DIR = O
 PORT fpga_0_SRAM1_ZBT_512Kx32_Mem_BEN_pin = fpga_0_SRAM1_ZBT_512Kx32_Mem_BEN, DIR = O, VEC = [0:3]
 PORT fpga_0_SRAM1_ZBT_512Kx32_Mem_WEN_pin = fpga_0_SRAM1_ZBT_512Kx32_Mem_WEN, DIR = O
 PORT fpga_0_SRAM1_ZBT_512Kx32_Mem_CE_pin = fpga_0_SRAM1_ZBT_512Kx32_Mem_CE, DIR = O
 PORT fpga_0_SRAM1_ZBT_512Kx32_Mem_A_pin = fpga_0_SRAM1_ZBT_512Kx32_Mem_A, DIR = O, VEC = [11:29]
 PORT fpga_0_SRAM1_ZBT_512Kx32_Mem_DQ_pin = fpga_0_SRAM1_ZBT_512Kx32_Mem_DQ, DIR = IO, VEC = [0:31]
 PORT fpga_0_SRAM0_CLOCK = sys_clk_s, DIR = O
 PORT fpga_0_SRAM1_CLOCK = sys_clk_s, DIR = O
 PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 40000000
 PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 1, SIGIS = RST
 PORT debug = debug_tx_pktrunning & debug_rx_payload & rssi_pkt_detect_opbw_0_rssi_pkt_det_out & rx_int_goodpkt & rx_int_badpkt & rx_pktdetreset & debug_rx_pktdone & rx_int_goodheader & ofdm_pktDetector_mimo_opbw_0_debugbusy & ofdm_pktDetector_mimo_opbw_0_debugidledifs, VEC = [0:9], DIR = O
 PORT debug_chipscopetrig_pin = debug_chipscopetrig, DIR = I
 PORT debug_GPIO_d_out_pin = fpga_0_debug_GPIO_d_out, DIR = O, VEC = [0:3]


BEGIN ppc405
 PARAMETER INSTANCE = ppc405_0
 PARAMETER HW_VER = 2.00.c
 BUS_INTERFACE JTAGPPC = jtagppc_0_0
 BUS_INTERFACE ISOCM = iocm
 BUS_INTERFACE DSOCM = docm
 BUS_INTERFACE IPLB = plb
 BUS_INTERFACE DPLB = plb
 PORT PLBCLK = sys_clk_s
 PORT C405RSTCHIPRESETREQ = C405RSTCHIPRESETREQ
 PORT C405RSTCORERESETREQ = C405RSTCORERESETREQ
 PORT C405RSTSYSRESETREQ = C405RSTSYSRESETREQ
 PORT RSTC405RESETCHIP = RSTC405RESETCHIP
 PORT RSTC405RESETCORE = RSTC405RESETCORE
 PORT RSTC405RESETSYS = RSTC405RESETSYS
 PORT BRAMISOCMCLK = sys_clk_s
 PORT BRAMDSOCMCLK = sys_clk_s
 PORT EICC405EXTINPUTIRQ = EICC405EXTINPUTIRQ
 PORT CPMC405CLOCK = proc_clk_s
END

BEGIN ppc405
 PARAMETER INSTANCE = ppc405_1
 PARAMETER HW_VER = 2.00.c
 BUS_INTERFACE JTAGPPC = jtagppc_0_1
END

BEGIN jtagppc_cntlr
 PARAMETER INSTANCE = jtagppc_0
 PARAMETER HW_VER = 2.00.a
 BUS_INTERFACE JTAGPPC0 = jtagppc_0_0
 BUS_INTERFACE JTAGPPC1 = jtagppc_0_1
END

BEGIN proc_sys_reset
 PARAMETER INSTANCE = reset_block
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT Ext_Reset_In = sys_rst_s
 PORT Slowest_sync_clk = sys_clk_OPB
 PORT Chip_Reset_Req = C405RSTCHIPRESETREQ
 PORT Core_Reset_Req = C405RSTCORERESETREQ
 PORT System_Reset_Req = C405RSTSYSRESETREQ
 PORT Rstc405resetchip = RSTC405RESETCHIP
 PORT Rstc405resetcore = RSTC405RESETCORE
 PORT Rstc405resetsys = RSTC405RESETSYS
 PORT Bus_Struct_Reset = sys_bus_reset
 PORT Dcm_locked = dcm_0_lock
 PORT Peripheral_Reset = pcoreReset
END

BEGIN isocm_v10
 PARAMETER INSTANCE = iocm
 PARAMETER HW_VER = 2.00.b
 PARAMETER C_ISCNTLVALUE = 0x83
 PORT ISOCM_Clk = sys_clk_s
 PORT sys_rst = sys_bus_reset
END

BEGIN isbram_if_cntlr
 PARAMETER INSTANCE = iocm_cntlr
 PARAMETER HW_VER = 3.00.b
 PARAMETER C_BASEADDR = 0xfffe0000
 PARAMETER C_HIGHADDR = 0xffffffff
 BUS_INTERFACE ISOCM = iocm
 BUS_INTERFACE DCR_WRITE_PORT = isocm_porta
 BUS_INTERFACE INSTRN_READ_PORT = isocm_portb
END

BEGIN bram_block
 PARAMETER INSTANCE = isocm_bram
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = isocm_porta
 BUS_INTERFACE PORTB = isocm_portb
END

BEGIN dsocm_v10
 PARAMETER INSTANCE = docm
 PARAMETER HW_VER = 2.00.b
 PARAMETER C_DSCNTLVALUE = 0x83
 PORT DSOCM_Clk = sys_clk_s
 PORT sys_rst = sys_bus_reset
END

BEGIN dsbram_if_cntlr
 PARAMETER INSTANCE = docm_cntlr
 PARAMETER HW_VER = 3.00.b
 PARAMETER C_BASEADDR = 0xc0200000
 PARAMETER C_HIGHADDR = 0xc020ffff
 BUS_INTERFACE DSOCM = docm
 BUS_INTERFACE PORTA = dsocm_porta
END

BEGIN bram_block
 PARAMETER INSTANCE = dsocm_bram
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = dsocm_porta
END

BEGIN plb_v34
 PARAMETER INSTANCE = plb
 PARAMETER HW_VER = 1.02.a
 PARAMETER C_DCR_INTFCE = 0
 PARAMETER C_NUM_OPBCLK_PLB2OPB_REARB = 100
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT SYS_Rst = sys_bus_reset
 PORT PLB_Clk = sys_clk_s
END

BEGIN opb_v20
 PARAMETER INSTANCE = opb
 PARAMETER HW_VER = 1.10.c
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT SYS_Rst = sys_bus_reset
 PORT OPB_Clk = sys_clk_OPB
END

BEGIN plb2opb_bridge
 PARAMETER INSTANCE = plb2opb
 PARAMETER HW_VER = 1.01.a
 PARAMETER C_DCR_INTFCE = 0
 PARAMETER C_NUM_ADDR_RNG = 1
 PARAMETER C_RNG0_BASEADDR = 0x40000000
 PARAMETER C_RNG0_HIGHADDR = 0x7fffffff
 BUS_INTERFACE SPLB = plb
 BUS_INTERFACE MOPB = opb
 PORT PLB_Clk = sys_clk_s
 PORT OPB_Clk = sys_clk_OPB
END

BEGIN opb_gpio
 PARAMETER INSTANCE = LED_7SEGMENT
 PARAMETER HW_VER = 3.01.b
 PARAMETER C_GPIO_WIDTH = 7
 PARAMETER C_IS_DUAL = 0
 PARAMETER C_IS_BIDIR = 0
 PARAMETER C_ALL_INPUTS = 0
 PARAMETER C_BASEADDR = 0x40000000
 PARAMETER C_HIGHADDR = 0x4000ffff
 BUS_INTERFACE SOPB = opb
 PORT OPB_Clk = sys_clk_OPB
 PORT GPIO_d_out = fpga_0_LED_7SEGMENT_GPIO_d_out
END

BEGIN opb_gpio
 PARAMETER INSTANCE = LED_7SEGMENT_1
 PARAMETER HW_VER = 3.01.b
 PARAMETER C_GPIO_WIDTH = 7
 PARAMETER C_IS_DUAL = 0
 PARAMETER C_IS_BIDIR = 0
 PARAMETER C_ALL_INPUTS = 0
 PARAMETER C_BASEADDR = 0x40020000
 PARAMETER C_HIGHADDR = 0x4002ffff
 BUS_INTERFACE SOPB = opb
 PORT OPB_Clk = sys_clk_OPB
 PORT GPIO_d_out = fpga_0_LED_7SEGMENT_1_GPIO_d_out
END

BEGIN opb_gpio
 PARAMETER INSTANCE = LEDs_4Bit
 PARAMETER HW_VER = 3.01.b
 PARAMETER C_GPIO_WIDTH = 4
 PARAMETER C_IS_DUAL = 0
 PARAMETER C_IS_BIDIR = 0
 PARAMETER C_ALL_INPUTS = 0
 PARAMETER C_BASEADDR = 0x40060000
 PARAMETER C_HIGHADDR = 0x4006ffff
 BUS_INTERFACE SOPB = opb
 PORT OPB_Clk = sys_clk_OPB
 PORT GPIO_d_out = fpga_0_LEDs_4Bit_GPIO_d_out
END

BEGIN opb_gpio
 PARAMETER INSTANCE = Push_Buttons_4bit
 PARAMETER HW_VER = 3.01.b
 PARAMETER C_INTERRUPT_PRESENT = 1
 PARAMETER C_GPIO_WIDTH = 4
 PARAMETER C_IS_DUAL = 0
 PARAMETER C_IS_BIDIR = 0
 PARAMETER C_ALL_INPUTS = 1
 PARAMETER C_BASEADDR = 0x40080000
 PARAMETER C_HIGHADDR = 0x4008ffff
 BUS_INTERFACE SOPB = opb
 PORT OPB_Clk = sys_clk_OPB
 PORT IP2INTC_Irpt = Push_Buttons_4bit_IP2INTC_Irpt
 PORT GPIO_in = fpga_0_Push_Buttons_4bit_GPIO_in
END

BEGIN opb_gpio
 PARAMETER INSTANCE = DIPSWs_4Bit
 PARAMETER HW_VER = 3.01.b
 PARAMETER C_GPIO_WIDTH = 4
 PARAMETER C_IS_DUAL = 0
 PARAMETER C_IS_BIDIR = 0
 PARAMETER C_ALL_INPUTS = 1
 PARAMETER C_BASEADDR = 0x400a0000
 PARAMETER C_HIGHADDR = 0x400affff
 BUS_INTERFACE SOPB = opb
 PORT OPB_Clk = sys_clk_OPB
 PORT GPIO_in = fpga_0_DIPSWs_4Bit_GPIO_in
END

BEGIN opb_uartlite
 PARAMETER INSTANCE = rs232
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BAUDRATE = 57600
 PARAMETER C_DATA_BITS = 8
 PARAMETER C_ODD_PARITY = 0
 PARAMETER C_USE_PARITY = 0
 PARAMETER C_CLK_FREQ = 40000000
 PARAMETER C_BASEADDR = 0x40600000
 PARAMETER C_HIGHADDR = 0x4060ffff
 BUS_INTERFACE SOPB = opb
 PORT OPB_Clk = sys_clk_OPB
 PORT RX = fpga_0_rs232_RX
 PORT TX = fpga_0_rs232_TX
END

BEGIN clock_board_config
 PARAMETER INSTANCE = clk_board_config
 PARAMETER HW_VER = 1.04.a
 PARAMETER radio_clk_out0_mode = 0x1eff
 PARAMETER radio_clk_out1_mode = 0x1eff
 PARAMETER radio_clk_out2_mode = 0x1eff
 PARAMETER radio_clk_out3_mode = 0x1eff
 PARAMETER logic_clk_out0_mode = 0x08ff
 PARAMETER logic_clk_out1_mode = 0x08ff
 PARAMETER logic_clk_out2_mode = 0x08ff
 PARAMETER logic_clk_out3_mode = 0x08ff
 PORT sys_clk = fpga_0_clk_board_config_sys_clk
 PORT sys_rst = net_gnd
 PORT cfg_radio_dat_out = fpga_0_clk_board_config_cfg_radio_dat_out
 PORT cfg_radio_csb_out = fpga_0_clk_board_config_cfg_radio_csb_out
 PORT cfg_radio_en_out = fpga_0_clk_board_config_cfg_radio_en_out
 PORT cfg_radio_clk_out = fpga_0_clk_board_config_cfg_radio_clk_out
 PORT cfg_logic_dat_out = fpga_0_clk_board_config_cfg_logic_dat_out
 PORT cfg_logic_csb_out = fpga_0_clk_board_config_cfg_logic_csb_out
 PORT cfg_logic_en_out = fpga_0_clk_board_config_cfg_logic_en_out
 PORT cfg_logic_clk_out = fpga_0_clk_board_config_cfg_logic_clk_out
 PORT config_invalid = clkBoardConfig_DCM_Reset
END

BEGIN eeprom
 PARAMETER INSTANCE = eeprom_controller
 PARAMETER HW_VER = 1.02.a
 PARAMETER C_BASEADDR = 0x73800000
 PARAMETER C_HIGHADDR = 0x7380ffff
 BUS_INTERFACE SOPB = opb
 PORT OPB_Clk = sys_clk_OPB
 PORT DQ0 = fpga_0_eeprom_controller_DQ0
 PORT DQ2_T = eeprom_controller_DQ2_T_radio_bridge_slot_2_user_EEPROM_IO_T
 PORT DQ2_O = eeprom_controller_DQ2_O_radio_bridge_slot_2_user_EEPROM_IO_O
 PORT DQ2_I = eeprom_controller_DQ2_I_radio_bridge_slot_2_user_EEPROM_IO_I
 PORT DQ3_T = eeprom_controller_DQ3_T_radio_bridge_slot_3_user_EEPROM_IO_T
 PORT DQ3_O = eeprom_controller_DQ3_O_radio_bridge_slot_3_user_EEPROM_IO_O
 PORT DQ3_I = eeprom_controller_DQ3_I_radio_bridge_slot_3_user_EEPROM_IO_I
 PORT DQ5_I = net_vcc
 PORT DQ6_I = net_vcc
 PORT DQ7_I = net_vcc
 PORT DQ1_T = eeprom_controller_DQ1_T_radio_bridge_slot_1_user_EEPROM_IO_T
 PORT DQ1_O = eeprom_controller_DQ1_O_radio_bridge_slot_1_user_EEPROM_IO_O
 PORT DQ1_I = eeprom_controller_DQ1_I_radio_bridge_slot_1_user_EEPROM_IO_I
 PORT DQ4_T = eeprom_controller_DQ4_T_radio_bridge_slot_4_user_EEPROM_IO_T
 PORT DQ4_O = eeprom_controller_DQ4_O_radio_bridge_slot_4_user_EEPROM_IO_O
 PORT DQ4_I = eeprom_controller_DQ4_I_radio_bridge_slot_4_user_EEPROM_IO_I
END

BEGIN plb_ethernet
 PARAMETER INSTANCE = Ethernet_MAC
 PARAMETER HW_VER = 1.01.a
 PARAMETER C_DMA_PRESENT = 2
 PARAMETER C_IPIF_FIFO_DEPTH = 32768
 PARAMETER C_PLB_CLK_PERIOD_PS = 12500
 PARAMETER C_BASEADDR = 0x80400000
 PARAMETER C_HIGHADDR = 0x8040ffff
 BUS_INTERFACE MSPLB = plb
 PORT IP2INTC_Irpt = Ethernet_MAC_IP2INTC_Irpt
 PORT PHY_rst_n = fpga_0_Ethernet_MAC_PHY_rst_n
 PORT PHY_crs = fpga_0_Ethernet_MAC_PHY_crs
 PORT PHY_col = fpga_0_Ethernet_MAC_PHY_col
 PORT PHY_tx_data = fpga_0_Ethernet_MAC_PHY_tx_data
 PORT PHY_tx_en = fpga_0_Ethernet_MAC_PHY_tx_en
 PORT PHY_tx_clk = fpga_0_Ethernet_MAC_PHY_tx_clk
 PORT PHY_tx_er = fpga_0_Ethernet_MAC_PHY_tx_er
 PORT PHY_rx_er = fpga_0_Ethernet_MAC_PHY_rx_er
 PORT PHY_rx_clk = fpga_0_Ethernet_MAC_PHY_rx_clk
 PORT PHY_dv = fpga_0_Ethernet_MAC_PHY_dv
 PORT PHY_rx_data = fpga_0_Ethernet_MAC_PHY_rx_data
 PORT PHY_Mii_clk = fpga_0_Ethernet_MAC_PHY_Mii_clk
 PORT PHY_Mii_data = fpga_0_Ethernet_MAC_PHY_Mii_data
END

BEGIN radio_controller
 PARAMETER INSTANCE = radio_controller_0
 PARAMETER HW_VER = 1.10.a
 PARAMETER C_BASEADDR = 0x7ac00000
 PARAMETER C_HIGHADDR = 0x7ac0ffff
 BUS_INTERFACE SOPB = opb
 PORT spi_clk = radio_bridge_slot_1_controller_spi_clk_radio_bridge_slot_2_controller_spi_clk_radio_bridge_slot_3_controller_spi_clk_radio_bridge_slot_4_controller_spi_clk_radio_controller_0_spi_clk
 PORT data_out = radio_bridge_slot_1_controller_spi_data_radio_bridge_slot_2_controller_spi_data_radio_bridge_slot_3_controller_spi_data_radio_bridge_slot_4_controller_spi_data_radio_controller_0_data_out
 PORT radio1_cs = radio_bridge_slot_1_controller_radio_cs_radio_controller_0_radio1_cs
 PORT radio2_cs = radio_bridge_slot_2_controller_radio_cs_radio_controller_0_radio2_cs
 PORT radio3_cs = radio_bridge_slot_3_controller_radio_cs_radio_controller_0_radio3_cs
 PORT radio4_cs = radio_bridge_slot_4_controller_radio_cs_radio_controller_0_radio4_cs
 PORT dac1_cs = radio_bridge_slot_1_controller_dac_cs_radio_controller_0_dac1_cs
 PORT dac2_cs = radio_bridge_slot_2_controller_dac_cs_radio_controller_0_dac2_cs
 PORT dac3_cs = radio_bridge_slot_3_controller_dac_cs_radio_controller_0_dac3_cs
 PORT dac4_cs = radio_bridge_slot_4_controller_dac_cs_radio_controller_0_dac4_cs
 PORT radio1_SHDN = radio_bridge_slot_1_controller_SHDN_radio_controller_0_radio1_SHDN
 PORT radio1_TxEn = radio_bridge_slot_1_controller_TxEn_radio_controller_0_radio1_TxEn
 PORT radio1_RxEn = radio_bridge_slot_1_controller_RxEn_radio_controller_0_radio1_RxEn
 PORT radio1_RxHP = radio_bridge_slot_1_controller_RxHP_radio_controller_0_radio1_RxHP
 PORT radio1_LD = radio_bridge_slot_1_controller_LD_radio_controller_0_radio1_LD
 PORT radio1_24PA = radio_bridge_slot_1_controller_24PA_radio_controller_0_radio1_24PA
 PORT radio1_5PA = radio_bridge_slot_1_controller_5PA_radio_controller_0_radio1_5PA
 PORT radio1_ANTSW = radio_bridge_slot_1_controller_ANTSW_radio_controller_0_radio1_ANTSW
 PORT radio1_LED = radio_bridge_slot_1_controller_LED_radio_controller_0_radio1_LED
 PORT radio1_ADC_RX_DCS = radio_bridge_slot_1_controller_RX_ADC_DCS_radio_controller_0_radio1_ADC_RX_DCS
 PORT radio1_ADC_RX_DFS = radio_bridge_slot_1_controller_RX_ADC_DFS_radio_controller_0_radio1_ADC_RX_DFS
 PORT radio1_ADC_RX_OTRA = radio_bridge_slot_1_controller_RX_ADC_OTRA_radio_controller_0_radio1_ADC_RX_OTRA
 PORT radio1_ADC_RX_OTRB = radio_bridge_slot_1_controller_RX_ADC_OTRB_radio_controller_0_radio1_ADC_RX_OTRB
 PORT radio1_ADC_RX_PWDNA = radio_bridge_slot_1_controller_RX_ADC_PWDNA_radio_controller_0_radio1_ADC_RX_PWDNA
 PORT radio1_ADC_RX_PWDNB = radio_bridge_slot_1_controller_RX_ADC_PWDNB_radio_controller_0_radio1_ADC_RX_PWDNB
 PORT radio1_DIPSW = radio_bridge_slot_1_controller_DIPSW_radio_controller_0_radio1_DIPSW
 PORT radio1_RSSI_ADC_CLAMP = radio_bridge_slot_1_controller_RSSI_ADC_CLAMP_radio_controller_0_radio1_RSSI_ADC_CLAMP
 PORT radio1_RSSI_ADC_HIZ = radio_bridge_slot_1_controller_RSSI_ADC_HIZ_radio_controller_0_radio1_RSSI_ADC_HIZ
 PORT radio1_RSSI_ADC_OTR = radio_bridge_slot_1_controller_RSSI_ADC_OTR_radio_controller_0_radio1_RSSI_ADC_OTR
 PORT radio1_RSSI_ADC_SLEEP = radio_bridge_slot_1_controller_RSSI_ADC_SLEEP_radio_controller_0_radio1_RSSI_ADC_SLEEP
 PORT radio1_RSSI_ADC_D = radio_bridge_slot_1_controller_RSSI_ADC_D_radio_controller_0_radio1_RSSI_ADC_D
 PORT radio1_TX_DAC_PLL_LOCK = radio_bridge_slot_1_controller_dac_PLL_LOCK_radio_controller_0_radio1_TX_DAC_PLL_LOCK
 PORT radio1_TX_DAC_RESET = radio_bridge_slot_1_controller_dac_RESET_radio_controller_0_radio1_TX_DAC_RESET
 PORT radio1_SHDN_external = radio_bridge_slot_1_controller_SHDN_external_radio_controller_0_radio1_SHDN_external
 PORT radio1_TxEn_external = radio_bridge_slot_1_controller_TxEn_external_radio_controller_0_radio1_TxEn_external
 PORT radio1_RxEn_external = radio_bridge_slot_1_controller_RxEn_external_radio_controller_0_radio1_RxEn_external
 PORT radio1_RxHP_external = radio_bridge_slot_1_controller_RxHP_external_radio_controller_0_radio1_RxHP_external
 PORT radio1_TxGain = radio_bridge_slot_1_user_Tx_gain_radio_controller_0_radio1_TxGain
 PORT radio1_TxStart = radio_bridge_slot_1_controller_TxStart_radio_controller_0_radio1_TxStart
 PORT radio2_SHDN = radio_bridge_slot_2_controller_SHDN_radio_controller_0_radio2_SHDN
 PORT radio2_TxEn = radio_bridge_slot_2_controller_TxEn_radio_controller_0_radio2_TxEn
 PORT radio2_RxEn = radio_bridge_slot_2_controller_RxEn_radio_controller_0_radio2_RxEn
 PORT radio2_RxHP = radio_bridge_slot_2_controller_RxHP_radio_controller_0_radio2_RxHP
 PORT radio2_LD = radio_bridge_slot_2_controller_LD_radio_controller_0_radio2_LD
 PORT radio2_24PA = radio_bridge_slot_2_controller_24PA_radio_controller_0_radio2_24PA
 PORT radio2_5PA = radio_bridge_slot_2_controller_5PA_radio_controller_0_radio2_5PA
 PORT radio2_ANTSW = radio_bridge_slot_2_controller_ANTSW_radio_controller_0_radio2_ANTSW
 PORT radio2_LED = radio_bridge_slot_2_controller_LED_radio_controller_0_radio2_LED
 PORT radio2_ADC_RX_DCS = radio_bridge_slot_2_controller_RX_ADC_DCS_radio_controller_0_radio2_ADC_RX_DCS
 PORT radio2_ADC_RX_DFS = radio_bridge_slot_2_controller_RX_ADC_DFS_radio_controller_0_radio2_ADC_RX_DFS
 PORT radio2_ADC_RX_OTRA = radio_bridge_slot_2_controller_RX_ADC_OTRA_radio_controller_0_radio2_ADC_RX_OTRA
 PORT radio2_ADC_RX_OTRB = radio_bridge_slot_2_controller_RX_ADC_OTRB_radio_controller_0_radio2_ADC_RX_OTRB
 PORT radio2_ADC_RX_PWDNA = radio_bridge_slot_2_controller_RX_ADC_PWDNA_radio_controller_0_radio2_ADC_RX_PWDNA
 PORT radio2_ADC_RX_PWDNB = radio_bridge_slot_2_controller_RX_ADC_PWDNB_radio_controller_0_radio2_ADC_RX_PWDNB
 PORT radio2_DIPSW = radio_bridge_slot_2_controller_DIPSW_radio_controller_0_radio2_DIPSW
 PORT radio2_RSSI_ADC_CLAMP = radio_bridge_slot_2_controller_RSSI_ADC_CLAMP_radio_controller_0_radio2_RSSI_ADC_CLAMP
 PORT radio2_RSSI_ADC_HIZ = radio_bridge_slot_2_controller_RSSI_ADC_HIZ_radio_controller_0_radio2_RSSI_ADC_HIZ
 PORT radio2_RSSI_ADC_OTR = radio_bridge_slot_2_controller_RSSI_ADC_OTR_radio_controller_0_radio2_RSSI_ADC_OTR
 PORT radio2_RSSI_ADC_SLEEP = radio_bridge_slot_2_controller_RSSI_ADC_SLEEP_radio_controller_0_radio2_RSSI_ADC_SLEEP
 PORT radio2_RSSI_ADC_D = radio_bridge_slot_2_controller_RSSI_ADC_D_radio_controller_0_radio2_RSSI_ADC_D
 PORT radio2_TX_DAC_PLL_LOCK = radio_bridge_slot_2_controller_dac_PLL_LOCK_radio_controller_0_radio2_TX_DAC_PLL_LOCK
 PORT radio2_TX_DAC_RESET = radio_bridge_slot_2_controller_dac_RESET_radio_controller_0_radio2_TX_DAC_RESET
 PORT radio2_SHDN_external = radio_bridge_slot_2_controller_SHDN_external_radio_controller_0_radio2_SHDN_external
 PORT radio2_TxEn_external = radio_bridge_slot_2_controller_TxEn_external_radio_controller_0_radio2_TxEn_external
 PORT radio2_RxEn_external = radio_bridge_slot_2_controller_RxEn_external_radio_controller_0_radio2_RxEn_external
 PORT radio2_RxHP_external = radio_bridge_slot_2_controller_RxHP_external_radio_controller_0_radio2_RxHP_external
 PORT radio2_TxGain = radio_bridge_slot_2_user_Tx_gain_radio_controller_0_radio2_TxGain
 PORT radio2_TxStart = radio_bridge_slot_2_controller_TxStart_radio_controller_0_radio2_TxStart
 PORT radio3_SHDN = radio_bridge_slot_3_controller_SHDN_radio_controller_0_radio3_SHDN
 PORT radio3_TxEn = radio_bridge_slot_3_controller_TxEn_radio_controller_0_radio3_TxEn
 PORT radio3_RxEn = radio_bridge_slot_3_controller_RxEn_radio_controller_0_radio3_RxEn
 PORT radio3_RxHP = radio_bridge_slot_3_controller_RxHP_radio_controller_0_radio3_RxHP
 PORT radio3_LD = radio_bridge_slot_3_controller_LD_radio_controller_0_radio3_LD
 PORT radio3_24PA = radio_bridge_slot_3_controller_24PA_radio_controller_0_radio3_24PA
 PORT radio3_5PA = radio_bridge_slot_3_controller_5PA_radio_controller_0_radio3_5PA
 PORT radio3_ANTSW = radio_bridge_slot_3_controller_ANTSW_radio_controller_0_radio3_ANTSW
 PORT radio3_LED = radio_bridge_slot_3_controller_LED_radio_controller_0_radio3_LED
 PORT radio3_ADC_RX_DCS = radio_bridge_slot_3_controller_RX_ADC_DCS_radio_controller_0_radio3_ADC_RX_DCS
 PORT radio3_ADC_RX_DFS = radio_bridge_slot_3_controller_RX_ADC_DFS_radio_controller_0_radio3_ADC_RX_DFS
 PORT radio3_ADC_RX_OTRA = radio_bridge_slot_3_controller_RX_ADC_OTRA_radio_controller_0_radio3_ADC_RX_OTRA
 PORT radio3_ADC_RX_OTRB = radio_bridge_slot_3_controller_RX_ADC_OTRB_radio_controller_0_radio3_ADC_RX_OTRB
 PORT radio3_ADC_RX_PWDNA = radio_bridge_slot_3_controller_RX_ADC_PWDNA_radio_controller_0_radio3_ADC_RX_PWDNA
 PORT radio3_ADC_RX_PWDNB = radio_bridge_slot_3_controller_RX_ADC_PWDNB_radio_controller_0_radio3_ADC_RX_PWDNB
 PORT radio3_DIPSW = radio_bridge_slot_3_controller_DIPSW_radio_controller_0_radio3_DIPSW
 PORT radio3_RSSI_ADC_CLAMP = radio_bridge_slot_3_controller_RSSI_ADC_CLAMP_radio_controller_0_radio3_RSSI_ADC_CLAMP
 PORT radio3_RSSI_ADC_HIZ = radio_bridge_slot_3_controller_RSSI_ADC_HIZ_radio_controller_0_radio3_RSSI_ADC_HIZ
 PORT radio3_RSSI_ADC_OTR = radio_bridge_slot_3_controller_RSSI_ADC_OTR_radio_controller_0_radio3_RSSI_ADC_OTR
 PORT radio3_RSSI_ADC_SLEEP = radio_bridge_slot_3_controller_RSSI_ADC_SLEEP_radio_controller_0_radio3_RSSI_ADC_SLEEP
 PORT radio3_RSSI_ADC_D = radio_bridge_slot_3_controller_RSSI_ADC_D_radio_controller_0_radio3_RSSI_ADC_D
 PORT radio3_TX_DAC_PLL_LOCK = radio_bridge_slot_3_controller_dac_PLL_LOCK_radio_controller_0_radio3_TX_DAC_PLL_LOCK
 PORT radio3_TX_DAC_RESET = radio_bridge_slot_3_controller_dac_RESET_radio_controller_0_radio3_TX_DAC_RESET
 PORT radio3_SHDN_external = radio_bridge_slot_3_controller_SHDN_external_radio_controller_0_radio3_SHDN_external
 PORT radio3_TxEn_external = radio_bridge_slot_3_controller_TxEn_external_radio_controller_0_radio3_TxEn_external
 PORT radio3_RxEn_external = radio_bridge_slot_3_controller_RxEn_external_radio_controller_0_radio3_RxEn_external
 PORT radio3_RxHP_external = radio_bridge_slot_3_controller_RxHP_external_radio_controller_0_radio3_RxHP_external
 PORT radio3_TxGain = radio_bridge_slot_3_user_Tx_gain_radio_controller_0_radio3_TxGain
 PORT radio3_TxStart = radio_bridge_slot_3_controller_TxStart_radio_controller_0_radio3_TxStart
 PORT radio4_SHDN = radio_bridge_slot_4_controller_SHDN_radio_controller_0_radio4_SHDN
 PORT radio4_TxEn = radio_bridge_slot_4_controller_TxEn_radio_controller_0_radio4_TxEn
 PORT radio4_RxEn = radio_bridge_slot_4_controller_RxEn_radio_controller_0_radio4_RxEn
 PORT radio4_RxHP = radio_bridge_slot_4_controller_RxHP_radio_controller_0_radio4_RxHP
 PORT radio4_LD = radio_bridge_slot_4_controller_LD_radio_controller_0_radio4_LD
 PORT radio4_24PA = radio_bridge_slot_4_controller_24PA_radio_controller_0_radio4_24PA
 PORT radio4_5PA = radio_bridge_slot_4_controller_5PA_radio_controller_0_radio4_5PA
 PORT radio4_ANTSW = radio_bridge_slot_4_controller_ANTSW_radio_controller_0_radio4_ANTSW
 PORT radio4_LED = radio_bridge_slot_4_controller_LED_radio_controller_0_radio4_LED
 PORT radio4_ADC_RX_DCS = radio_bridge_slot_4_controller_RX_ADC_DCS_radio_controller_0_radio4_ADC_RX_DCS
 PORT radio4_ADC_RX_DFS = radio_bridge_slot_4_controller_RX_ADC_DFS_radio_controller_0_radio4_ADC_RX_DFS
 PORT radio4_ADC_RX_OTRA = radio_bridge_slot_4_controller_RX_ADC_OTRA_radio_controller_0_radio4_ADC_RX_OTRA
 PORT radio4_ADC_RX_OTRB = radio_bridge_slot_4_controller_RX_ADC_OTRB_radio_controller_0_radio4_ADC_RX_OTRB
 PORT radio4_ADC_RX_PWDNA = radio_bridge_slot_4_controller_RX_ADC_PWDNA_radio_controller_0_radio4_ADC_RX_PWDNA
 PORT radio4_ADC_RX_PWDNB = radio_bridge_slot_4_controller_RX_ADC_PWDNB_radio_controller_0_radio4_ADC_RX_PWDNB
 PORT radio4_DIPSW = radio_bridge_slot_4_controller_DIPSW_radio_controller_0_radio4_DIPSW
 PORT radio4_RSSI_ADC_CLAMP = radio_bridge_slot_4_controller_RSSI_ADC_CLAMP_radio_controller_0_radio4_RSSI_ADC_CLAMP
 PORT radio4_RSSI_ADC_HIZ = radio_bridge_slot_4_controller_RSSI_ADC_HIZ_radio_controller_0_radio4_RSSI_ADC_HIZ
 PORT radio4_RSSI_ADC_OTR = radio_bridge_slot_4_controller_RSSI_ADC_OTR_radio_controller_0_radio4_RSSI_ADC_OTR
 PORT radio4_RSSI_ADC_SLEEP = radio_bridge_slot_4_controller_RSSI_ADC_SLEEP_radio_controller_0_radio4_RSSI_ADC_SLEEP
 PORT radio4_RSSI_ADC_D = radio_bridge_slot_4_controller_RSSI_ADC_D_radio_controller_0_radio4_RSSI_ADC_D
 PORT radio4_TX_DAC_PLL_LOCK = radio_bridge_slot_4_controller_dac_PLL_LOCK_radio_controller_0_radio4_TX_DAC_PLL_LOCK
 PORT radio4_TX_DAC_RESET = radio_bridge_slot_4_controller_dac_RESET_radio_controller_0_radio4_TX_DAC_RESET
 PORT radio4_SHDN_external = radio_bridge_slot_4_controller_SHDN_external_radio_controller_0_radio4_SHDN_external
 PORT radio4_TxEn_external = radio_bridge_slot_4_controller_TxEn_external_radio_controller_0_radio4_TxEn_external
 PORT radio4_RxEn_external = radio_bridge_slot_4_controller_RxEn_external_radio_controller_0_radio4_RxEn_external
 PORT radio4_RxHP_external = radio_bridge_slot_4_controller_RxHP_external_radio_controller_0_radio4_RxHP_external
 PORT radio4_TxGain = radio_bridge_slot_4_user_Tx_gain_radio_controller_0_radio4_TxGain
 PORT radio4_TxStart = radio_bridge_slot_4_controller_TxStart_radio_controller_0_radio4_TxStart
 PORT OPB_Clk = sys_clk_OPB
END

Amir · 2008-Nov-12 08:02:08

and the second part:

p.s.: radio controller and radio bridge sections were copied from 4x4 WARPLAB MHS during the course of debugging this issue.

Code:

BEGIN radio_bridge
 PARAMETER INSTANCE = radio_bridge_slot_1
 PARAMETER HW_VER = 1.08.a
 PORT converter_clock_out = fpga_0_radio_bridge_slot_1_converter_clock_out
 PORT radio_B = fpga_0_radio_bridge_slot_1_radio_B
 PORT radio_ADC_I = fpga_0_radio_bridge_slot_1_radio_ADC_I
 PORT radio_ADC_Q = fpga_0_radio_bridge_slot_1_radio_ADC_Q
 PORT radio_DAC_I = fpga_0_radio_bridge_slot_1_radio_DAC_I
 PORT radio_DAC_Q = fpga_0_radio_bridge_slot_1_radio_DAC_Q
 PORT controller_spi_clk = radio_bridge_slot_1_controller_spi_clk_radio_bridge_slot_2_controller_spi_clk_radio_bridge_slot_3_controller_spi_clk_radio_bridge_slot_4_controller_spi_clk_radio_controller_0_spi_clk
 PORT controller_spi_data = radio_bridge_slot_1_controller_spi_data_radio_bridge_slot_2_controller_spi_data_radio_bridge_slot_3_controller_spi_data_radio_bridge_slot_4_controller_spi_data_radio_controller_0_data_out
 PORT controller_radio_cs = radio_bridge_slot_1_controller_radio_cs_radio_controller_0_radio1_cs
 PORT controller_dac_cs = radio_bridge_slot_1_controller_dac_cs_radio_controller_0_dac1_cs
 PORT controller_SHDN = radio_bridge_slot_1_controller_SHDN_radio_controller_0_radio1_SHDN
 PORT controller_TxEn = radio_bridge_slot_1_controller_TxEn_radio_controller_0_radio1_TxEn
 PORT controller_RxEn = radio_bridge_slot_1_controller_RxEn_radio_controller_0_radio1_RxEn
 PORT controller_RxHP = radio_bridge_slot_1_controller_RxHP_radio_controller_0_radio1_RxHP
 PORT controller_24PA = radio_bridge_slot_1_controller_24PA_radio_controller_0_radio1_24PA
 PORT controller_5PA = radio_bridge_slot_1_controller_5PA_radio_controller_0_radio1_5PA
 PORT controller_ANTSW = radio_bridge_slot_1_controller_ANTSW_radio_controller_0_radio1_ANTSW
 PORT controller_LED = radio_bridge_slot_1_controller_LED_radio_controller_0_radio1_LED
 PORT controller_RX_ADC_DCS = radio_bridge_slot_1_controller_RX_ADC_DCS_radio_controller_0_radio1_ADC_RX_DCS
 PORT controller_RX_ADC_DFS = radio_bridge_slot_1_controller_RX_ADC_DFS_radio_controller_0_radio1_ADC_RX_DFS
 PORT controller_RX_ADC_PWDNA = radio_bridge_slot_1_controller_RX_ADC_PWDNA_radio_controller_0_radio1_ADC_RX_PWDNA
 PORT controller_RX_ADC_PWDNB = radio_bridge_slot_1_controller_RX_ADC_PWDNB_radio_controller_0_radio1_ADC_RX_PWDNB
 PORT controller_DIPSW = radio_bridge_slot_1_controller_DIPSW_radio_controller_0_radio1_DIPSW
 PORT controller_RSSI_ADC_CLAMP = radio_bridge_slot_1_controller_RSSI_ADC_CLAMP_radio_controller_0_radio1_RSSI_ADC_CLAMP
 PORT controller_RSSI_ADC_HIZ = radio_bridge_slot_1_controller_RSSI_ADC_HIZ_radio_controller_0_radio1_RSSI_ADC_HIZ
 PORT controller_RSSI_ADC_SLEEP = radio_bridge_slot_1_controller_RSSI_ADC_SLEEP_radio_controller_0_radio1_RSSI_ADC_SLEEP
 PORT controller_RSSI_ADC_D = radio_bridge_slot_1_controller_RSSI_ADC_D_radio_controller_0_radio1_RSSI_ADC_D
 PORT controller_LD = radio_bridge_slot_1_controller_LD_radio_controller_0_radio1_LD
 PORT controller_RX_ADC_OTRA = radio_bridge_slot_1_controller_RX_ADC_OTRA_radio_controller_0_radio1_ADC_RX_OTRA
 PORT controller_RX_ADC_OTRB = radio_bridge_slot_1_controller_RX_ADC_OTRB_radio_controller_0_radio1_ADC_RX_OTRB
 PORT controller_RSSI_ADC_OTR = radio_bridge_slot_1_controller_RSSI_ADC_OTR_radio_controller_0_radio1_RSSI_ADC_OTR
 PORT controller_dac_PLL_LOCK = radio_bridge_slot_1_controller_dac_PLL_LOCK_radio_controller_0_radio1_TX_DAC_PLL_LOCK
 PORT controller_dac_RESET = radio_bridge_slot_1_controller_dac_RESET_radio_controller_0_radio1_TX_DAC_RESET
 PORT user_Tx_gain = radio_bridge_slot_1_user_Tx_gain_radio_controller_0_radio1_TxGain
 PORT controller_TxStart = radio_bridge_slot_1_controller_TxStart_radio_controller_0_radio1_TxStart
 PORT controller_SHDN_external = radio_bridge_slot_1_controller_SHDN_external_radio_controller_0_radio1_SHDN_external
 PORT controller_RxEn_external = radio_bridge_slot_1_controller_RxEn_external_radio_controller_0_radio1_RxEn_external
 PORT controller_TxEn_external = radio_bridge_slot_1_controller_TxEn_external_radio_controller_0_radio1_TxEn_external
 PORT controller_RxHP_external = radio_bridge_slot_1_controller_RxHP_external_radio_controller_0_radio1_RxHP_external
 PORT dac_spi_data = fpga_0_radio_bridge_slot_1_dac_spi_data
 PORT dac_spi_cs = fpga_0_radio_bridge_slot_1_dac_spi_cs
 PORT dac_spi_clk = fpga_0_radio_bridge_slot_1_dac_spi_clk
 PORT radio_spi_clk = fpga_0_radio_bridge_slot_1_radio_spi_clk
 PORT radio_spi_data = fpga_0_radio_bridge_slot_1_radio_spi_data
 PORT radio_spi_cs = fpga_0_radio_bridge_slot_1_radio_spi_cs
 PORT radio_SHDN = fpga_0_radio_bridge_slot_1_radio_SHDN
 PORT radio_TxEn = fpga_0_radio_bridge_slot_1_radio_TxEn
 PORT radio_RxEn = fpga_0_radio_bridge_slot_1_radio_RxEn
 PORT radio_RxHP = fpga_0_radio_bridge_slot_1_radio_RxHP
 PORT radio_24PA = fpga_0_radio_bridge_slot_1_radio_24PA
 PORT radio_5PA = fpga_0_radio_bridge_slot_1_radio_5PA
 PORT radio_ANTSW = fpga_0_radio_bridge_slot_1_radio_ANTSW
 PORT radio_LED = fpga_0_radio_bridge_slot_1_radio_LED
 PORT radio_RX_ADC_DCS = fpga_0_radio_bridge_slot_1_radio_RX_ADC_DCS
 PORT radio_RX_ADC_DFS = fpga_0_radio_bridge_slot_1_radio_RX_ADC_DFS
 PORT radio_RX_ADC_PWDNA = fpga_0_radio_bridge_slot_1_radio_RX_ADC_PWDNA
 PORT radio_RX_ADC_PWDNB = fpga_0_radio_bridge_slot_1_radio_RX_ADC_PWDNB
 PORT radio_DIPSW = fpga_0_radio_bridge_slot_1_radio_DIPSW
 PORT radio_RSSI_ADC_clk = fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_clk
 PORT radio_RSSI_ADC_CLAMP = fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_CLAMP
 PORT radio_RSSI_ADC_HIZ = fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_HIZ
 PORT radio_RSSI_ADC_SLEEP = fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_SLEEP
 PORT radio_RSSI_ADC_D = fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D
 PORT radio_LD = fpga_0_radio_bridge_slot_1_radio_LD
 PORT radio_RX_ADC_OTRA = fpga_0_radio_bridge_slot_1_radio_RX_ADC_OTRA
 PORT radio_RX_ADC_OTRB = fpga_0_radio_bridge_slot_1_radio_RX_ADC_OTRB
 PORT radio_RSSI_ADC_OTR = fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_OTR
 PORT radio_dac_PLL_LOCK = fpga_0_radio_bridge_slot_1_radio_dac_PLL_LOCK
 PORT radio_dac_RESET = fpga_0_radio_bridge_slot_1_radio_dac_RESET
 PORT radio_EEPROM_IO = fpga_0_radio_bridge_slot_1_radio_EEPROM_IO
 PORT user_ADC_I = radio_bridge_slot_1_user_ADC_I
 PORT user_ADC_Q = radio_bridge_slot_1_user_ADC_Q
 PORT user_DAC_I = radio_bridge_slot_1_user_DAC_I
 PORT user_DAC_Q = radio_bridge_slot_1_user_DAC_Q
 PORT user_TxModelStart = radio1_txStart
 PORT user_RSSI_ADC_clk = rssi_pkt_detect_opbw_0_rssi_clk_out
 PORT user_RSSI_ADC_D = radio_bridge_slot_1_user_RSSI_ADC_D
 PORT user_RxRF_gain = agc_g_rf_a
 PORT user_RxBB_gain = agc_g_bb_a
 PORT user_RxHP_external = agc_rxhp_a
 PORT converter_clock_in = sys_clk_OPB
 PORT user_EEPROM_IO_T = eeprom_controller_DQ1_T_radio_bridge_slot_1_user_EEPROM_IO_T
 PORT user_EEPROM_IO_O = eeprom_controller_DQ1_O_radio_bridge_slot_1_user_EEPROM_IO_O
 PORT user_EEPROM_IO_I = eeprom_controller_DQ1_I_radio_bridge_slot_1_user_EEPROM_IO_I
END

BEGIN radio_bridge
 PARAMETER INSTANCE = radio_bridge_slot_2
 PARAMETER HW_VER = 1.08.a
 PORT converter_clock_out = fpga_0_radio_bridge_slot_2_converter_clock_out
 PORT radio_B = fpga_0_radio_bridge_slot_2_radio_B
 PORT radio_ADC_I = fpga_0_radio_bridge_slot_2_radio_ADC_I
 PORT radio_ADC_Q = fpga_0_radio_bridge_slot_2_radio_ADC_Q
 PORT radio_DAC_I = fpga_0_radio_bridge_slot_2_radio_DAC_I
 PORT radio_DAC_Q = fpga_0_radio_bridge_slot_2_radio_DAC_Q
 PORT controller_spi_clk = radio_bridge_slot_1_controller_spi_clk_radio_bridge_slot_2_controller_spi_clk_radio_bridge_slot_3_controller_spi_clk_radio_bridge_slot_4_controller_spi_clk_radio_controller_0_spi_clk
 PORT controller_spi_data = radio_bridge_slot_1_controller_spi_data_radio_bridge_slot_2_controller_spi_data_radio_bridge_slot_3_controller_spi_data_radio_bridge_slot_4_controller_spi_data_radio_controller_0_data_out
 PORT controller_radio_cs = radio_bridge_slot_2_controller_radio_cs_radio_controller_0_radio2_cs
 PORT controller_dac_cs = radio_bridge_slot_2_controller_dac_cs_radio_controller_0_dac2_cs
 PORT controller_SHDN = radio_bridge_slot_2_controller_SHDN_radio_controller_0_radio2_SHDN
 PORT controller_TxEn = radio_bridge_slot_2_controller_TxEn_radio_controller_0_radio2_TxEn
 PORT controller_RxEn = radio_bridge_slot_2_controller_RxEn_radio_controller_0_radio2_RxEn
 PORT controller_RxHP = radio_bridge_slot_2_controller_RxHP_radio_controller_0_radio2_RxHP
 PORT controller_24PA = radio_bridge_slot_2_controller_24PA_radio_controller_0_radio2_24PA
 PORT controller_5PA = radio_bridge_slot_2_controller_5PA_radio_controller_0_radio2_5PA
 PORT controller_ANTSW = radio_bridge_slot_2_controller_ANTSW_radio_controller_0_radio2_ANTSW
 PORT controller_LED = radio_bridge_slot_2_controller_LED_radio_controller_0_radio2_LED
 PORT controller_RX_ADC_DCS = radio_bridge_slot_2_controller_RX_ADC_DCS_radio_controller_0_radio2_ADC_RX_DCS
 PORT controller_RX_ADC_DFS = radio_bridge_slot_2_controller_RX_ADC_DFS_radio_controller_0_radio2_ADC_RX_DFS
 PORT controller_RX_ADC_PWDNA = radio_bridge_slot_2_controller_RX_ADC_PWDNA_radio_controller_0_radio2_ADC_RX_PWDNA
 PORT controller_RX_ADC_PWDNB = radio_bridge_slot_2_controller_RX_ADC_PWDNB_radio_controller_0_radio2_ADC_RX_PWDNB
 PORT controller_DIPSW = radio_bridge_slot_2_controller_DIPSW_radio_controller_0_radio2_DIPSW
 PORT controller_RSSI_ADC_CLAMP = radio_bridge_slot_2_controller_RSSI_ADC_CLAMP_radio_controller_0_radio2_RSSI_ADC_CLAMP
 PORT controller_RSSI_ADC_HIZ = radio_bridge_slot_2_controller_RSSI_ADC_HIZ_radio_controller_0_radio2_RSSI_ADC_HIZ
 PORT controller_RSSI_ADC_SLEEP = radio_bridge_slot_2_controller_RSSI_ADC_SLEEP_radio_controller_0_radio2_RSSI_ADC_SLEEP
 PORT controller_RSSI_ADC_D = radio_bridge_slot_2_controller_RSSI_ADC_D_radio_controller_0_radio2_RSSI_ADC_D
 PORT controller_LD = radio_bridge_slot_2_controller_LD_radio_controller_0_radio2_LD
 PORT controller_RX_ADC_OTRA = radio_bridge_slot_2_controller_RX_ADC_OTRA_radio_controller_0_radio2_ADC_RX_OTRA
 PORT controller_RX_ADC_OTRB = radio_bridge_slot_2_controller_RX_ADC_OTRB_radio_controller_0_radio2_ADC_RX_OTRB
 PORT controller_RSSI_ADC_OTR = radio_bridge_slot_2_controller_RSSI_ADC_OTR_radio_controller_0_radio2_RSSI_ADC_OTR
 PORT controller_dac_PLL_LOCK = radio_bridge_slot_2_controller_dac_PLL_LOCK_radio_controller_0_radio2_TX_DAC_PLL_LOCK
 PORT controller_dac_RESET = radio_bridge_slot_2_controller_dac_RESET_radio_controller_0_radio2_TX_DAC_RESET
 PORT user_Tx_gain = radio_bridge_slot_2_user_Tx_gain_radio_controller_0_radio2_TxGain
 PORT controller_TxStart = radio_bridge_slot_2_controller_TxStart_radio_controller_0_radio2_TxStart
 PORT controller_SHDN_external = radio_bridge_slot_2_controller_SHDN_external_radio_controller_0_radio2_SHDN_external
 PORT controller_RxEn_external = radio_bridge_slot_2_controller_RxEn_external_radio_controller_0_radio2_RxEn_external
 PORT controller_TxEn_external = radio_bridge_slot_2_controller_TxEn_external_radio_controller_0_radio2_TxEn_external
 PORT controller_RxHP_external = radio_bridge_slot_2_controller_RxHP_external_radio_controller_0_radio2_RxHP_external
 PORT dac_spi_data = fpga_0_radio_bridge_slot_2_dac_spi_data
 PORT dac_spi_cs = fpga_0_radio_bridge_slot_2_dac_spi_cs
 PORT dac_spi_clk = fpga_0_radio_bridge_slot_2_dac_spi_clk
 PORT radio_spi_clk = fpga_0_radio_bridge_slot_2_radio_spi_clk
 PORT radio_spi_data = fpga_0_radio_bridge_slot_2_radio_spi_data
 PORT radio_spi_cs = fpga_0_radio_bridge_slot_2_radio_spi_cs
 PORT radio_SHDN = fpga_0_radio_bridge_slot_2_radio_SHDN
 PORT radio_TxEn = fpga_0_radio_bridge_slot_2_radio_TxEn
 PORT radio_RxEn = fpga_0_radio_bridge_slot_2_radio_RxEn
 PORT radio_RxHP = fpga_0_radio_bridge_slot_2_radio_RxHP
 PORT radio_24PA = fpga_0_radio_bridge_slot_2_radio_24PA
 PORT radio_5PA = fpga_0_radio_bridge_slot_2_radio_5PA
 PORT radio_ANTSW = fpga_0_radio_bridge_slot_2_radio_ANTSW
 PORT radio_LED = fpga_0_radio_bridge_slot_2_radio_LED
 PORT radio_RX_ADC_DCS = fpga_0_radio_bridge_slot_2_radio_RX_ADC_DCS
 PORT radio_RX_ADC_DFS = fpga_0_radio_bridge_slot_2_radio_RX_ADC_DFS
 PORT radio_RX_ADC_PWDNA = fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNA
 PORT radio_RX_ADC_PWDNB = fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNB
 PORT radio_DIPSW = fpga_0_radio_bridge_slot_2_radio_DIPSW
 PORT radio_RSSI_ADC_clk = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_clk
 PORT radio_RSSI_ADC_CLAMP = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_CLAMP
 PORT radio_RSSI_ADC_HIZ = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_HIZ
 PORT radio_RSSI_ADC_SLEEP = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_SLEEP
 PORT radio_RSSI_ADC_D = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D
 PORT radio_LD = fpga_0_radio_bridge_slot_2_radio_LD
 PORT radio_RX_ADC_OTRA = fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRA
 PORT radio_RX_ADC_OTRB = fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRB
 PORT radio_RSSI_ADC_OTR = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_OTR
 PORT radio_dac_PLL_LOCK = fpga_0_radio_bridge_slot_2_radio_dac_PLL_LOCK
 PORT radio_dac_RESET = fpga_0_radio_bridge_slot_2_radio_dac_RESET
 PORT user_EEPROM_IO_T = eeprom_controller_DQ2_T_radio_bridge_slot_2_user_EEPROM_IO_T
 PORT user_EEPROM_IO_O = eeprom_controller_DQ2_O_radio_bridge_slot_2_user_EEPROM_IO_O
 PORT user_EEPROM_IO_I = eeprom_controller_DQ2_I_radio_bridge_slot_2_user_EEPROM_IO_I
 PORT radio_EEPROM_IO = fpga_0_radio_bridge_slot_2_radio_EEPROM_IO
 PORT user_ADC_I = radio_bridge_slot_2_user_ADC_I
 PORT user_ADC_Q = radio_bridge_slot_2_user_ADC_Q
 PORT user_DAC_I = radio_bridge_slot_2_user_DAC_I
 PORT user_DAC_Q = radio_bridge_slot_2_user_DAC_Q
 PORT user_TxModelStart = radio2_txStart
 PORT user_RSSI_ADC_clk = rssi_pkt_detect_opbw_0_rssi_clk_out
 PORT user_RSSI_ADC_D = radio_bridge_slot_2_user_RSSI_ADC_D
 PORT user_RxRF_gain = agc_g_rf_b
 PORT user_RxBB_gain = agc_g_bb_b
 PORT user_RxHP_external = agc_rxhp_b
 PORT converter_clock_in = sys_clk_OPB
END

BEGIN radio_bridge
 PARAMETER INSTANCE = radio_bridge_slot_3
 PARAMETER HW_VER = 1.08.a
 PORT converter_clock_out = fpga_0_radio_bridge_slot_3_converter_clock_out
 PORT radio_B = fpga_0_radio_bridge_slot_3_radio_B
 PORT radio_ADC_I = fpga_0_radio_bridge_slot_3_radio_ADC_I
 PORT radio_ADC_Q = fpga_0_radio_bridge_slot_3_radio_ADC_Q
 PORT radio_DAC_I = fpga_0_radio_bridge_slot_3_radio_DAC_I
 PORT radio_DAC_Q = fpga_0_radio_bridge_slot_3_radio_DAC_Q
 PORT controller_spi_clk = radio_bridge_slot_1_controller_spi_clk_radio_bridge_slot_2_controller_spi_clk_radio_bridge_slot_3_controller_spi_clk_radio_bridge_slot_4_controller_spi_clk_radio_controller_0_spi_clk
 PORT controller_spi_data = radio_bridge_slot_1_controller_spi_data_radio_bridge_slot_2_controller_spi_data_radio_bridge_slot_3_controller_spi_data_radio_bridge_slot_4_controller_spi_data_radio_controller_0_data_out
 PORT controller_radio_cs = radio_bridge_slot_3_controller_radio_cs_radio_controller_0_radio3_cs
 PORT controller_dac_cs = radio_bridge_slot_3_controller_dac_cs_radio_controller_0_dac3_cs
 PORT controller_SHDN = radio_bridge_slot_3_controller_SHDN_radio_controller_0_radio3_SHDN
 PORT controller_TxEn = radio_bridge_slot_3_controller_TxEn_radio_controller_0_radio3_TxEn
 PORT controller_RxEn = radio_bridge_slot_3_controller_RxEn_radio_controller_0_radio3_RxEn
 PORT controller_RxHP = radio_bridge_slot_3_controller_RxHP_radio_controller_0_radio3_RxHP
 PORT controller_24PA = radio_bridge_slot_3_controller_24PA_radio_controller_0_radio3_24PA
 PORT controller_5PA = radio_bridge_slot_3_controller_5PA_radio_controller_0_radio3_5PA
 PORT controller_ANTSW = radio_bridge_slot_3_controller_ANTSW_radio_controller_0_radio3_ANTSW
 PORT controller_LED = radio_bridge_slot_3_controller_LED_radio_controller_0_radio3_LED
 PORT controller_RX_ADC_DCS = radio_bridge_slot_3_controller_RX_ADC_DCS_radio_controller_0_radio3_ADC_RX_DCS
 PORT controller_RX_ADC_DFS = radio_bridge_slot_3_controller_RX_ADC_DFS_radio_controller_0_radio3_ADC_RX_DFS
 PORT controller_RX_ADC_PWDNA = radio_bridge_slot_3_controller_RX_ADC_PWDNA_radio_controller_0_radio3_ADC_RX_PWDNA
 PORT controller_RX_ADC_PWDNB = radio_bridge_slot_3_controller_RX_ADC_PWDNB_radio_controller_0_radio3_ADC_RX_PWDNB
 PORT controller_DIPSW = radio_bridge_slot_3_controller_DIPSW_radio_controller_0_radio3_DIPSW
 PORT controller_RSSI_ADC_CLAMP = radio_bridge_slot_3_controller_RSSI_ADC_CLAMP_radio_controller_0_radio3_RSSI_ADC_CLAMP
 PORT controller_RSSI_ADC_HIZ = radio_bridge_slot_3_controller_RSSI_ADC_HIZ_radio_controller_0_radio3_RSSI_ADC_HIZ
 PORT controller_RSSI_ADC_SLEEP = radio_bridge_slot_3_controller_RSSI_ADC_SLEEP_radio_controller_0_radio3_RSSI_ADC_SLEEP
 PORT controller_RSSI_ADC_D = radio_bridge_slot_3_controller_RSSI_ADC_D_radio_controller_0_radio3_RSSI_ADC_D
 PORT controller_LD = radio_bridge_slot_3_controller_LD_radio_controller_0_radio3_LD
 PORT controller_RX_ADC_OTRA = radio_bridge_slot_3_controller_RX_ADC_OTRA_radio_controller_0_radio3_ADC_RX_OTRA
 PORT controller_RX_ADC_OTRB = radio_bridge_slot_3_controller_RX_ADC_OTRB_radio_controller_0_radio3_ADC_RX_OTRB
 PORT controller_RSSI_ADC_OTR = radio_bridge_slot_3_controller_RSSI_ADC_OTR_radio_controller_0_radio3_RSSI_ADC_OTR
 PORT controller_dac_PLL_LOCK = radio_bridge_slot_3_controller_dac_PLL_LOCK_radio_controller_0_radio3_TX_DAC_PLL_LOCK
 PORT controller_dac_RESET = radio_bridge_slot_3_controller_dac_RESET_radio_controller_0_radio3_TX_DAC_RESET
 PORT user_Tx_gain = radio_bridge_slot_3_user_Tx_gain_radio_controller_0_radio3_TxGain
 PORT controller_TxStart = radio_bridge_slot_3_controller_TxStart_radio_controller_0_radio3_TxStart
 PORT controller_SHDN_external = radio_bridge_slot_3_controller_SHDN_external_radio_controller_0_radio3_SHDN_external
 PORT controller_RxEn_external = radio_bridge_slot_3_controller_RxEn_external_radio_controller_0_radio3_RxEn_external
 PORT controller_TxEn_external = radio_bridge_slot_3_controller_TxEn_external_radio_controller_0_radio3_TxEn_external
 PORT controller_RxHP_external = radio_bridge_slot_3_controller_RxHP_external_radio_controller_0_radio3_RxHP_external
 PORT dac_spi_data = fpga_0_radio_bridge_slot_3_dac_spi_data
 PORT dac_spi_cs = fpga_0_radio_bridge_slot_3_dac_spi_cs
 PORT dac_spi_clk = fpga_0_radio_bridge_slot_3_dac_spi_clk
 PORT radio_spi_clk = fpga_0_radio_bridge_slot_3_radio_spi_clk
 PORT radio_spi_data = fpga_0_radio_bridge_slot_3_radio_spi_data
 PORT radio_spi_cs = fpga_0_radio_bridge_slot_3_radio_spi_cs
 PORT radio_SHDN = fpga_0_radio_bridge_slot_3_radio_SHDN
 PORT radio_TxEn = fpga_0_radio_bridge_slot_3_radio_TxEn
 PORT radio_RxEn = fpga_0_radio_bridge_slot_3_radio_RxEn
 PORT radio_RxHP = fpga_0_radio_bridge_slot_3_radio_RxHP
 PORT radio_24PA = fpga_0_radio_bridge_slot_3_radio_24PA
 PORT radio_5PA = fpga_0_radio_bridge_slot_3_radio_5PA
 PORT radio_ANTSW = fpga_0_radio_bridge_slot_3_radio_ANTSW
 PORT radio_LED = fpga_0_radio_bridge_slot_3_radio_LED
 PORT radio_RX_ADC_DCS = fpga_0_radio_bridge_slot_3_radio_RX_ADC_DCS
 PORT radio_RX_ADC_DFS = fpga_0_radio_bridge_slot_3_radio_RX_ADC_DFS
 PORT radio_RX_ADC_PWDNA = fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNA
 PORT radio_RX_ADC_PWDNB = fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNB
 PORT radio_DIPSW = fpga_0_radio_bridge_slot_3_radio_DIPSW
 PORT radio_RSSI_ADC_clk = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_clk
 PORT radio_RSSI_ADC_CLAMP = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_CLAMP
 PORT radio_RSSI_ADC_HIZ = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_HIZ
 PORT radio_RSSI_ADC_SLEEP = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_SLEEP
 PORT radio_RSSI_ADC_D = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D
 PORT radio_LD = fpga_0_radio_bridge_slot_3_radio_LD
 PORT radio_RX_ADC_OTRA = fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRA
 PORT radio_RX_ADC_OTRB = fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRB
 PORT radio_RSSI_ADC_OTR = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_OTR
 PORT radio_dac_PLL_LOCK = fpga_0_radio_bridge_slot_3_radio_dac_PLL_LOCK
 PORT user_EEPROM_IO_T = eeprom_controller_DQ3_T_radio_bridge_slot_3_user_EEPROM_IO_T
 PORT user_EEPROM_IO_O = eeprom_controller_DQ3_O_radio_bridge_slot_3_user_EEPROM_IO_O
 PORT user_EEPROM_IO_I = eeprom_controller_DQ3_I_radio_bridge_slot_3_user_EEPROM_IO_I
 PORT radio_dac_RESET = fpga_0_radio_bridge_slot_3_radio_dac_RESET
 PORT radio_EEPROM_IO = fpga_0_radio_bridge_slot_3_radio_EEPROM_IO
 PORT user_ADC_I = radio_bridge_slot_3_user_ADC_I
 PORT user_ADC_Q = radio_bridge_slot_3_user_ADC_Q
 PORT user_DAC_I = radio_bridge_slot_3_user_DAC_I
 PORT user_DAC_Q = radio_bridge_slot_3_user_DAC_Q
 PORT user_TxModelStart = radio3_txStart
 PORT user_RSSI_ADC_clk = rssi_pkt_detect_opbw_0_rssi_clk_out
 PORT user_RSSI_ADC_D = radio_bridge_slot_3_user_RSSI_ADC_D
 PORT user_RxRF_gain = agc_g_rf_c
 PORT user_RxBB_gain = agc_g_bb_c
 PORT user_RxHP_external = agc_rxhp_c
 PORT converter_clock_in = sys_clk_OPB
END

BEGIN radio_bridge
 PARAMETER INSTANCE = radio_bridge_slot_4
 PARAMETER HW_VER = 1.08.a
 PORT converter_clock_out = fpga_0_radio_bridge_slot_4_converter_clock_out
 PORT radio_B = fpga_0_radio_bridge_slot_4_radio_B
 PORT radio_ADC_I = fpga_0_radio_bridge_slot_4_radio_ADC_I
 PORT radio_ADC_Q = fpga_0_radio_bridge_slot_4_radio_ADC_Q
 PORT radio_DAC_I = fpga_0_radio_bridge_slot_4_radio_DAC_I
 PORT radio_DAC_Q = fpga_0_radio_bridge_slot_4_radio_DAC_Q
 PORT controller_spi_clk = radio_bridge_slot_1_controller_spi_clk_radio_bridge_slot_2_controller_spi_clk_radio_bridge_slot_3_controller_spi_clk_radio_bridge_slot_4_controller_spi_clk_radio_controller_0_spi_clk
 PORT controller_spi_data = radio_bridge_slot_1_controller_spi_data_radio_bridge_slot_2_controller_spi_data_radio_bridge_slot_3_controller_spi_data_radio_bridge_slot_4_controller_spi_data_radio_controller_0_data_out
 PORT controller_radio_cs = radio_bridge_slot_4_controller_radio_cs_radio_controller_0_radio4_cs
 PORT controller_dac_cs = radio_bridge_slot_4_controller_dac_cs_radio_controller_0_dac4_cs
 PORT controller_SHDN = radio_bridge_slot_4_controller_SHDN_radio_controller_0_radio4_SHDN
 PORT controller_TxEn = radio_bridge_slot_4_controller_TxEn_radio_controller_0_radio4_TxEn
 PORT controller_RxEn = radio_bridge_slot_4_controller_RxEn_radio_controller_0_radio4_RxEn
 PORT controller_RxHP = radio_bridge_slot_4_controller_RxHP_radio_controller_0_radio4_RxHP
 PORT controller_24PA = radio_bridge_slot_4_controller_24PA_radio_controller_0_radio4_24PA
 PORT controller_5PA = radio_bridge_slot_4_controller_5PA_radio_controller_0_radio4_5PA
 PORT controller_ANTSW = radio_bridge_slot_4_controller_ANTSW_radio_controller_0_radio4_ANTSW
 PORT controller_LED = radio_bridge_slot_4_controller_LED_radio_controller_0_radio4_LED
 PORT controller_RX_ADC_DCS = radio_bridge_slot_4_controller_RX_ADC_DCS_radio_controller_0_radio4_ADC_RX_DCS
 PORT controller_RX_ADC_DFS = radio_bridge_slot_4_controller_RX_ADC_DFS_radio_controller_0_radio4_ADC_RX_DFS
 PORT controller_RX_ADC_PWDNA = radio_bridge_slot_4_controller_RX_ADC_PWDNA_radio_controller_0_radio4_ADC_RX_PWDNA
 PORT controller_RX_ADC_PWDNB = radio_bridge_slot_4_controller_RX_ADC_PWDNB_radio_controller_0_radio4_ADC_RX_PWDNB
 PORT controller_DIPSW = radio_bridge_slot_4_controller_DIPSW_radio_controller_0_radio4_DIPSW
 PORT controller_RSSI_ADC_CLAMP = radio_bridge_slot_4_controller_RSSI_ADC_CLAMP_radio_controller_0_radio4_RSSI_ADC_CLAMP
 PORT controller_RSSI_ADC_HIZ = radio_bridge_slot_4_controller_RSSI_ADC_HIZ_radio_controller_0_radio4_RSSI_ADC_HIZ
 PORT controller_RSSI_ADC_SLEEP = radio_bridge_slot_4_controller_RSSI_ADC_SLEEP_radio_controller_0_radio4_RSSI_ADC_SLEEP
 PORT controller_RSSI_ADC_D = radio_bridge_slot_4_controller_RSSI_ADC_D_radio_controller_0_radio4_RSSI_ADC_D
 PORT controller_LD = radio_bridge_slot_4_controller_LD_radio_controller_0_radio4_LD
 PORT controller_RX_ADC_OTRA = radio_bridge_slot_4_controller_RX_ADC_OTRA_radio_controller_0_radio4_ADC_RX_OTRA
 PORT controller_RX_ADC_OTRB = radio_bridge_slot_4_controller_RX_ADC_OTRB_radio_controller_0_radio4_ADC_RX_OTRB
 PORT controller_RSSI_ADC_OTR = radio_bridge_slot_4_controller_RSSI_ADC_OTR_radio_controller_0_radio4_RSSI_ADC_OTR
 PORT controller_dac_PLL_LOCK = radio_bridge_slot_4_controller_dac_PLL_LOCK_radio_controller_0_radio4_TX_DAC_PLL_LOCK
 PORT controller_dac_RESET = radio_bridge_slot_4_controller_dac_RESET_radio_controller_0_radio4_TX_DAC_RESET
 PORT user_Tx_gain = radio_bridge_slot_4_user_Tx_gain_radio_controller_0_radio4_TxGain
 PORT controller_TxStart = radio_bridge_slot_4_controller_TxStart_radio_controller_0_radio4_TxStart
 PORT controller_SHDN_external = radio_bridge_slot_4_controller_SHDN_external_radio_controller_0_radio4_SHDN_external
 PORT controller_RxEn_external = radio_bridge_slot_4_controller_RxEn_external_radio_controller_0_radio4_RxEn_external
 PORT controller_TxEn_external = radio_bridge_slot_4_controller_TxEn_external_radio_controller_0_radio4_TxEn_external
 PORT controller_RxHP_external = radio_bridge_slot_4_controller_RxHP_external_radio_controller_0_radio4_RxHP_external
 PORT dac_spi_data = fpga_0_radio_bridge_slot_4_dac_spi_data
 PORT dac_spi_cs = fpga_0_radio_bridge_slot_4_dac_spi_cs
 PORT dac_spi_clk = fpga_0_radio_bridge_slot_4_dac_spi_clk
 PORT radio_spi_clk = fpga_0_radio_bridge_slot_4_radio_spi_clk
 PORT radio_spi_data = fpga_0_radio_bridge_slot_4_radio_spi_data
 PORT radio_spi_cs = fpga_0_radio_bridge_slot_4_radio_spi_cs
 PORT radio_SHDN = fpga_0_radio_bridge_slot_4_radio_SHDN
 PORT radio_TxEn = fpga_0_radio_bridge_slot_4_radio_TxEn
 PORT radio_RxEn = fpga_0_radio_bridge_slot_4_radio_RxEn
 PORT radio_RxHP = fpga_0_radio_bridge_slot_4_radio_RxHP
 PORT radio_24PA = fpga_0_radio_bridge_slot_4_radio_24PA
 PORT radio_5PA = fpga_0_radio_bridge_slot_4_radio_5PA
 PORT radio_ANTSW = fpga_0_radio_bridge_slot_4_radio_ANTSW
 PORT radio_LED = fpga_0_radio_bridge_slot_4_radio_LED
 PORT radio_RX_ADC_DCS = fpga_0_radio_bridge_slot_4_radio_RX_ADC_DCS
 PORT radio_RX_ADC_DFS = fpga_0_radio_bridge_slot_4_radio_RX_ADC_DFS
 PORT radio_RX_ADC_PWDNA = fpga_0_radio_bridge_slot_4_radio_RX_ADC_PWDNA
 PORT radio_RX_ADC_PWDNB = fpga_0_radio_bridge_slot_4_radio_RX_ADC_PWDNB
 PORT radio_DIPSW = fpga_0_radio_bridge_slot_4_radio_DIPSW
 PORT radio_RSSI_ADC_clk = fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_clk
 PORT radio_RSSI_ADC_CLAMP = fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_CLAMP
 PORT radio_RSSI_ADC_HIZ = fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_HIZ
 PORT radio_RSSI_ADC_SLEEP = fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_SLEEP
 PORT radio_RSSI_ADC_D = fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D
 PORT radio_LD = fpga_0_radio_bridge_slot_4_radio_LD
 PORT radio_RX_ADC_OTRA = fpga_0_radio_bridge_slot_4_radio_RX_ADC_OTRA
 PORT radio_RX_ADC_OTRB = fpga_0_radio_bridge_slot_4_radio_RX_ADC_OTRB
 PORT radio_RSSI_ADC_OTR = fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_OTR
 PORT radio_dac_PLL_LOCK = fpga_0_radio_bridge_slot_4_radio_dac_PLL_LOCK
 PORT radio_dac_RESET = fpga_0_radio_bridge_slot_4_radio_dac_RESET
 PORT radio_EEPROM_IO = fpga_0_radio_bridge_slot_4_radio_EEPROM_IO
 PORT user_ADC_I = radio_bridge_slot_4_user_ADC_I
 PORT user_ADC_Q = radio_bridge_slot_4_user_ADC_Q
 PORT user_DAC_I = radio_bridge_slot_4_user_DAC_I
 PORT user_DAC_Q = radio_bridge_slot_4_user_DAC_Q
 PORT user_TxModelStart = radio4_txStart
 PORT user_RSSI_ADC_clk = rssi_pkt_detect_opbw_0_rssi_clk_out
 PORT user_RSSI_ADC_D = radio_bridge_slot_4_user_RSSI_ADC_D
 PORT user_RxRF_gain = agc_g_rf_d
 PORT user_RxBB_gain = agc_g_bb_d
 PORT user_RxHP_external = agc_rxhp_d
 PORT converter_clock_in = sys_clk_OPB
 PORT user_EEPROM_IO_T = eeprom_controller_DQ4_T_radio_bridge_slot_4_user_EEPROM_IO_T
 PORT user_EEPROM_IO_O = eeprom_controller_DQ4_O_radio_bridge_slot_4_user_EEPROM_IO_O
 PORT user_EEPROM_IO_I = eeprom_controller_DQ4_I_radio_bridge_slot_4_user_EEPROM_IO_I
END


BEGIN plb_emc
 PARAMETER INSTANCE = SRAM0_ZBT_512Kx32
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_PLB_CLK_PERIOD_PS = 12500
 PARAMETER C_NUM_BANKS_MEM = 1
 PARAMETER C_MAX_MEM_WIDTH = 32
 PARAMETER C_INCLUDE_NEGEDGE_IOREGS = 1
 PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1
 PARAMETER C_MEM0_WIDTH = 32
 PARAMETER C_SYNCH_MEM_0 = 1
 PARAMETER C_TCEDV_PS_MEM_0 = 0
 PARAMETER C_TWC_PS_MEM_0 = 0
 PARAMETER C_TAVDV_PS_MEM_0 = 0
 PARAMETER C_TWP_PS_MEM_0 = 0
 PARAMETER C_THZCE_PS_MEM_0 = 0
 PARAMETER C_TLZWE_PS_MEM_0 = 0
 PARAMETER C_MEM0_BASEADDR = 0x00600000
 PARAMETER C_MEM0_HIGHADDR = 0x007fffff
 BUS_INTERFACE SPLB = plb
 PORT Mem_A = fpga_0_SRAM0_ZBT_512Kx32_Mem_A_split
 PORT Mem_BEN = fpga_0_SRAM0_ZBT_512Kx32_Mem_BEN
 PORT Mem_WEN = fpga_0_SRAM0_ZBT_512Kx32_Mem_WEN
 PORT Mem_DQ = fpga_0_SRAM0_ZBT_512Kx32_Mem_DQ
 PORT Mem_OEN = fpga_0_SRAM0_ZBT_512Kx32_Mem_OEN
 PORT Mem_ADV_LDN = fpga_0_SRAM0_ZBT_512Kx32_Mem_ADV_LDN
 PORT Mem_CKEN = fpga_0_SRAM0_ZBT_512Kx32_Mem_CKEN
 PORT Mem_CE = fpga_0_SRAM0_ZBT_512Kx32_Mem_CE
END

BEGIN plb_emc
 PARAMETER INSTANCE = SRAM1_ZBT_512Kx32
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_PLB_CLK_PERIOD_PS = 12500
 PARAMETER C_NUM_BANKS_MEM = 1
 PARAMETER C_MAX_MEM_WIDTH = 32
 PARAMETER C_INCLUDE_NEGEDGE_IOREGS = 1
 PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1
 PARAMETER C_MEM0_WIDTH = 32
 PARAMETER C_SYNCH_MEM_0 = 1
 PARAMETER C_TCEDV_PS_MEM_0 = 0
 PARAMETER C_TWC_PS_MEM_0 = 0
 PARAMETER C_TAVDV_PS_MEM_0 = 0
 PARAMETER C_TWP_PS_MEM_0 = 0
 PARAMETER C_THZCE_PS_MEM_0 = 0
 PARAMETER C_TLZWE_PS_MEM_0 = 0
 PARAMETER C_MEM0_BASEADDR = 0x00000000
 PARAMETER C_MEM0_HIGHADDR = 0x001fffff
 BUS_INTERFACE SPLB = plb
 PORT Mem_A = fpga_0_SRAM1_ZBT_512Kx32_Mem_A_split
 PORT Mem_BEN = fpga_0_SRAM1_ZBT_512Kx32_Mem_BEN
 PORT Mem_WEN = fpga_0_SRAM1_ZBT_512Kx32_Mem_WEN
 PORT Mem_DQ = fpga_0_SRAM1_ZBT_512Kx32_Mem_DQ
 PORT Mem_OEN = fpga_0_SRAM1_ZBT_512Kx32_Mem_OEN
 PORT Mem_ADV_LDN = fpga_0_SRAM1_ZBT_512Kx32_Mem_ADV_LDN
 PORT Mem_CKEN = fpga_0_SRAM1_ZBT_512Kx32_Mem_CKEN
 PORT Mem_CE = fpga_0_SRAM1_ZBT_512Kx32_Mem_CE
END

BEGIN plb_bram_if_cntlr
 PARAMETER INSTANCE = plb_bram_if_cntlr_1
 PARAMETER HW_VER = 1.00.b
 PARAMETER c_plb_clk_period_ps = 12500
 PARAMETER c_baseaddr = 0x00400000
 PARAMETER c_highaddr = 0x0041ffff
 BUS_INTERFACE SPLB = plb
 BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_port
END

BEGIN bram_block
 PARAMETER INSTANCE = plb_bram_if_cntlr_1_bram
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_port
END

BEGIN opb_intc
 PARAMETER INSTANCE = opb_intc_0
 PARAMETER HW_VER = 1.00.c
 PARAMETER C_BASEADDR = 0x41200000
 PARAMETER C_HIGHADDR = 0x4120ffff
 BUS_INTERFACE SOPB = opb
 PORT OPB_Clk = sys_clk_OPB
 PORT Irq = EICC405EXTINPUTIRQ
 PORT Intr = Push_Buttons_4bit_IP2INTC_Irpt & rx_int_badpkt & Ethernet_MAC_IP2INTC_Irpt & tx_int_pktdone & rx_int_goodpkt & rx_int_goodheader & ofdm_timer_opbw_0_timerexpire
END

BEGIN util_bus_split
 PARAMETER INSTANCE = SRAM0_ZBT_512Kx32_util_bus_split_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_SIZE_IN = 32
 PARAMETER C_LEFT_POS = 11
 PARAMETER C_SPLIT = 30
 PORT Sig = fpga_0_SRAM0_ZBT_512Kx32_Mem_A_split
 PORT Out1 = fpga_0_SRAM0_ZBT_512Kx32_Mem_A
END

BEGIN util_bus_split
 PARAMETER INSTANCE = SRAM1_ZBT_512Kx32_util_bus_split_1
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_SIZE_IN = 32
 PARAMETER C_LEFT_POS = 11
 PARAMETER C_SPLIT = 30
 PORT Sig = fpga_0_SRAM1_ZBT_512Kx32_Mem_A_split
 PORT Out1 = fpga_0_SRAM1_ZBT_512Kx32_Mem_A
END

BEGIN dcm_module
 PARAMETER INSTANCE = dcm_0
 PARAMETER HW_VER = 1.00.c
 PARAMETER C_CLK0_BUF = TRUE
 PARAMETER C_CLK2X_BUF = TRUE
 PARAMETER C_CLKFX_BUF = TRUE
 PARAMETER C_CLKFX_DIVIDE = 1
 PARAMETER C_CLKFX_MULTIPLY = 4
 PARAMETER C_CLKIN_PERIOD = 25.000000
 PARAMETER C_CLK_FEEDBACK = 1X
 PARAMETER C_DFS_FREQUENCY_MODE = LOW
 PARAMETER C_DLL_FREQUENCY_MODE = LOW
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT CLKIN = dcm_clk_s
 PORT CLK2X = sys_clk_s
 PORT CLKFX = proc_clk_s
 PORT CLK0 = sys_clk_OPB
 PORT CLKFB = sys_clk_OPB
 PORT RST = clkBoardConfig_DCM_Reset
 PORT LOCKED = dcm_0_lock
END

BEGIN ofdm_timer_opbw
 PARAMETER INSTANCE = ofdm_timer_opbw_0
 PARAMETER C_BASEADDR = 0x77200000
 PARAMETER C_HIGHADDR = 0x7720ffff
 BUS_INTERFACE SOPB = opb
 PORT opb_clk = sys_clk_OPB
 PORT timerexpire = ofdm_timer_opbw_0_timerexpire
 PORT idlefordifs = ofdm_pktDetector_mimo_opbw_0_idlefordifs
END

BEGIN ofdm_pktdetector_mimo_opbw
 PARAMETER INSTANCE = ofdm_pktDetector_mimo_opbw_0
 PARAMETER C_BASEADDR = 0x71200000
 PARAMETER C_HIGHADDR = 0x7120ffff
 BUS_INTERFACE SOPB = opb
 PORT reset = rx_pktdetreset
 PORT rssi1 = radio_bridge_slot_1_user_RSSI_ADC_D
 PORT rssi2 = radio_bridge_slot_2_user_RSSI_ADC_D
 PORT rssi3 = radio_bridge_slot_3_user_RSSI_ADC_D
 PORT rssi4 = radio_bridge_slot_4_user_RSSI_ADC_D
 PORT pktdet = rssi_pkt_detect_opbw_0_rssi_pkt_det_out
 PORT rssi_clk_out = rssi_pkt_detect_opbw_0_rssi_clk_out
 PORT idlefordifs = ofdm_pktDetector_mimo_opbw_0_idlefordifs
 PORT opb_clk = sys_clk_OPB
 PORT debugbusy = ofdm_pktDetector_mimo_opbw_0_debugbusy
 PORT debugidledifs = ofdm_pktDetector_mimo_opbw_0_debugidledifs
END

BEGIN ofdm_txrx_mimo_opbw
 PARAMETER INSTANCE = ofdm_TxRx_mimo_opbw_0
 PARAMETER C_BASEADDR = 0x7DA00000
 PARAMETER C_HIGHADDR = 0x7DAFFFFF
 BUS_INTERFACE SOPB = opb
 BUS_INTERFACE PORTB = ofdm_TxRxPLB_BRAM_port
 PORT opb_clk = sys_clk_OPB
 PORT rx_anta_adci_dv4 = ofdmRx_antA_ADC_I
 PORT rx_anta_adcq_dv4 = ofdmRx_antA_ADC_Q
 PORT rx_anta_agc_done = agc_done_a
 PORT rx_anta_gainbb = agc_g_bb_a
 PORT rx_anta_gainrf = agc_g_rf_a
 PORT rx_antb_adci_dv4 = ofdmRx_antB_ADC_I
 PORT rx_antb_adcq_dv4 = ofdmRx_antB_ADC_Q
 PORT rx_antb_agc_done = agc_done_b
 PORT rx_antb_gainbb = agc_g_bb_b
 PORT rx_antb_gainrf = agc_g_rf_b
 PORT rx_antc_adci_dv4 = ofdmRx_antC_ADC_I
 PORT rx_antc_adcq_dv4 = ofdmRx_antC_ADC_Q
 PORT rx_antc_agc_done = agc_done_c
 PORT rx_antc_gainbb = agc_g_bb_c
 PORT rx_antc_gainrf = agc_g_rf_c
 PORT rx_antd_adci_dv4 = ofdmRx_antD_ADC_I
 PORT rx_antd_adcq_dv4 = ofdmRx_antD_ADC_Q
 PORT rx_antd_agc_done = agc_done_d
 PORT rx_antd_gainbb = agc_g_bb_d
 PORT rx_antd_gainrf = agc_g_rf_d
 PORT rx_extpktdet = rssi_pkt_detect_opbw_0_rssi_pkt_det_out
 PORT rx_reset = pcoreReset
 PORT tx_reset = pcoreReset
 PORT tx_starttransmit = txPHYStart
 PORT rx_int_badpkt = rx_int_badpkt
 PORT rx_int_goodpkt = rx_int_goodpkt
 PORT rx_int_goodheader = rx_int_goodheader
 PORT tx_int_pktdone = tx_int_pktdone
 PORT rx_pktdetreset = rx_pktdetreset
 PORT tx_anta_dac_i = radio_bridge_slot_1_user_DAC_I
 PORT tx_anta_dac_q = radio_bridge_slot_1_user_DAC_Q
 PORT tx_antb_dac_i = radio_bridge_slot_2_user_DAC_I
 PORT tx_antb_dac_q = radio_bridge_slot_2_user_DAC_Q
 PORT tx_antc_dac_i = radio_bridge_slot_3_user_DAC_I
 PORT tx_antc_dac_q = radio_bridge_slot_3_user_DAC_Q
 PORT tx_antd_dac_i = radio_bridge_slot_4_user_DAC_I
 PORT tx_antd_dac_q = radio_bridge_slot_4_user_DAC_Q
 PORT tx_debug_pktrunning = debug_tx_pktrunning
 PORT debug_chipscopetrig1 = debug_chipscopetrig
 PORT rx_debug_payload = debug_rx_payload
 PORT rx_debug_pktdone = debug_rx_pktdone
 PORT rx_debug_eq_i = ofdm_rx_debug_eq_i
 PORT rx_debug_eq_q = ofdm_rx_debug_eq_q
 PORT rx_debug_phasecorrect = rx_debug_phasecorrect
 PORT rx_debug_phaseerror = rx_debug_phaseerr
 PORT rx_debug_cfophasediff = rx_debug_cfophasediff
END

# PORT rx_debug_antsel = debug_antSel
BEGIN ofdm_agc_mimo_opbw
 PARAMETER INSTANCE = ofdm_AGC_mimo_opbw_0
 PARAMETER HW_VER = 1.03.a
 PARAMETER C_BASEADDR = 0x74020000
 PARAMETER C_HIGHADDR = 0x7402ffff
 BUS_INTERFACE SOPB = opb
 PORT opb_clk = sys_clk_OPB
 PORT i_in_a = radio_bridge_slot_1_user_ADC_I
 PORT q_in_a = radio_bridge_slot_1_user_ADC_Q
 PORT i_in_b = radio_bridge_slot_4_user_ADC_I
 PORT q_in_b = radio_bridge_slot_4_user_ADC_Q
 PORT i_out_a = ofdmRx_antA_ADC_I
 PORT q_out_a = ofdmRx_antA_ADC_Q
 PORT i_out_b = ofdmRx_antD_ADC_I
 PORT q_out_b = ofdmRx_antD_ADC_Q
 PORT packet_in = rssi_pkt_detect_opbw_0_rssi_pkt_det_out
 PORT rssi_in_a = radio_bridge_slot_1_user_RSSI_ADC_D
 PORT rssi_in_b = radio_bridge_slot_4_user_RSSI_ADC_D
 PORT rxhp_a = agc_rxhp_a
 PORT rxhp_b = agc_rxhp_d
 PORT g_bb_a = agc_g_bb_a
 PORT g_rf_a = agc_g_rf_a
 PORT g_bb_b = agc_g_bb_d
 PORT g_rf_b = agc_g_rf_d
 PORT reset_in = rx_pktdetreset
 PORT done_a = agc_done_a
 PORT done_b = agc_done_d
END

BEGIN ofdm_agc_mimo_opbw
 PARAMETER INSTANCE = ofdm_AGC_mimo_opbw_1
 PARAMETER HW_VER = 1.03.a
 PARAMETER C_BASEADDR = 0x74000000
 PARAMETER C_HIGHADDR = 0x7400ffff
 BUS_INTERFACE SOPB = opb
 PORT opb_clk = sys_clk_OPB
 PORT i_in_a = radio_bridge_slot_2_user_ADC_I
 PORT q_in_a = radio_bridge_slot_2_user_ADC_Q
 PORT i_in_b = radio_bridge_slot_3_user_ADC_I
 PORT q_in_b = radio_bridge_slot_3_user_ADC_Q
 PORT i_out_a = ofdmRx_antB_ADC_I
 PORT q_out_a = ofdmRx_antB_ADC_Q
 PORT i_out_b = ofdmRx_antC_ADC_I
 PORT q_out_b = ofdmRx_antC_ADC_Q
 PORT packet_in = rssi_pkt_detect_opbw_0_rssi_pkt_det_out
 PORT rssi_in_a = radio_bridge_slot_2_user_RSSI_ADC_D
 PORT rssi_in_b = radio_bridge_slot_3_user_RSSI_ADC_D
 PORT rxhp_a = agc_rxhp_b
 PORT rxhp_b = agc_rxhp_c
 PORT g_bb_a = agc_g_bb_b
 PORT g_rf_a = agc_g_rf_b
 PORT g_bb_b = agc_g_bb_c
 PORT g_rf_b = agc_g_rf_c
 PORT reset_in = rx_pktdetreset
 PORT done_a = agc_done_b
 PORT done_b = agc_done_c
END

BEGIN plb_bram_if_cntlr
 PARAMETER INSTANCE = plb_bram_if_cntlr_2
 PARAMETER HW_VER = 1.00.b
 PARAMETER c_plb_clk_period_ps = 10000
 PARAMETER c_include_burst_cacheln_support = 1
 PARAMETER c_baseaddr = 0x00300000
 PARAMETER c_highaddr = 0x00303fff
 BUS_INTERFACE SPLB = plb
 BUS_INTERFACE PORTA = plb_bram_if_cntlr_2_port
END

BEGIN bram_block
 PARAMETER INSTANCE = plb_bram_if_cntlr_2_bram
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = plb_bram_if_cntlr_2_port
 BUS_INTERFACE PORTB = ofdm_TxRxPLB_BRAM_port
 PORT BRAM_Clk_B = sys_clk_OPB
 PORT BRAM_EN_B = net_vcc
END

BEGIN opb_gpio
 PARAMETER INSTANCE = debugOutputs
 PARAMETER HW_VER = 3.01.b
 PARAMETER C_GPIO_WIDTH = 4
 PARAMETER C_IS_DUAL = 0
 PARAMETER C_IS_BIDIR = 0
 PARAMETER C_ALL_INPUTS = 0
 PARAMETER C_BASEADDR = 0x40040000
 PARAMETER C_HIGHADDR = 0x4004ffff
 BUS_INTERFACE SOPB = opb
 PORT OPB_Clk = sys_clk_OPB
 PORT GPIO_d_out = fpga_0_debug_GPIO_d_out
END

BEGIN util_reduced_logic
 PARAMETER INSTANCE = util_reduced_logic_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_OPERATION = or
 PARAMETER C_SIZE = 2
 #PORT Op1 = radio1_txStart & radio2_txStart & radio3_txStart & radio4_txStart
 PORT Op1 = radio1_txStart & radio2_txStart
 PORT Res = txPHYStart
END

# BEGIN user_io_board_controller_opbw
# PARAMETER INSTANCE = user_io_board_controller_opbw_0
# PARAMETER HW_VER = 1.00.a
# PARAMETER C_BASEADDR = 0x75400000
# PARAMETER C_HIGHADDR = 0x7547ffff
# BUS_INTERFACE SOPB = opb
# PORT OPB_Clk = sys_clk_OPB
# PORT reset = pcoreReset
# PORT cs = user_io_board_controller_opbw_0_cs
# PORT resetlcd = user_io_board_controller_opbw_0_resetlcd
# PORT scl = user_io_board_controller_opbw_0_scl
# PORT sdi = user_io_board_controller_opbw_0_sdi
# END

Amir · 2008-Nov-12 13:13:56

UPDATE: the problem doesn't seem to be from the radio controller. I changed the MHS file to swap radio controller port connections for radios 2 and 4 (without changing the radio bridge to AGC connections). The new bit-stream functioned as before, i.e. disabling the radio in daughtercard slot 4 (this time perceived as radio #2 by the radio controller) had no effect on its "I" channel at the input port of phy. Any suggestion on how to proceed debugging this issue?

Last edited by Amir (2008-Nov-12 13:15:04)

murphpo · 2008-Nov-12 16:12:08

Well, I don't see any obvious problems in the hardware connections. A few things worth trying:

-Double check the radio controller driver version in the MSS file. It needs to match the hardware version.

-Try the 4x4 WARPLab design from the repository. There is a bitsteam ready for download, plus a handful of m-code examples which exercise each path in the 4x4 setup. This would at least rule out the boards, clock cables, antennas, etc. in your setup.

Amir · 2008-Nov-13 10:55:02

- The radio controller version in the MSS matches the HW version.

- Instead of trying the WARPLAB, here's what I did. I created a new project with additional chipscope signals to directly probe the output of the radio bridges before going into the two AGC cores. The results indicate that the output of radio bridges are fine in all cases, i.e. the "I" channel output of any radio becomes negligible (with a DC offset since this is the pre-AGC signal) if and only if that radio is disabled. However, after the same negligible signal goes through the AGC the problem occurs (in cases mentioned in post #7).

Here are the chipscope captures with

- all 4 radios enabled:

http://www.fileshost.com/en/file/70125/debug-xls.html

- radio 3 TXRXdisabled:

http://www.fileshost.com/en/file/70126/ … d-xls.html

RadioX_I and AntX_ADC_I are the pre- and post-AGC "I" channels of radio #X respectively. Radios 1 & 4 are connected to AGC0 and radios 2 & 3 to AGC1.

As you can see in the second data set, with radio 3 disabled, the "I" channel of both radios 3 and 4 become negligible. However, the "Q" channel of radio 4 remains ok. I have repeated the tests with different cables, clock board, etc. (which seems irrelevant at this point since the radio bridge outputs seem ok).

Any idea on what may cause this behavior? Has anybody else ever tried instantiating two AGCs on this board? How hard would it be to extend the AGC core to support 4 antennas so we can have a single AGC core?

Thanks.

Last edited by Amir (2008-Nov-13 10:57:26)

murphpo · 2008-Nov-14 10:49:20

You're the first to instantiate two AGC cores in one design, and your results pretty clearly show the AGC core is screwing things up. Let me look through the guts of the core again this weekend.

One thing that would help- can you post the C code you're using to initialize the two AGC cores? The values you write to their control registers will be useful in figuring out what's happening.

Amir · 2008-Nov-14 12:44:26

Here is our dirty extension of the AGC driver, simply initializing and operating both AGCs simultaneously.

Code:

#include "ofdm_AGC_mimo.h"
#include "xparameters.h"

void ofdm_AGC_SetDCO(unsigned int AGCstate){

	// Enables DCO and DCO subtraction (correction scheme and butterworth hipass are active)

	unsigned int bits0, bits1;

	bits0 = *((volatile unsigned int *)(XPAR_OFDM_AGC_MIMO_OPBW_0_BASEADDR+OFDM_AGC_MIMO_Bits_OFFSET));
	bits1 = *((volatile unsigned int *)(XPAR_OFDM_AGC_MIMO_OPBW_1_BASEADDR+OFDM_AGC_MIMO_Bits_OFFSET));

	if(AGCstate) {
		bits0 = bits0 | 0x6;
		bits1 = bits1 | 0x6;
	}
	else {
		bits0 = bits0 & 0x1;
		bits1 = bits1 & 0x1;
	}
		

	*((volatile unsigned int *)(XPAR_OFDM_AGC_MIMO_OPBW_0_BASEADDR+OFDM_AGC_MIMO_Bits_OFFSET) ) = bits0;
	*((volatile unsigned int *)(XPAR_OFDM_AGC_MIMO_OPBW_1_BASEADDR+OFDM_AGC_MIMO_Bits_OFFSET) ) = bits1;

	xil_printf("AGC BITSIN0 = %x\r\n",*((volatile unsigned int *)(XPAR_OFDM_AGC_MIMO_OPBW_0_BASEADDR+OFDM_AGC_MIMO_Bits_OFFSET) ));
	xil_printf("AGC BITSIN1 = %x\r\n",*((volatile unsigned int *)(XPAR_OFDM_AGC_MIMO_OPBW_1_BASEADDR+OFDM_AGC_MIMO_Bits_OFFSET) ));
}

void ofdm_AGC_FiltSel(unsigned int AGCstate){

	// Sets the downsampler AGCstate (0 is DS, 1 is filtered)

	unsigned int bits0, bits1;
	bits0 = *((volatile unsigned int *)(XPAR_OFDM_AGC_MIMO_OPBW_0_BASEADDR+OFDM_AGC_MIMO_Bits_OFFSET));
	bits1 = *((volatile unsigned int *)(XPAR_OFDM_AGC_MIMO_OPBW_1_BASEADDR+OFDM_AGC_MIMO_Bits_OFFSET));

	if(AGCstate) {
		bits0 = bits0 | 0x1;
		bits1 = bits1 | 0x1;
	}
	else {
		bits0 = bits0 & 0x6;
		bits1 = bits1 & 0x6;
	}

	*((volatile unsigned int *)(XPAR_OFDM_AGC_MIMO_OPBW_0_BASEADDR+OFDM_AGC_MIMO_Bits_OFFSET)) = bits0;
	*((volatile unsigned int *)(XPAR_OFDM_AGC_MIMO_OPBW_1_BASEADDR+OFDM_AGC_MIMO_Bits_OFFSET)) = bits1;

}

void ofdm_AGC_Reset(){

	// Cycle the agc's software reset port

	*((volatile unsigned int *)(XPAR_OFDM_AGC_MIMO_OPBW_0_BASEADDR+OFDM_AGC_MIMO_SRESET_IN_OFFSET) ) =1;
	*((volatile unsigned int *)(XPAR_OFDM_AGC_MIMO_OPBW_1_BASEADDR+OFDM_AGC_MIMO_SRESET_IN_OFFSET) ) =1;
	usleep(10);
	*((volatile unsigned int *)(XPAR_OFDM_AGC_MIMO_OPBW_0_BASEADDR+OFDM_AGC_MIMO_SRESET_IN_OFFSET) ) =0;
	*((volatile unsigned int *)(XPAR_OFDM_AGC_MIMO_OPBW_1_BASEADDR+OFDM_AGC_MIMO_SRESET_IN_OFFSET) ) =0;
	usleep(100);

}


void ofdm_AGC_MasterReset(){

	// Cycle the master reset register in the AGC and enable it

	*((volatile unsigned int *)(XPAR_OFDM_AGC_MIMO_OPBW_0_BASEADDR+OFDM_AGC_MIMO_AGC_EN_OFFSET)) = 0;
	*((volatile unsigned int *)(XPAR_OFDM_AGC_MIMO_OPBW_1_BASEADDR+OFDM_AGC_MIMO_AGC_EN_OFFSET)) = 0;
	usleep(10);

	*((volatile unsigned int *)(XPAR_OFDM_AGC_MIMO_OPBW_0_BASEADDR+OFDM_AGC_MIMO_MRESET_IN_OFFSET)) = 0;
	*((volatile unsigned int *)(XPAR_OFDM_AGC_MIMO_OPBW_1_BASEADDR+OFDM_AGC_MIMO_MRESET_IN_OFFSET)) = 0;
	usleep(10);
	*((volatile unsigned int *)(XPAR_OFDM_AGC_MIMO_OPBW_0_BASEADDR+OFDM_AGC_MIMO_MRESET_IN_OFFSET)) = 1;
	*((volatile unsigned int *)(XPAR_OFDM_AGC_MIMO_OPBW_1_BASEADDR+OFDM_AGC_MIMO_MRESET_IN_OFFSET)) = 1;
	usleep(10);
	*((volatile unsigned int *)(XPAR_OFDM_AGC_MIMO_OPBW_0_BASEADDR+OFDM_AGC_MIMO_MRESET_IN_OFFSET)) = 0;
	*((volatile unsigned int *)(XPAR_OFDM_AGC_MIMO_OPBW_1_BASEADDR+OFDM_AGC_MIMO_MRESET_IN_OFFSET)) = 0;
	usleep(10);

	*((volatile unsigned int *)(XPAR_OFDM_AGC_MIMO_OPBW_0_BASEADDR+OFDM_AGC_MIMO_AGC_EN_OFFSET)) = 1;
	*((volatile unsigned int *)(XPAR_OFDM_AGC_MIMO_OPBW_1_BASEADDR+OFDM_AGC_MIMO_AGC_EN_OFFSET)) = 1;

}

void ofdm_AGC_Initialize(int noise_estimate){

	int g_bbset = 0;

	// First set all standard parameters

	// Turn off both resets and the master enable
	*((volatile unsigned int *)(XPAR_OFDM_AGC_MIMO_OPBW_0_BASEADDR+OFDM_AGC_MIMO_AGC_EN_OFFSET)) = 0;
	*((volatile unsigned int *)(XPAR_OFDM_AGC_MIMO_OPBW_0_BASEADDR+OFDM_AGC_MIMO_SRESET_IN_OFFSET) ) = 0;
	*((volatile unsigned int *)(XPAR_OFDM_AGC_MIMO_OPBW_0_BASEADDR+OFDM_AGC_MIMO_MRESET_IN_OFFSET)) = 0;
	
	*((volatile unsigned int *)(XPAR_OFDM_AGC_MIMO_OPBW_1_BASEADDR+OFDM_AGC_MIMO_AGC_EN_OFFSET)) = 0;
	*((volatile unsigned int *)(XPAR_OFDM_AGC_MIMO_OPBW_1_BASEADDR+OFDM_AGC_MIMO_SRESET_IN_OFFSET) ) = 0;
	*((volatile unsigned int *)(XPAR_OFDM_AGC_MIMO_OPBW_1_BASEADDR+OFDM_AGC_MIMO_MRESET_IN_OFFSET)) = 0;


	// An adjustment parameter
	*((volatile signed int *)(XPAR_OFDM_AGC_MIMO_OPBW_0_BASEADDR+OFDM_AGC_MIMO_ADJ_OFFSET)) = 8;
	*((volatile signed int *)(XPAR_OFDM_AGC_MIMO_OPBW_1_BASEADDR+OFDM_AGC_MIMO_ADJ_OFFSET)) = 8;

	// Timing for the DC-offset correction
	*((volatile unsigned int *)(XPAR_OFDM_AGC_MIMO_OPBW_0_BASEADDR+OFDM_AGC_MIMO_DCO_Timing_OFFSET)) = 0x46403003;
	*((volatile unsigned int *)(XPAR_OFDM_AGC_MIMO_OPBW_1_BASEADDR+OFDM_AGC_MIMO_DCO_Timing_OFFSET)) = 0x46403003;

	// Initial baseband gain setting
	*((volatile unsigned int *)(XPAR_OFDM_AGC_MIMO_OPBW_0_BASEADDR+OFDM_AGC_MIMO_GBB_init_OFFSET)) = 52;
	*((volatile unsigned int *)(XPAR_OFDM_AGC_MIMO_OPBW_1_BASEADDR+OFDM_AGC_MIMO_GBB_init_OFFSET)) = 52;

	// RF gain AGCstate thresholds
	*((volatile unsigned int *)(XPAR_OFDM_AGC_MIMO_OPBW_0_BASEADDR+OFDM_AGC_MIMO_Thresholds_OFFSET)) = 0xD5CBA6;//0xE0D3A6;
	*((volatile unsigned int *)(XPAR_OFDM_AGC_MIMO_OPBW_1_BASEADDR+OFDM_AGC_MIMO_Thresholds_OFFSET)) = 0xD5CBA6;//0xE0D3A6;

	// Overall AGC timing
	*((volatile unsigned int *)(XPAR_OFDM_AGC_MIMO_OPBW_0_BASEADDR+OFDM_AGC_MIMO_Timing_OFFSET)) = 0x9A962A28;//0x826E3C0A;
	*((volatile unsigned int *)(XPAR_OFDM_AGC_MIMO_OPBW_1_BASEADDR+OFDM_AGC_MIMO_Timing_OFFSET)) = 0x9A962A28;//0x826E3C0A;

	// vIQ and RSSI average lengths
	*((volatile unsigned int *)(XPAR_OFDM_AGC_MIMO_OPBW_0_BASEADDR+OFDM_AGC_MIMO_AVG_LEN_OFFSET)) = 0x10F; //103
	*((volatile unsigned int *)(XPAR_OFDM_AGC_MIMO_OPBW_1_BASEADDR+OFDM_AGC_MIMO_AVG_LEN_OFFSET)) = 0x10F; //103

	// Disable DCO, disable DCO subtraction, set filter to straight downsampling
	*((volatile unsigned int *)(XPAR_OFDM_AGC_MIMO_OPBW_0_BASEADDR+OFDM_AGC_MIMO_Bits_OFFSET) ) = 0x0;
	*((volatile unsigned int *)(XPAR_OFDM_AGC_MIMO_OPBW_1_BASEADDR+OFDM_AGC_MIMO_Bits_OFFSET) ) = 0x0;

	// Compute and set the initial g_BB gain value from the noise estimate
	// The initial g_bb sets noise to -19 db, assuming 32 db RF gain

	g_bbset = -19 - 32 - noise_estimate;
	*((volatile unsigned int *)(XPAR_OFDM_AGC_MIMO_OPBW_0_BASEADDR+OFDM_AGC_MIMO_GBB_init_OFFSET)) = g_bbset;
	*((volatile unsigned int *)(XPAR_OFDM_AGC_MIMO_OPBW_1_BASEADDR+OFDM_AGC_MIMO_GBB_init_OFFSET)) = g_bbset;


	// Perform a master reset
	ofdm_AGC_MasterReset();

	// Agc is now reset and enabled, ready to go!
}


void ofdm_AGC_setNoiseEstimate(int noise_estimate){
	int g_bbset;
	g_bbset = -19 - 32 - noise_estimate;
	*((volatile unsigned int *)(XPAR_OFDM_AGC_MIMO_OPBW_0_BASEADDR+OFDM_AGC_MIMO_GBB_init_OFFSET)) = g_bbset;
	xil_printf("-19 - 32 - noise_estimate (AGC0) = %d\r\n",*((volatile unsigned int *)(XPAR_OFDM_AGC_MIMO_OPBW_0_BASEADDR+OFDM_AGC_MIMO_GBB_init_OFFSET)));
	
	*((volatile unsigned int *)(XPAR_OFDM_AGC_MIMO_OPBW_1_BASEADDR+OFDM_AGC_MIMO_GBB_init_OFFSET)) = g_bbset;
	xil_printf("-19 - 32 - noise_estimate (AGC1)= %d\r\n",*((volatile unsigned int *)(XPAR_OFDM_AGC_MIMO_OPBW_1_BASEADDR+OFDM_AGC_MIMO_GBB_init_OFFSET)));

}

unsigned int ofdm_AGC_GetGains(void){

	// Returns hi[0 gBB_B g_RF_B | 0 g_BB_A g_RF_A]lo

	unsigned int gBB_A0, gRF_A0, gBB_B0, gRF_B0, gains0;
	unsigned int gBB_A1, gRF_A1, gBB_B1, gRF_B1, gains1;

	// Get the gains from the registers

	gBB_A0 = *((volatile unsigned int *)(XPAR_OFDM_AGC_MIMO_OPBW_0_BASEADDR+OFDM_AGC_MIMO_GBB_A_OFFSET));
	gRF_A0 = *((volatile unsigned int *)(XPAR_OFDM_AGC_MIMO_OPBW_0_BASEADDR+OFDM_AGC_MIMO_GRF_A_OFFSET));
	
	gBB_A1 = *((volatile unsigned int *)(XPAR_OFDM_AGC_MIMO_OPBW_1_BASEADDR+OFDM_AGC_MIMO_GBB_A_OFFSET));
	gRF_A1 = *((volatile unsigned int *)(XPAR_OFDM_AGC_MIMO_OPBW_1_BASEADDR+OFDM_AGC_MIMO_GRF_A_OFFSET));


	gBB_B0 = *((volatile unsigned int *)(XPAR_OFDM_AGC_MIMO_OPBW_0_BASEADDR+OFDM_AGC_MIMO_GBB_B_OFFSET));
	gRF_B0 = *((volatile unsigned int *)(XPAR_OFDM_AGC_MIMO_OPBW_0_BASEADDR+OFDM_AGC_MIMO_GRF_B_OFFSET));
	
	gBB_B1 = *((volatile unsigned int *)(XPAR_OFDM_AGC_MIMO_OPBW_1_BASEADDR+OFDM_AGC_MIMO_GBB_B_OFFSET));
	gRF_B1 = *((volatile unsigned int *)(XPAR_OFDM_AGC_MIMO_OPBW_1_BASEADDR+OFDM_AGC_MIMO_GRF_B_OFFSET));

	// Concatenate into one return register

	// First concatenate the two radios together, into the gRF register
	// 2 lowest bits are RF, 5 higher bits are BB, last bit is unused

	// Multiply by 2^2, shift gBB right by 2 bits

	gRF_A0 = gRF_A0 + (gBB_A0 * 4);
	gRF_B0 = gRF_B0 + (gBB_B0 * 4);
	
	gRF_A1 = gRF_A1 + (gBB_A1 * 4);
	gRF_B1 = gRF_B1 + (gBB_B1 * 4);

	// Multiply by 2^8 shift gRF right by 8 bits

	gains0 = gRF_A0 + (gRF_B0 * 256);
	gains1 = gRF_A1 + (gRF_B1 * 256);

	return gains0;


}

void ofdm_AGC_SetTarget(unsigned int target){
	*((volatile unsigned int*) (XPAR_OFDM_AGC_MIMO_OPBW_0_BASEADDR+OFDM_AGC_MIMO_T_dB_OFFSET)) = target;
	*((volatile unsigned int*) (XPAR_OFDM_AGC_MIMO_OPBW_1_BASEADDR+OFDM_AGC_MIMO_T_dB_OFFSET)) = target;
	return;
}

Amir · 2008-Nov-19 11:29:41

Any updates on this issue?

I did further debugging by modifying the AGC driver to disable the DCO subtraction (bits | 0x2). All the pre- and post-AGC values were identical (i.e. no DC change) except for the "I" channel of Radio4 which showed some DC variation after the AGC and the signal's shape also changed. The "Q" channel remained same as the radio bridge output.

In another test, I fully disabled the DCO correction of both AGCs in warpphy.c. In this case radio4_I showed no DC variation before and after the AGC. However, its post-AGC values were still a bit far from the pre-AGC ones.

Any feedback is appreciated.

Last edited by Amir (2008-Nov-19 11:31:19)

murphpo · 2008-Nov-20 10:17:10

The I/Q paths through the AGC are processed in two places. The first is a decimation step, to downsample the 40MS/s from bridge to 10Ms/s for the PHY. This decimation uses either simple downsampling or a decimation filter. We usually run the system without the filter, trusting the radio's LPF to prevent aliasing. This choice is controlled by the LSB of 'bits':
(bits | 0x1) => use the filter
(bits & ~0x1) => simple downsampling

The second block is DC offset correction. This block estimates risidual DCO in the I/Q paths, subtracts it from the I/Q streams, then runs the I/Q streams through an IIR HPF to remove slowly varying DC offsets over the length of a packet. The filter is enabled only after the estimation/subtraction is applied. The DCO block is configured by two bits in the 'bits' register.
(bits & ~0x2) => Bypass DCO correction and HPF
((bits | 0x2) & ~0x4) => Bypass DCO subtraction; enable just HPF
(bits | 0x6) => enable DCO correction and HPF

If you disable both the decimation filter and DCO correction, the I/Q outputs should match the inputs exactly. Is this what you observe?

Amir · 2008-Nov-20 10:29:10

Yes, as I mentioned in the previous post, by fully disabling both AGCs using AGC_SetDCO(0), all the inputs and outputs were almost identical. Disabling only the DCO subtraction resulted in DC offset change in radio4_I only.

Last edited by Amir (2008-Nov-20 10:29:32)

murphpo · 2008-Nov-20 11:07:01

Calling AGC_SetDCO(0) won't disable the gain-control blocks, but will bypass any I/Q processing in the AGC core. In this mode, the I/Q inputs and outputs of the AGC core should be identical bit-for-bit. Are you seeing differences (even small ones) in this mode?

Amir · 2008-Nov-20 17:09:48

Yes, in that mode, radio 4's pre- and post-AGC "I" channel were not identical.

EDIT: I finally got it working by rebuilding the project from a different folder. As far as I can see, the new project is identical to the old one in terms of all dthe esign files and parameters (except a few chipscope debug signal within the ofdm core). Also both projects were created on the same machine. In either case, the AGC outputs of the new project look ok on all four radios. I guess the problem was due to a peculiarity of the XPS flow. As another example, the first bitstream generated from the new project was getting stuck at radio EEPROM initialization stage. Clearing the HW and regenerating the bitstream, without any other changes, solved that issue.

On a different note, I'm having issues downloading the new bitstream using JTAG. With everything else remaining fixed (including HW setup, environment, etc.), consecutive downloads of the same bitstream to the receiver board behave very differently, i.e., one gives a very clean equalized signal while the other one is badly distorted. Redownloading the bitstream multiple times seems to fix this. I haven't tried this one on the compact flash yet but have you seen a similar behavior?

WARP Project Forums - Wireless Open-Access Research Platform

#1 2008-Nov-06 12:07:11

AGC question

Code:

#2 2008-Nov-06 15:10:07

Re: AGC question

#3 2008-Nov-10 09:05:22

Re: AGC question

#4 2008-Nov-10 10:57:43

Re: AGC question

#5 2008-Nov-11 12:43:50

Re: AGC question

#6 2008-Nov-11 13:44:57

Re: AGC question

#7 2008-Nov-11 15:34:39

Re: AGC question

#8 2008-Nov-11 16:24:02

Re: AGC question

#9 2008-Nov-12 07:59:51

Re: AGC question

Code:

#10 2008-Nov-12 08:02:08

Re: AGC question

Code:

#11 2008-Nov-12 13:13:56

Re: AGC question

#12 2008-Nov-12 16:12:08

Re: AGC question

#13 2008-Nov-13 10:55:02

Re: AGC question

#14 2008-Nov-14 10:49:20

Re: AGC question

#15 2008-Nov-14 12:44:26

Re: AGC question

Code:

#16 2008-Nov-19 11:29:41

Re: AGC question

#17 2008-Nov-20 10:17:10

Re: AGC question

#18 2008-Nov-20 10:29:10

Re: AGC question

#19 2008-Nov-20 11:07:01

Re: AGC question

#20 2008-Nov-20 17:09:48

Re: AGC question

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