WARP Project Forums - Wireless Open-Access Research Platform

The Rx packet buffer contains all payload bits decoded by the PHY. The DSSS Rx PHY does not write the SYNC or SFD fields to the packet buffer (see here for good guide to the 802.11 DSSS frame format).  You can access the decoded bytes by reading the Rx packet buffer anywhere in the C code.

Each Rx packet buffer starts with the rx_frame_info_t struct (metadata about the packet), then the PHY header (SIGNAL, SERVICE), then the MAC header+payload. See wlan_mac_pkt_buf_util.h for more details.

To access the Rx packet buffer contents from C:

u8* pkt_buf_addr;
u8* phy_header;
mac_header_80211* mac_header;

% Retrieve memory address for Rx packet buffer index rx_pkt_buf
pkt_buf_addr = (u8*)CALC_PKT_BUF_ADDR(platform_common_dev_info.rx_pkt_buf_baseaddr, rx_pkt_buf);

% Compute memory address for PHY header in current Rx packet buffer
phy_header = (u8*)(pkt_buf_addr + PHY_RX_PKT_BUF_PHY_HDR_OFFSET);

% Compute memory address for MAC header in current Rx packet buffer
mac_header = (mac_header_80211*)((u8*)(pkt_buf_addr + PHY_RX_PKT_BUF_MPDU_OFFSET));

From those pointers you can read specific byte offsets with your choice of C (Xil_In8(ptr+N), phy_header[N], etc).

Right, the DSSS Rx pipeline will reset if the SFD is not detected following the SYNC field.

The DSSS Rx pipeline only writes decoded header/payload bytes to the packet buffer. The PHY preamble (SYNC, SFD) is processed by the PHY but not recorded anywhere. Monitoring the raw output of the descrambler would require modifying the Rx PHY model in System Generator/Simulink.

One option would be to add the descrambler output as another input to the ChipScope core, then use ChipScope Analyzer to extract the data. However this approach will not capture the bits for every packet (ChipScope uses JTAG to communicate with the hardware, so it's much too slow to offload data for every packet). Alternatively you could modify the DSSS Rx PHY control logic to write all descrambled bits to the packet buffer, or to another shared memory area (like a System Generator Shared Memory block). Any of these changes will require re-exporting the Rx PHY model from Sysgen, updating the XPS design then re-building the 802.11 hardware project in XPS.

Please answer some Xilinx License questions to complete PHY modification. Above mentions Sysgen and XPS rebuild

Recommended Tools for WARP v3:
"Xilinx ISE Design Suite: 14.4 System Edition"
Complete installation of ISE System Edition?

Xilinx wrote:

Unfortunately, Xilinx no longer offers our ISE tools for purchase.  However, we do provide ISE with any purchase of Vivado.  There are two Vivado suites available; "Design" and "System".  (Your license will entitle the last release version of ISE and any version prior. (To version 11.1)

The Design edition enables the ISE Embedded Edition while the Vivado System purchase enables the ISE system edition so please check the ISE support matrix at https://www.xilinx.com/products/design- … suite.html to make sure you purchase the correct Vivado to enable the features you need.

There are 2 possible licenses needs. Will I need both?
option 1: Vivado System allows ISE systems: Sysgen for Simulink Models
option 2: Vivado Design allows Xilinx Platform Studio (XPS)

Thanks for your help.