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#1 2017-Oct-18 09:35:37

DHR
Member
Registered: 2016-Jun-01
Posts: 4

Analogic control signal

Hello, we are students and we are just starting with Warp V3. We need to generate a control signal after processing the RF signal. The control signal must be analogic, but a digital word is also useful.

The only option we imagine is to use the debug header. We actually are using WARPlab 7.3

What is the best option to do this?

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#2 2017-Oct-18 10:10:28

murphpo
Administrator
From: Mango Communications
Registered: 2006-Jul-03
Posts: 5159

Re: Analogic control signal

You could use the debug header to drive (up to) 16 bits to an external circuit. You would need to modify the WARPLab Reference Design hardware project for this - the reference project uses the debug header for trigger and debug I/O (refer to the user guide). Keep in mind the debug header pins are connected directly to 2.5v FPGA I/O pins. You must use external level shifting if you need to connect to other voltages (3.3v, 5v, etc).

In order to drive an analog control signal you will need an external DAC of some sort. The choice of DAC depends on the analog requirements - accuracy, voltage range, update rate, etc. A few options:
- Build a simple "DAC" with a resistor ladder connected to the debug header
- Use a DAC connected to the debug header pins; you could build this on a breadboard, for example. Take care to honor the 2.5v voltage requirement of the debug pins
- Use a DAC FMC module; our FMC-BB-4DA is one option, there are many other options with different analog specs (Xilinx's list is a good starting point)

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#3 2017-Oct-25 13:19:11

DHR
Member
Registered: 2016-Jun-01
Posts: 4

Re: Analogic control signal

Thanyou for your answer, we find in this link the posibility to use the debug header as an 8-bit outut without modify the reference model using the WARPLAB 5.2.

https://warpproject.org/forums/viewtopic.php?id=1198

"-The WARPLab v5.2 ref design includes an xps_gpio core named debug_sw_gpio, with an 8-bit output mapped to pins 8:15 of the FPGA Board's debug header (debug_sw_gpio.debug_sw_gpio_O is tied to bits 8:15 of the top level output port 'debug', which is mapped to the debug header in the UCF). You don't need to modify the MHS, MSS or UCF files."

Is it posible to download this reference model? We dont find it in the downloads section. This would be very helfull cause we dont know how to modify the reference model with XPS.

Thanks for your support.

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#4 2017-Oct-25 13:44:01

murphpo
Administrator
From: Mango Communications
Registered: 2006-Jul-03
Posts: 5159

Re: Analogic control signal

No, WARPLab 5.2 was never supported on WARP v3 hardware. You should use the latest reference design for any new projects.

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