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Hi, currently I am working on the updates on physical layer with updates on the system generator model. However every time when I update the pcore and export the hardware to SDK, the generation time for .bit files takes up to 7 hours to generate, which is too long when comes to debugging the design. Does any of you guys has encounter this issue? Is there any good solutions to speed up the process?
Thanks
Ruirong Chen
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Re-running implementation for 802.11 Reference Design hardware will always be a lengthy process. It's a big design and the Xilinx ISE tools are not especially speedy. The implementation time is dominated by the CPU speed and available memory on your PC. On my PC (4GHz i7-6700K CPU, 32GB RAM) it takes about 1.5 hours to re-run implementation in XPS after small modifications to the Rx PHY pcore. The run time increases with more substantial changes (XPS re-uses synthesis outputs for cores that don't change between builds).
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